0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2012 Freescale Semiconductor, Inc.
0004 // Copyright 2011 Linaro Ltd.
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/input.h>
0008
0009 / {
0010 chosen {
0011 stdout-path = &uart4;
0012 };
0013
0014 memory@10000000 {
0015 device_type = "memory";
0016 reg = <0x10000000 0x80000000>;
0017 };
0018
0019 leds {
0020 compatible = "gpio-leds";
0021 pinctrl-names = "default";
0022 pinctrl-0 = <&pinctrl_gpio_leds>;
0023
0024 user {
0025 label = "debug";
0026 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
0027 };
0028 };
0029
0030 gpio-keys {
0031 compatible = "gpio-keys";
0032 pinctrl-names = "default";
0033 pinctrl-0 = <&pinctrl_gpio_keys>;
0034
0035 home {
0036 label = "Home";
0037 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
0038 linux,code = <KEY_HOME>;
0039 wakeup-source;
0040 };
0041
0042 back {
0043 label = "Back";
0044 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0045 linux,code = <KEY_BACK>;
0046 wakeup-source;
0047 };
0048
0049 program {
0050 label = "Program";
0051 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0052 linux,code = <KEY_PROGRAM>;
0053 wakeup-source;
0054 };
0055
0056 volume-up {
0057 label = "Volume Up";
0058 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
0059 linux,code = <KEY_VOLUMEUP>;
0060 wakeup-source;
0061 };
0062
0063 volume-down {
0064 label = "Volume Down";
0065 gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
0066 linux,code = <KEY_VOLUMEDOWN>;
0067 wakeup-source;
0068 };
0069 };
0070
0071 clocks {
0072 codec_osc: anaclk2 {
0073 compatible = "fixed-clock";
0074 #clock-cells = <0>;
0075 clock-frequency = <24576000>;
0076 };
0077 };
0078
0079 reg_audio: regulator-audio {
0080 compatible = "regulator-fixed";
0081 regulator-name = "cs42888_supply";
0082 regulator-min-microvolt = <3300000>;
0083 regulator-max-microvolt = <3300000>;
0084 regulator-always-on;
0085 };
0086
0087 reg_usb_h1_vbus: regulator-usb-h1-vbus {
0088 compatible = "regulator-fixed";
0089 regulator-name = "usb_h1_vbus";
0090 regulator-min-microvolt = <5000000>;
0091 regulator-max-microvolt = <5000000>;
0092 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
0093 enable-active-high;
0094 };
0095
0096 reg_usb_otg_vbus: regulator-usb-otg-vbus {
0097 compatible = "regulator-fixed";
0098 regulator-name = "usb_otg_vbus";
0099 regulator-min-microvolt = <5000000>;
0100 regulator-max-microvolt = <5000000>;
0101 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
0102 enable-active-high;
0103 };
0104
0105 reg_can_en: regulator-can-en {
0106 compatible = "regulator-fixed";
0107 regulator-name = "can-en";
0108 regulator-min-microvolt = <3300000>;
0109 regulator-max-microvolt = <3300000>;
0110 gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
0111 enable-active-high;
0112 };
0113
0114 reg_can_stby: regulator-can-stby {
0115 compatible = "regulator-fixed";
0116 regulator-name = "can-stby";
0117 regulator-min-microvolt = <3300000>;
0118 regulator-max-microvolt = <3300000>;
0119 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
0120 enable-active-high;
0121 vin-supply = <®_can_en>;
0122 };
0123
0124 sound-cs42888 {
0125 compatible = "fsl,imx6-sabreauto-cs42888",
0126 "fsl,imx-audio-cs42888";
0127 model = "imx-cs42888";
0128 audio-cpu = <&esai>;
0129 audio-asrc = <&asrc>;
0130 audio-codec = <&codec>;
0131 audio-routing =
0132 "Line Out Jack", "AOUT1L",
0133 "Line Out Jack", "AOUT1R",
0134 "Line Out Jack", "AOUT2L",
0135 "Line Out Jack", "AOUT2R",
0136 "Line Out Jack", "AOUT3L",
0137 "Line Out Jack", "AOUT3R",
0138 "Line Out Jack", "AOUT4L",
0139 "Line Out Jack", "AOUT4R",
0140 "AIN1L", "Line In Jack",
0141 "AIN1R", "Line In Jack",
0142 "AIN2L", "Line In Jack",
0143 "AIN2R", "Line In Jack";
0144 };
0145
0146 sound-spdif {
0147 compatible = "fsl,imx-audio-spdif",
0148 "fsl,imx-sabreauto-spdif";
0149 model = "imx-spdif";
0150 spdif-controller = <&spdif>;
0151 spdif-in;
0152 };
0153
0154 backlight {
0155 compatible = "pwm-backlight";
0156 pwms = <&pwm3 0 5000000>;
0157 brightness-levels = <0 4 8 16 32 64 128 255>;
0158 default-brightness-level = <7>;
0159 status = "okay";
0160 };
0161
0162 i2cmux {
0163 compatible = "i2c-mux-gpio";
0164 #address-cells = <1>;
0165 #size-cells = <0>;
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&pinctrl_i2c3mux>;
0168 mux-gpios = <&gpio5 4 0>;
0169 i2c-parent = <&i2c3>;
0170 idle-state = <0>;
0171
0172 i2c@1 {
0173 #address-cells = <1>;
0174 #size-cells = <0>;
0175 reg = <1>;
0176
0177 adv7180: camera@21 {
0178 compatible = "adi,adv7180";
0179 reg = <0x21>;
0180 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
0181 interrupt-parent = <&gpio1>;
0182 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
0183
0184 port {
0185 adv7180_to_ipu1_csi0_mux: endpoint {
0186 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
0187 bus-width = <8>;
0188 };
0189 };
0190 };
0191
0192 max7310_a: gpio@30 {
0193 compatible = "maxim,max7310";
0194 reg = <0x30>;
0195 gpio-controller;
0196 #gpio-cells = <2>;
0197 };
0198
0199 max7310_b: gpio@32 {
0200 compatible = "maxim,max7310";
0201 reg = <0x32>;
0202 gpio-controller;
0203 #gpio-cells = <2>;
0204 pinctrl-names = "default";
0205 pinctrl-0 = <&pinctrl_max7310>;
0206 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
0207 };
0208
0209 max7310_c: gpio@34 {
0210 compatible = "maxim,max7310";
0211 reg = <0x34>;
0212 gpio-controller;
0213 #gpio-cells = <2>;
0214 };
0215
0216 light-sensor@44 {
0217 compatible = "isil,isl29023";
0218 reg = <0x44>;
0219 interrupt-parent = <&gpio5>;
0220 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
0221 };
0222
0223 magnetometer@e {
0224 compatible = "fsl,mag3110";
0225 reg = <0x0e>;
0226 interrupt-parent = <&gpio2>;
0227 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
0228 };
0229
0230 accelerometer@1c {
0231 compatible = "fsl,mma8451";
0232 reg = <0x1c>;
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&pinctrl_mma8451_int>;
0235 interrupt-parent = <&gpio6>;
0236 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
0237 };
0238 };
0239 };
0240 };
0241
0242 &ipu1_csi0_from_ipu1_csi0_mux {
0243 bus-width = <8>;
0244 };
0245
0246 &ipu1_csi0_mux_from_parallel_sensor {
0247 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
0248 bus-width = <8>;
0249 };
0250
0251 &ipu1_csi0 {
0252 pinctrl-names = "default";
0253 pinctrl-0 = <&pinctrl_ipu1_csi0>;
0254 };
0255
0256 &clks {
0257 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
0258 <&clks IMX6QDL_PLL4_BYPASS>,
0259 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
0260 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
0261 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
0262 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
0263 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
0264 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
0265 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
0266 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
0267 };
0268
0269 &ecspi1 {
0270 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
0271 pinctrl-names = "default";
0272 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
0273 status = "disabled"; /* pin conflict with WEIM NOR */
0274
0275 flash: flash@0 {
0276 #address-cells = <1>;
0277 #size-cells = <1>;
0278 compatible = "st,m25p32", "jedec,spi-nor";
0279 spi-max-frequency = <20000000>;
0280 reg = <0>;
0281 };
0282 };
0283
0284 &esai {
0285 pinctrl-names = "default";
0286 pinctrl-0 = <&pinctrl_esai>;
0287 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
0288 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
0289 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
0290 assigned-clock-rates = <0>, <24576000>;
0291 status = "okay";
0292 };
0293
0294 &fec {
0295 pinctrl-names = "default";
0296 pinctrl-0 = <&pinctrl_enet>;
0297 phy-mode = "rgmii-id";
0298 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
0299 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
0300 fsl,err006687-workaround-present;
0301 fsl,magic-packet;
0302 status = "okay";
0303 };
0304
0305 &can1 {
0306 pinctrl-names = "default";
0307 pinctrl-0 = <&pinctrl_flexcan1>;
0308 xceiver-supply = <®_can_stby>;
0309 status = "disabled"; /* pin conflict with fec */
0310 };
0311
0312 &can2 {
0313 pinctrl-names = "default";
0314 pinctrl-0 = <&pinctrl_flexcan2>;
0315 xceiver-supply = <®_can_stby>;
0316 status = "okay";
0317 };
0318
0319 &gpmi {
0320 pinctrl-names = "default";
0321 pinctrl-0 = <&pinctrl_gpmi_nand>;
0322 status = "okay";
0323 };
0324
0325 &hdmi {
0326 pinctrl-names = "default";
0327 pinctrl-0 = <&pinctrl_hdmi_cec>;
0328 ddc-i2c-bus = <&i2c2>;
0329 status = "okay";
0330 };
0331
0332 &i2c2 {
0333 clock-frequency = <100000>;
0334 pinctrl-names = "default";
0335 pinctrl-0 = <&pinctrl_i2c2>;
0336 status = "okay";
0337
0338 pmic: pfuze100@8 {
0339 compatible = "fsl,pfuze100";
0340 reg = <0x08>;
0341
0342 regulators {
0343 sw1a_reg: sw1ab {
0344 regulator-min-microvolt = <300000>;
0345 regulator-max-microvolt = <1875000>;
0346 regulator-boot-on;
0347 regulator-always-on;
0348 regulator-ramp-delay = <6250>;
0349 };
0350
0351 sw1c_reg: sw1c {
0352 regulator-min-microvolt = <300000>;
0353 regulator-max-microvolt = <1875000>;
0354 regulator-boot-on;
0355 regulator-always-on;
0356 regulator-ramp-delay = <6250>;
0357 };
0358
0359 sw2_reg: sw2 {
0360 regulator-min-microvolt = <800000>;
0361 regulator-max-microvolt = <3300000>;
0362 regulator-boot-on;
0363 regulator-always-on;
0364 };
0365
0366 sw3a_reg: sw3a {
0367 regulator-min-microvolt = <400000>;
0368 regulator-max-microvolt = <1975000>;
0369 regulator-boot-on;
0370 regulator-always-on;
0371 };
0372
0373 sw3b_reg: sw3b {
0374 regulator-min-microvolt = <400000>;
0375 regulator-max-microvolt = <1975000>;
0376 regulator-boot-on;
0377 regulator-always-on;
0378 };
0379
0380 sw4_reg: sw4 {
0381 regulator-min-microvolt = <800000>;
0382 regulator-max-microvolt = <3300000>;
0383 };
0384
0385 swbst_reg: swbst {
0386 regulator-min-microvolt = <5000000>;
0387 regulator-max-microvolt = <5150000>;
0388 };
0389
0390 snvs_reg: vsnvs {
0391 regulator-min-microvolt = <1000000>;
0392 regulator-max-microvolt = <3000000>;
0393 regulator-boot-on;
0394 regulator-always-on;
0395 };
0396
0397 vref_reg: vrefddr {
0398 regulator-boot-on;
0399 regulator-always-on;
0400 };
0401
0402 vgen1_reg: vgen1 {
0403 regulator-min-microvolt = <800000>;
0404 regulator-max-microvolt = <1550000>;
0405 };
0406
0407 vgen2_reg: vgen2 {
0408 regulator-min-microvolt = <800000>;
0409 regulator-max-microvolt = <1550000>;
0410 };
0411
0412 vgen3_reg: vgen3 {
0413 regulator-min-microvolt = <1800000>;
0414 regulator-max-microvolt = <3300000>;
0415 };
0416
0417 vgen4_reg: vgen4 {
0418 regulator-min-microvolt = <1800000>;
0419 regulator-max-microvolt = <3300000>;
0420 regulator-always-on;
0421 };
0422
0423 vgen5_reg: vgen5 {
0424 regulator-min-microvolt = <1800000>;
0425 regulator-max-microvolt = <3300000>;
0426 regulator-always-on;
0427 };
0428
0429 vgen6_reg: vgen6 {
0430 regulator-min-microvolt = <1800000>;
0431 regulator-max-microvolt = <3300000>;
0432 regulator-always-on;
0433 };
0434 };
0435 };
0436
0437 codec: cs42888@48 {
0438 compatible = "cirrus,cs42888";
0439 reg = <0x48>;
0440 clocks = <&codec_osc>;
0441 clock-names = "mclk";
0442 VA-supply = <®_audio>;
0443 VD-supply = <®_audio>;
0444 VLS-supply = <®_audio>;
0445 VLC-supply = <®_audio>;
0446 };
0447
0448 touchscreen@4 {
0449 compatible = "eeti,egalax_ts";
0450 reg = <0x04>;
0451 pinctrl-names = "default";
0452 pinctrl-0 = <&pinctrl_egalax_int>;
0453 interrupt-parent = <&gpio2>;
0454 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
0455 wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
0456 };
0457 };
0458
0459 &i2c3 {
0460 pinctrl-names = "default";
0461 pinctrl-0 = <&pinctrl_i2c3>;
0462 status = "okay";
0463 };
0464
0465 &iomuxc {
0466 pinctrl-names = "default";
0467 pinctrl-0 = <&pinctrl_hog>;
0468
0469 imx6qdl-sabreauto {
0470 pinctrl_hog: hoggrp {
0471 fsl,pins = <
0472 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
0473 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
0474 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
0475 >;
0476 };
0477
0478 pinctrl_ecspi1: ecspi1grp {
0479 fsl,pins = <
0480 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0481 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
0482 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
0483 >;
0484 };
0485
0486 pinctrl_ecspi1_cs: ecspi1cs {
0487 fsl,pins = <
0488 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
0489 >;
0490 };
0491
0492 pinctrl_egalax_int: egalax-intgrp {
0493 fsl,pins = <
0494 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
0495 >;
0496 };
0497
0498 pinctrl_enet: enetgrp {
0499 fsl,pins = <
0500 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
0501 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
0502 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0503 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0504 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0505 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0506 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0507 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0508 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0509 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0510 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0511 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0512 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0513 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0514 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0515 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
0516 >;
0517 };
0518
0519 pinctrl_esai: esaigrp {
0520 fsl,pins = <
0521 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
0522 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
0523 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
0524 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
0525 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
0526 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
0527 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
0528 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
0529 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
0530 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
0531 >;
0532 };
0533
0534 pinctrl_flexcan1: flexcan1grp {
0535 fsl,pins = <
0536 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059
0537 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059
0538 >;
0539 };
0540
0541 pinctrl_flexcan2: flexcan2grp {
0542 fsl,pins = <
0543 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059
0544 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059
0545 >;
0546 };
0547
0548 pinctrl_gpio_keys: gpiokeysgrp {
0549 fsl,pins = <
0550 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
0551 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
0552 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
0553 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
0554 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
0555 >;
0556 };
0557
0558 pinctrl_gpio_leds: gpioledsgrp {
0559 fsl,pins = <
0560 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
0561 >;
0562 };
0563
0564 pinctrl_gpmi_nand: gpminandgrp {
0565 fsl,pins = <
0566 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0567 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0568 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
0569 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0570 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0571 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
0572 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0573 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0574 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0575 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0576 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0577 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0578 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0579 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0580 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0581 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0582 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
0583 >;
0584 };
0585
0586 pinctrl_hdmi_cec: hdmicecgrp {
0587 fsl,pins = <
0588 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
0589 >;
0590 };
0591
0592 pinctrl_i2c2: i2c2grp {
0593 fsl,pins = <
0594 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
0595 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0596 >;
0597 };
0598
0599 pinctrl_i2c3: i2c3grp {
0600 fsl,pins = <
0601 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
0602 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
0603 >;
0604 };
0605
0606 pinctrl_i2c3mux: i2c3muxgrp {
0607 fsl,pins = <
0608 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
0609 >;
0610 };
0611
0612 pinctrl_ipu1_csi0: ipu1csi0grp {
0613 fsl,pins = <
0614 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
0615 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
0616 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
0617 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
0618 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
0619 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
0620 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
0621 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
0622 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
0623 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
0624 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
0625 >;
0626 };
0627
0628 pinctrl_max7310: max7310grp {
0629 fsl,pins = <
0630 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
0631 >;
0632 };
0633
0634 pinctrl_mma8451_int: mma8451intgrp {
0635 fsl,pins = <
0636 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1
0637 >;
0638 };
0639
0640 pinctrl_pwm3: pwm1grp {
0641 fsl,pins = <
0642 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
0643 >;
0644 };
0645
0646 pinctrl_gpt_input_capture0: gptinputcapture0grp {
0647 fsl,pins = <
0648 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
0649 >;
0650 };
0651
0652 pinctrl_gpt_input_capture1: gptinputcapture1grp {
0653 fsl,pins = <
0654 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
0655 >;
0656 };
0657
0658 pinctrl_spdif: spdifgrp {
0659 fsl,pins = <
0660 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
0661 >;
0662 };
0663
0664 pinctrl_uart4: uart4grp {
0665 fsl,pins = <
0666 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
0667 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
0668 >;
0669 };
0670
0671 pinctrl_usbotg: usbotggrp {
0672 fsl,pins = <
0673 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
0674 >;
0675 };
0676
0677 pinctrl_usdhc3: usdhc3grp {
0678 fsl,pins = <
0679 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0680 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0681 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0682 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0683 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0684 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0685 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
0686 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
0687 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
0688 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
0689 >;
0690 };
0691
0692 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
0693 fsl,pins = <
0694 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
0695 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
0696 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
0697 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
0698 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
0699 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
0700 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
0701 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
0702 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
0703 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
0704 >;
0705 };
0706
0707 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
0708 fsl,pins = <
0709 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
0710 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
0711 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
0712 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
0713 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
0714 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
0715 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
0716 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
0717 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
0718 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
0719 >;
0720 };
0721
0722 pinctrl_weim_cs0: weimcs0grp {
0723 fsl,pins = <
0724 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
0725 >;
0726 };
0727
0728 pinctrl_weim_nor: weimnorgrp {
0729 fsl,pins = <
0730 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
0731 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
0732 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
0733 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
0734 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
0735 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
0736 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
0737 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
0738 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
0739 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
0740 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
0741 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
0742 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
0743 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
0744 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
0745 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
0746 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
0747 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
0748 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
0749 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
0750 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
0751 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
0752 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
0753 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
0754 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
0755 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
0756 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
0757 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
0758 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
0759 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
0760 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
0761 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
0762 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
0763 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
0764 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
0765 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
0766 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
0767 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
0768 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
0769 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
0770 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
0771 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
0772 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
0773 >;
0774 };
0775 };
0776 };
0777
0778 &ldb {
0779 status = "okay";
0780
0781 lvds-channel@0 {
0782 fsl,data-mapping = "spwg";
0783 fsl,data-width = <18>;
0784 status = "okay";
0785
0786 display-timings {
0787 native-mode = <&timing0>;
0788 timing0: hsd100pxn1 {
0789 clock-frequency = <65000000>;
0790 hactive = <1024>;
0791 vactive = <768>;
0792 hback-porch = <220>;
0793 hfront-porch = <40>;
0794 vback-porch = <21>;
0795 vfront-porch = <7>;
0796 hsync-len = <60>;
0797 vsync-len = <10>;
0798 };
0799 };
0800 };
0801 };
0802
0803 &pwm3 {
0804 #pwm-cells = <2>;
0805 pinctrl-names = "default";
0806 pinctrl-0 = <&pinctrl_pwm3>;
0807 status = "okay";
0808 };
0809
0810 &pcie {
0811 status = "okay";
0812 };
0813
0814 &spdif {
0815 pinctrl-names = "default";
0816 pinctrl-0 = <&pinctrl_spdif>;
0817 status = "okay";
0818 };
0819
0820 &uart4 {
0821 pinctrl-names = "default";
0822 pinctrl-0 = <&pinctrl_uart4>;
0823 status = "okay";
0824 };
0825
0826 &usbh1 {
0827 vbus-supply = <®_usb_h1_vbus>;
0828 status = "okay";
0829 };
0830
0831 &usbotg {
0832 vbus-supply = <®_usb_otg_vbus>;
0833 pinctrl-names = "default";
0834 pinctrl-0 = <&pinctrl_usbotg>;
0835 status = "okay";
0836 };
0837
0838 &usdhc3 {
0839 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0840 pinctrl-0 = <&pinctrl_usdhc3>;
0841 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0842 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0843 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
0844 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
0845 status = "okay";
0846 };
0847
0848 &weim {
0849 pinctrl-names = "default";
0850 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
0851 ranges = <0 0 0x08000000 0x08000000>;
0852 status = "disabled"; /* pin conflict with SPI NOR */
0853
0854 nor@0,0 {
0855 compatible = "cfi-flash";
0856 reg = <0 0 0x02000000>;
0857 #address-cells = <1>;
0858 #size-cells = <1>;
0859 bank-width = <2>;
0860 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0861 0x0000c000 0x1404a38e 0x00000000>;
0862 };
0863 };
