0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
0004 * Author: Christian Hemp <c.hemp@phytec.de>
0005 */
0006
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/regulator/dlg,da9063-regulator.h>
0009
0010 / {
0011 aliases {
0012 rtc1 = &da9062_rtc;
0013 rtc2 = &snvs_rtc;
0014 };
0015
0016 /*
0017 * Set the minimum memory size here and
0018 * let the bootloader set the real size.
0019 */
0020 memory@10000000 {
0021 device_type = "memory";
0022 reg = <0x10000000 0x8000000>;
0023 };
0024
0025 gpio_leds_som: somleds {
0026 compatible = "gpio-leds";
0027 pinctrl-names = "default";
0028 pinctrl-0 = <&pinctrl_gpioleds_som>;
0029
0030 som-led-green {
0031 label = "phycore:green";
0032 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
0033 linux,default-trigger = "heartbeat";
0034 };
0035 };
0036 };
0037
0038 &ecspi1 {
0039 pinctrl-names = "default";
0040 pinctrl-0 = <&pinctrl_ecspi1>;
0041 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
0042 status = "okay";
0043
0044 m25p80: flash@0 {
0045 compatible = "jedec,spi-nor";
0046 spi-max-frequency = <20000000>;
0047 reg = <0>;
0048 status = "disabled";
0049 };
0050 };
0051
0052 &fec {
0053 pinctrl-names = "default";
0054 pinctrl-0 = <&pinctrl_enet>;
0055 phy-handle = <ðphy>;
0056 phy-mode = "rgmii";
0057 phy-supply = <&vdd_eth_io>;
0058 phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
0059 status = "disabled";
0060
0061 mdio {
0062 #address-cells = <1>;
0063 #size-cells = <0>;
0064
0065 ethphy: ethernet-phy@3 {
0066 reg = <3>;
0067 txc-skew-ps = <1680>;
0068 rxc-skew-ps = <1860>;
0069 };
0070 };
0071 };
0072
0073 &gpmi {
0074 pinctrl-names = "default";
0075 pinctrl-0 = <&pinctrl_gpmi_nand>;
0076 nand-on-flash-bbt;
0077 status = "disabled";
0078 };
0079
0080 &i2c3 {
0081 pinctrl-names = "default", "gpio";
0082 pinctrl-0 = <&pinctrl_i2c3>;
0083 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0084 scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0085 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0086 clock-frequency = <400000>;
0087 status = "okay";
0088
0089 eeprom@50 {
0090 compatible = "st,24c32", "atmel,24c32";
0091 pagesize = <32>;
0092 reg = <0x50>;
0093 };
0094
0095 pmic: pmic@58 {
0096 compatible = "dlg,da9062";
0097 pinctrl-names = "default";
0098 pinctrl-0 = <&pinctrl_pmic>;
0099 reg = <0x58>;
0100 interrupt-parent = <&gpio1>;
0101 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0102 interrupt-controller;
0103 gpio-controller;
0104 #gpio-cells = <2>;
0105
0106 da9062_rtc: rtc {
0107 compatible = "dlg,da9062-rtc";
0108 };
0109
0110 da9062_onkey: onkey {
0111 compatible = "dlg,da9062-onkey";
0112 };
0113
0114 watchdog {
0115 compatible = "dlg,da9062-watchdog";
0116 dlg,use-sw-pm;
0117 };
0118
0119 thermal {
0120 compatible = "dlg,da9062-thermal";
0121 status = "disabled";
0122 };
0123
0124 gpio {
0125 compatible = "dlg,da9062-gpio";
0126 status = "disabled";
0127 };
0128
0129 regulators {
0130 vdd_arm: buck1 {
0131 regulator-name = "vdd_arm";
0132 regulator-min-microvolt = <925000>;
0133 regulator-max-microvolt = <1380000>;
0134 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
0135 regulator-always-on;
0136 };
0137
0138 vdd_soc: buck2 {
0139 regulator-name = "vdd_soc";
0140 regulator-min-microvolt = <1150000>;
0141 regulator-max-microvolt = <1380000>;
0142 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
0143 regulator-always-on;
0144 };
0145
0146 vdd_ddr3_1p5: buck3 {
0147 regulator-name = "vdd_ddr3";
0148 regulator-min-microvolt = <1500000>;
0149 regulator-max-microvolt = <1500000>;
0150 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
0151 regulator-always-on;
0152 };
0153
0154 vdd_eth_1p2: buck4 {
0155 regulator-name = "vdd_eth";
0156 regulator-min-microvolt = <1200000>;
0157 regulator-max-microvolt = <1200000>;
0158 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
0159 regulator-always-on;
0160 };
0161
0162 vdd_snvs: ldo1 {
0163 regulator-name = "vdd_snvs";
0164 regulator-min-microvolt = <3000000>;
0165 regulator-max-microvolt = <3000000>;
0166 regulator-always-on;
0167 };
0168
0169 vdd_high: ldo2 {
0170 regulator-name = "vdd_high";
0171 regulator-min-microvolt = <3000000>;
0172 regulator-max-microvolt = <3000000>;
0173 regulator-always-on;
0174 };
0175
0176 vdd_eth_io: ldo3 {
0177 regulator-name = "vdd_eth_io";
0178 regulator-min-microvolt = <2500000>;
0179 regulator-max-microvolt = <2500000>;
0180 };
0181
0182 vdd_emmc_1p8: ldo4 {
0183 regulator-name = "vdd_emmc";
0184 regulator-min-microvolt = <1800000>;
0185 regulator-max-microvolt = <1800000>;
0186 };
0187 };
0188 };
0189 };
0190
0191 ®_arm {
0192 vin-supply = <&vdd_arm>;
0193 };
0194
0195 ®_pu {
0196 vin-supply = <&vdd_soc>;
0197 };
0198
0199 ®_soc {
0200 vin-supply = <&vdd_soc>;
0201 };
0202
0203 &snvs_poweroff {
0204 status = "okay";
0205 };
0206
0207 &usdhc4 {
0208 pinctrl-names = "default";
0209 pinctrl-0 = <&pinctrl_usdhc4>;
0210 bus-width = <8>;
0211 non-removable;
0212 status = "disabled";
0213 };
0214
0215 &iomuxc {
0216 pinctrl_enet: enetgrp {
0217 fsl,pins = <
0218 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0219 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0220 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
0221 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
0222 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
0223 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
0224 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
0225 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
0226 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0227 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
0228 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
0229 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
0230 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
0231 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
0232 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
0233 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
0234 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
0235 >;
0236 };
0237
0238 pinctrl_gpioleds_som: gpioledssomgrp {
0239 fsl,pins = <
0240 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
0241 >;
0242 };
0243
0244 pinctrl_gpmi_nand: gpminandgrp {
0245 fsl,pins = <
0246 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0247 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0248 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
0249 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0250 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0251 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
0252 MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
0253 MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
0254 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0255 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0256 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0257 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0258 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0259 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0260 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0261 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0262 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0263 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0264 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
0265 >;
0266 };
0267
0268 pinctrl_i2c3: i2c3grp {
0269 fsl,pins = <
0270 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0271 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
0272 >;
0273 };
0274
0275 pinctrl_i2c3_gpio: i2c3gpiogrp {
0276 fsl,pins = <
0277 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
0278 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
0279 >;
0280 };
0281
0282 pinctrl_ecspi1: ecspi1grp {
0283 fsl,pins = <
0284 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
0285 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0286 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
0287 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
0288 >;
0289 };
0290
0291 pinctrl_pmic: pmicgrp {
0292 fsl,pins = <
0293 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
0294 >;
0295 };
0296
0297 pinctrl_usdhc4: usdhc4grp {
0298 fsl,pins = <
0299 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
0300 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
0301 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
0302 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
0303 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
0304 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
0305 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
0306 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
0307 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
0308 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
0309 >;
0310 };
0311 };
