0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007
0008 / {
0009 model = "Phytec phyFLEX-i.MX6 Quad";
0010 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
0011
0012 memory@10000000 {
0013 device_type = "memory";
0014 reg = <0x10000000 0x80000000>;
0015 };
0016
0017 regulators {
0018 compatible = "simple-bus";
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021
0022 reg_usb_otg_vbus: regulator@0 {
0023 compatible = "regulator-fixed";
0024 reg = <0>;
0025 regulator-name = "usb_otg_vbus";
0026 regulator-min-microvolt = <5000000>;
0027 regulator-max-microvolt = <5000000>;
0028 gpio = <&gpio4 15 0>;
0029 enable-active-high;
0030 };
0031
0032 reg_usb_h1_vbus: regulator@1 {
0033 compatible = "regulator-fixed";
0034 pinctrl-names = "default";
0035 pinctrl-0 = <&pinctrl_usbh1_vbus>;
0036 reg = <1>;
0037 regulator-name = "usb_h1_vbus";
0038 regulator-min-microvolt = <5000000>;
0039 regulator-max-microvolt = <5000000>;
0040 gpio = <&gpio1 0 0>;
0041 enable-active-high;
0042 };
0043 };
0044
0045 gpio_leds: leds {
0046 pinctrl-names = "default";
0047 pinctrl-0 = <&pinctrl_leds>;
0048 compatible = "gpio-leds";
0049
0050 led_green: green {
0051 label = "phyflex:green";
0052 gpios = <&gpio1 30 0>;
0053 };
0054
0055 led_red: red {
0056 label = "phyflex:red";
0057 gpios = <&gpio2 31 0>;
0058 };
0059 };
0060 };
0061
0062 &audmux {
0063 pinctrl-names = "default";
0064 pinctrl-0 = <&pinctrl_audmux>;
0065 status = "disabled";
0066 };
0067
0068 &can1 {
0069 pinctrl-names = "default";
0070 pinctrl-0 = <&pinctrl_flexcan1>;
0071 status = "disabled";
0072 };
0073
0074 &ecspi3 {
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_ecspi3>;
0077 status = "okay";
0078 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
0079
0080 som_flash: flash@0 {
0081 compatible = "m25p80", "jedec,spi-nor";
0082 spi-max-frequency = <20000000>;
0083 reg = <0>;
0084 };
0085 };
0086
0087 &fec {
0088 pinctrl-names = "default";
0089 pinctrl-0 = <&pinctrl_enet>;
0090 phy-handle = <ðphy>;
0091 phy-mode = "rgmii";
0092 phy-reset-duration = <10>; /* in msecs */
0093 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
0094 phy-supply = <&vdd_eth_io_reg>;
0095 status = "disabled";
0096
0097 fec_mdio: mdio {
0098 #address-cells = <1>;
0099 #size-cells = <0>;
0100
0101 ethphy: ethernet-phy@0 {
0102 compatible = "ethernet-phy-ieee802.3-c22";
0103 reg = <0>;
0104 txc-skew-ps = <1680>;
0105 rxc-skew-ps = <1860>;
0106 };
0107 };
0108 };
0109
0110 &gpmi {
0111 pinctrl-names = "default";
0112 pinctrl-0 = <&pinctrl_gpmi_nand>;
0113 nand-on-flash-bbt;
0114 status = "okay";
0115 };
0116
0117 &i2c1 {
0118 pinctrl-names = "default";
0119 pinctrl-0 = <&pinctrl_i2c1>;
0120 status = "okay";
0121
0122 som_eeprom: eeprom@50 {
0123 compatible = "catalyst,24c32", "atmel,24c32";
0124 pagesize = <32>;
0125 reg = <0x50>;
0126 };
0127
0128 pmic@58 {
0129 pinctrl-names = "default";
0130 pinctrl-0 = <&pinctrl_pmic>;
0131 compatible = "dlg,da9063";
0132 reg = <0x58>;
0133 interrupt-parent = <&gpio2>;
0134 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
0135 interrupt-controller;
0136
0137 regulators {
0138 vddcore_reg: bcore1 {
0139 regulator-min-microvolt = <730000>;
0140 regulator-max-microvolt = <1380000>;
0141 regulator-always-on;
0142 };
0143
0144 vddsoc_reg: bcore2 {
0145 regulator-min-microvolt = <730000>;
0146 regulator-max-microvolt = <1380000>;
0147 regulator-always-on;
0148 };
0149
0150 vdd_ddr3_reg: bpro {
0151 regulator-min-microvolt = <1500000>;
0152 regulator-max-microvolt = <1500000>;
0153 regulator-always-on;
0154 };
0155
0156 vdd_3v3_reg: bperi {
0157 regulator-min-microvolt = <3300000>;
0158 regulator-max-microvolt = <3300000>;
0159 regulator-always-on;
0160 };
0161
0162 vdd_buckmem_reg: bmem {
0163 regulator-min-microvolt = <3300000>;
0164 regulator-max-microvolt = <3300000>;
0165 regulator-always-on;
0166 };
0167
0168 vdd_eth_reg: bio {
0169 regulator-min-microvolt = <1200000>;
0170 regulator-max-microvolt = <1200000>;
0171 regulator-always-on;
0172 };
0173
0174 vdd_eth_io_reg: ldo4 {
0175 regulator-min-microvolt = <2500000>;
0176 regulator-max-microvolt = <2500000>;
0177 regulator-always-on;
0178 };
0179
0180 vdd_mx6_snvs_reg: ldo5 {
0181 regulator-min-microvolt = <3000000>;
0182 regulator-max-microvolt = <3000000>;
0183 regulator-always-on;
0184 };
0185
0186 vdd_3v3_pmic_io_reg: ldo6 {
0187 regulator-min-microvolt = <3300000>;
0188 regulator-max-microvolt = <3300000>;
0189 regulator-always-on;
0190 };
0191
0192 vdd_sd0_reg: ldo9 {
0193 regulator-min-microvolt = <3300000>;
0194 regulator-max-microvolt = <3300000>;
0195 };
0196
0197 vdd_sd1_reg: ldo10 {
0198 regulator-min-microvolt = <3300000>;
0199 regulator-max-microvolt = <3300000>;
0200 };
0201
0202 vdd_mx6_high_reg: ldo11 {
0203 regulator-min-microvolt = <3000000>;
0204 regulator-max-microvolt = <3000000>;
0205 regulator-always-on;
0206 };
0207 };
0208
0209 da9063_rtc: rtc {
0210 compatible = "dlg,da9063-rtc";
0211 };
0212
0213 da9063_wdog: watchdog {
0214 compatible = "dlg,da9063-watchdog";
0215 };
0216
0217 onkey {
0218 compatible = "dlg,da9063-onkey";
0219 status = "disabled";
0220 };
0221 };
0222 };
0223
0224 &i2c2 {
0225 pinctrl-names = "default";
0226 pinctrl-0 = <&pinctrl_i2c2>;
0227 clock-frequency = <100000>;
0228 };
0229
0230 &i2c3 {
0231 pinctrl-names = "default";
0232 pinctrl-0 = <&pinctrl_i2c3>;
0233 clock-frequency = <100000>;
0234 };
0235
0236 &iomuxc {
0237 imx6q-phytec-pfla02 {
0238 pinctrl_ecspi3: ecspi3grp {
0239 fsl,pins = <
0240 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
0241 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
0242 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
0243 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */
0244 >;
0245 };
0246
0247 pinctrl_enet: enetgrp {
0248 fsl,pins = <
0249 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0250 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0251 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0252 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0253 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0254 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0255 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0256 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0257 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0258 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0259 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0260 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0261 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0262 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0263 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0264 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
0265 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */
0266 >;
0267 };
0268
0269 pinctrl_flexcan1: flexcan1grp {
0270 fsl,pins = <
0271 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
0272 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
0273 >;
0274 };
0275
0276 pinctrl_gpmi_nand: gpminandgrp {
0277 fsl,pins = <
0278 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0279 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0280 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
0281 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0282 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0283 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
0284 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0285 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0286 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0287 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0288 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0289 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0290 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0291 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0292 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0293 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0294 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
0295 >;
0296 };
0297
0298 pinctrl_i2c1: i2c1grp {
0299 fsl,pins = <
0300 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
0301 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
0302 >;
0303 };
0304
0305 pinctrl_i2c2: i2c2grp {
0306 fsl,pins = <
0307 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
0308 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
0309 >;
0310 };
0311
0312 pinctrl_i2c3: i2c3grp {
0313 fsl,pins = <
0314 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
0315 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
0316 >;
0317 };
0318
0319 pinctrl_leds: ledsgrp {
0320 fsl,pins = <
0321 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
0322 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
0323 >;
0324 };
0325
0326 pinctrl_pcie: pciegrp {
0327 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
0328 };
0329
0330 pinctrl_pmic: pmicgrp {
0331 fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */
0332 };
0333
0334 pinctrl_uart3: uart3grp {
0335 fsl,pins = <
0336 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
0337 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
0338 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
0339 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
0340 >;
0341 };
0342
0343 pinctrl_uart4: uart4grp {
0344 fsl,pins = <
0345 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
0346 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
0347 >;
0348 };
0349
0350 pinctrl_usbh1_vbus: usbh1vbusgrp {
0351 fsl,pins = <
0352 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
0353 >;
0354 };
0355
0356 pinctrl_usbotg: usbotggrp {
0357 fsl,pins = <
0358 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
0359 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
0360 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
0361 >;
0362 };
0363
0364 pinctrl_usdhc2: usdhc2grp {
0365 fsl,pins = <
0366 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0367 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0368 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0369 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0370 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0371 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0372 >;
0373 };
0374
0375 pinctrl_usdhc3: usdhc3grp {
0376 fsl,pins = <
0377 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0378 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0379 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0380 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0381 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0382 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0383 >;
0384 };
0385
0386 pinctrl_usdhc3_cdwp: usdhc3cdwp {
0387 fsl,pins = <
0388 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
0389 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
0390 >;
0391 };
0392
0393 pinctrl_audmux: audmuxgrp {
0394 fsl,pins = <
0395 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
0396 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
0397 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
0398 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
0399 >;
0400 };
0401 };
0402 };
0403
0404 &pcie {
0405 pinctrl-names = "default";
0406 pinctrl-0 = <&pinctrl_pcie>;
0407 reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
0408 status = "disabled";
0409 };
0410
0411 ®_arm {
0412 vin-supply = <&vddcore_reg>;
0413 };
0414
0415 ®_pu {
0416 vin-supply = <&vddsoc_reg>;
0417 };
0418
0419 ®_soc {
0420 vin-supply = <&vddsoc_reg>;
0421 };
0422
0423 &uart3 {
0424 pinctrl-names = "default";
0425 pinctrl-0 = <&pinctrl_uart3>;
0426 uart-has-rtscts;
0427 status = "disabled";
0428 };
0429
0430 &uart4 {
0431 pinctrl-names = "default";
0432 pinctrl-0 = <&pinctrl_uart4>;
0433 status = "disabled";
0434 };
0435
0436 &usbh1 {
0437 vbus-supply = <®_usb_h1_vbus>;
0438 status = "disabled";
0439 };
0440
0441 &usbotg {
0442 vbus-supply = <®_usb_otg_vbus>;
0443 pinctrl-names = "default";
0444 pinctrl-0 = <&pinctrl_usbotg>;
0445 disable-over-current;
0446 status = "disabled";
0447 };
0448
0449 &usdhc2 {
0450 pinctrl-names = "default";
0451 pinctrl-0 = <&pinctrl_usdhc2>;
0452 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
0453 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
0454 vmmc-supply = <&vdd_sd1_reg>;
0455 status = "disabled";
0456 };
0457
0458 &usdhc3 {
0459 pinctrl-names = "default";
0460 pinctrl-0 = <&pinctrl_usdhc3
0461 &pinctrl_usdhc3_cdwp>;
0462 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
0463 wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
0464 vmmc-supply = <&vdd_sd0_reg>;
0465 status = "disabled";
0466 };
