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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003  * Copyright (C) 2018 PHYTEC Messtechnik
0004  * Author: Christian Hemp <c.hemp@phytec.de>
0005  */
0006 
0007 / {
0008         display: display0 {
0009                 #address-cells = <1>;
0010                 #size-cells = <0>;
0011                 compatible = "fsl,imx-parallel-display";
0012                 pinctrl-names = "default";
0013                 pinctrl-0 = <&pinctrl_disp0>;
0014                 interface-pix-fmt = "rgb24";
0015                 status = "disabled";
0016 
0017                 port@0 {
0018                         reg = <0>;
0019 
0020                         display0_in: endpoint {
0021                                 remote-endpoint = <&ipu1_di0_disp0>;
0022                         };
0023                 };
0024 
0025                 port@1 {
0026                         reg = <1>;
0027 
0028                         display0_out: endpoint {
0029                                 remote-endpoint = <&peb_panel_lcd_in>;
0030                         };
0031                 };
0032         };
0033 
0034         panel-lcd {
0035                 compatible = "edt,etm0700g0edh6";
0036                 pinctrl-names = "default";
0037                 pinctrl-0 = <&pinctrl_disp0_pwr>;
0038                 power-supply = <&reg_display>;
0039                 enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0040                 backlight = <&backlight>;
0041                 status = "disabled";
0042 
0043                 port {
0044                         peb_panel_lcd_in: endpoint {
0045                                 remote-endpoint = <&display0_out>;
0046                         };
0047                 };
0048         };
0049 
0050         reg_display: regulator-peb-display {
0051                 compatible = "regulator-fixed";
0052                 regulator-name = "peb-display";
0053                 regulator-min-microvolt = <3300000>;
0054                 regulator-max-microvolt = <3300000>;
0055         };
0056 };
0057 
0058 &i2c1 {
0059         edt_ft5x06: touchscreen@38 {
0060                 compatible = "edt,edt-ft5406";
0061                 pinctrl-names = "default";
0062                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
0063                 reg = <0x38>;
0064                 interrupt-parent = <&gpio3>;
0065                 interrupts = <2 IRQ_TYPE_NONE>;
0066                 status = "disabled";
0067         };
0068 };
0069 
0070 &ipu1_di0_disp0 {
0071         remote-endpoint = <&display0_in>;
0072 };
0073 
0074 &iomuxc {
0075         pinctrl_disp0: disp0grp {
0076                 fsl,pins = <
0077                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x10
0078                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x10
0079                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x10
0080                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0x1b080
0081                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x10
0082                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
0083                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
0084                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x10
0085                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x10
0086                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x10
0087                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x10
0088                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x10
0089                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x10
0090                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x10
0091                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x10
0092                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x10
0093                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x10
0094                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x10
0095                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x10
0096                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x10
0097                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x10
0098                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x10
0099                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x10
0100                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x10
0101                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x10
0102                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x10
0103                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x10
0104                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x10
0105                 >;
0106         };
0107 
0108         pinctrl_disp0_pwr: disp0pwrgrp {
0109                 fsl,pins = <
0110                         MX6QDL_PAD_EIM_D22__GPIO3_IO22                  0x1b0b0
0111                 >;
0112         };
0113 
0114         pinctrl_edt_ft5x06: edtft5x06grp {
0115                 fsl,pins = <
0116                         MX6QDL_PAD_EIM_DA2__GPIO3_IO02                  0xb0b1
0117                 >;
0118         };
0119 };