0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright 2013 Sascha Hauer, Pengutronix
0004 *
0005 * Copyright 2013-2021 TQ-Systems GmbH
0006 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
0007 */
0008
0009 #include <dt-bindings/clock/imx6qdl-clock.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/input/input.h>
0012 #include <dt-bindings/sound/fsl-imx-audmux.h>
0013
0014 / {
0015 aliases {
0016 mmc0 = &usdhc3;
0017 mmc1 = &usdhc2;
0018 /delete-property/ mmc2;
0019 /delete-property/ mmc3;
0020 rtc0 = &rtc0;
0021 };
0022
0023 chosen {
0024 stdout-path = &uart2;
0025 };
0026
0027 beeper: gpio-beeper {
0028 compatible = "gpio-beeper";
0029 pinctrl-names = "default";
0030 pinctrl-0 = <&pinctrl_gpiobeeper>;
0031 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
0032 };
0033
0034 gpio_buttons: gpio-buttons {
0035 compatible = "gpio-keys";
0036 pinctrl-names = "default";
0037 pinctrl-0 = <&pinctrl_gpiobuttons>;
0038
0039 button1 {
0040 label = "s6";
0041 linux,code = <KEY_F6>;
0042 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
0043 wakeup-source;
0044 };
0045
0046 button2 {
0047 label = "s7";
0048 linux,code = <KEY_F7>;
0049 gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
0050 wakeup-source;
0051 };
0052
0053 button3 {
0054 label = "s8";
0055 linux,code = <KEY_F8>;
0056 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
0057 wakeup-source;
0058 };
0059 };
0060
0061 gpio-leds {
0062 compatible = "gpio-leds";
0063 pinctrl-names = "default";
0064 pinctrl-0 = <&pinctrl_gpioled>;
0065
0066 led1 {
0067 label = "led1";
0068 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
0069 linux,default-trigger = "default-on";
0070 };
0071
0072 led2 {
0073 label = "led2";
0074 gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
0075 linux,default-trigger = "heartbeat";
0076 };
0077 };
0078
0079 reg_mba6_3p3v: regulator-mba6-3p3v {
0080 compatible = "regulator-fixed";
0081 regulator-name = "supply-mba6-3p3v";
0082 regulator-min-microvolt = <3300000>;
0083 regulator-max-microvolt = <3300000>;
0084 regulator-always-on;
0085 };
0086
0087 reg_pcie: regulator-pcie {
0088 compatible = "regulator-fixed";
0089 pinctrl-names = "default";
0090 pinctrl-0 = <&pinctrl_regpcie>;
0091 regulator-name = "supply-pcie";
0092 regulator-min-microvolt = <3300000>;
0093 regulator-max-microvolt = <3300000>;
0094 /* PCIE.PWR_EN */
0095 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
0096 enable-active-high;
0097 regulator-always-on;
0098 vin-supply = <®_mba6_3p3v>;
0099 };
0100
0101 reg_vcc3v3_audio: regulator-vcc3v3-audio {
0102 compatible = "regulator-fixed";
0103 regulator-name = "vcc3v3-audio";
0104 regulator-min-microvolt = <3300000>;
0105 regulator-max-microvolt = <3300000>;
0106 vin-supply = <®_mba6_3p3v>;
0107 };
0108
0109 sound {
0110 compatible = "fsl,imx-audio-tlv320aic32x4";
0111 pinctrl-names = "default";
0112 pinctrl-0 = <&pinctrl_audmux>;
0113 model = "imx-audio-tlv320aic32x4";
0114 ssi-controller = <&ssi1>;
0115 audio-codec = <&tlv320aic32x4>;
0116 audio-asrc = <&asrc>;
0117 audio-routing =
0118 "IN3_L", "Mic Jack",
0119 "Mic Jack", "Mic Bias",
0120 "IN1_L", "Line In Jack",
0121 "IN1_R", "Line In Jack",
0122 "Line Out Jack", "LOL",
0123 "Line Out Jack", "LOR";
0124 mux-int-port = <1>;
0125 mux-ext-port = <3>;
0126 };
0127 };
0128
0129 &audmux {
0130 status = "okay";
0131
0132 ssi0 {
0133 fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
0134 fsl,port-config = <
0135 (IMX_AUDMUX_V2_PTCR_SYN |
0136 IMX_AUDMUX_V2_PTCR_TFSDIR |
0137 IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
0138 IMX_AUDMUX_V2_PTCR_TCLKDIR |
0139 IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
0140 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
0141 >;
0142 };
0143
0144 aud3 {
0145 fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
0146 fsl,port-config = <
0147 IMX_AUDMUX_V2_PTCR_SYN
0148 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
0149 >;
0150 };
0151 };
0152
0153 &can1 {
0154 pinctrl-names = "default";
0155 pinctrl-0 = <&pinctrl_can1>;
0156 status = "okay";
0157 };
0158
0159 &can2 {
0160 pinctrl-names = "default";
0161 pinctrl-0 = <&pinctrl_can2>;
0162 status = "okay";
0163 };
0164
0165 &ecspi1 {
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
0168 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
0169 };
0170
0171 &fec {
0172 phy-mode = "rgmii-id";
0173 phy-handle = <ðphy>;
0174 mac-address = [00 00 00 00 00 00];
0175 status = "okay";
0176
0177 mdio {
0178 #address-cells = <1>;
0179 #size-cells = <0>;
0180
0181 ethphy: ethernet-phy@3 {
0182 compatible = "ethernet-phy-ieee802.3-c22";
0183 reg = <3>;
0184 interrupt-parent = <&gpio1>;
0185 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
0186 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
0187 reset-assert-us = <1000>;
0188 reset-deassert-us = <100000>;
0189 micrel,force-master;
0190 max-speed = <1000>;
0191 };
0192 };
0193 };
0194
0195 &i2c1 {
0196 tlv320aic32x4: audio-codec@18 {
0197 compatible = "ti,tlv320aic32x4";
0198 reg = <0x18>;
0199 clocks = <&clks IMX6QDL_CLK_CKO>;
0200 clock-names = "mclk";
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_codec>;
0203 ldoin-supply = <®_vcc3v3_audio>;
0204 iov-supply = <®_mba6_3p3v>;
0205 };
0206 };
0207
0208 &pcie {
0209 pinctrl-names = "default";
0210 pinctrl-0 = <&pinctrl_pcie>;
0211 reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
0212 status = "okay";
0213 };
0214
0215 &pwm1 {
0216 pinctrl-names = "default";
0217 pinctrl-0 = <&pinctrl_pwm1>;
0218 status = "okay";
0219 };
0220
0221 &pwm3 {
0222 pinctrl-names = "default";
0223 pinctrl-0 = <&pinctrl_pwm3>;
0224 status = "okay";
0225 };
0226
0227 &pwm4 {
0228 pinctrl-names = "default";
0229 pinctrl-0 = <&pinctrl_pwm4>;
0230 status = "okay";
0231 };
0232
0233 &snvs_poweroff {
0234 status = "okay";
0235 };
0236
0237 &ssi1 {
0238 status = "okay";
0239 };
0240
0241 &uart2 {
0242 pinctrl-names = "default";
0243 pinctrl-0 = <&pinctrl_uart2>;
0244 status = "okay";
0245 };
0246
0247
0248 &uart3 {
0249 pinctrl-names = "default";
0250 pinctrl-0 = <&pinctrl_uart3>;
0251 uart-has-rtscts;
0252 status = "okay";
0253 };
0254
0255 &uart4 {
0256 pinctrl-names = "default";
0257 pinctrl-0 = <&pinctrl_uart4>;
0258 uart-has-rtscts;
0259 linux,rs485-enabled-at-boot-time;
0260 rs485-rts-active-low;
0261 rs485-rx-during-tx;
0262 status = "okay";
0263 };
0264
0265 &uart5 {
0266 pinctrl-names = "default";
0267 pinctrl-0 = <&pinctrl_uart5>;
0268 uart-has-rtscts;
0269 status = "okay";
0270 };
0271
0272 &usbh1 {
0273 disable-over-current;
0274 status = "okay";
0275 };
0276
0277 &usbotg {
0278 pinctrl-names = "default";
0279 pinctrl-0 = <&pinctrl_usbotg>;
0280 power-active-high;
0281 over-current-active-low;
0282 srp-disable;
0283 hnp-disable;
0284 adp-disable;
0285 dr_mode = "otg";
0286 status = "okay";
0287 };
0288
0289 /* SD card slot */
0290 &usdhc2 {
0291 pinctrl-names = "default";
0292 pinctrl-0 = <&pinctrl_usdhc2>;
0293 vmmc-supply = <®_mba6_3p3v>;
0294 bus-width = <4>;
0295 no-1-8-v;
0296 no-mmc;
0297 no-sdio;
0298 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
0299 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
0300 status = "okay";
0301 };
0302
0303 &wdog1 {
0304 pinctrl-names = "default";
0305 pinctrl-0 = <&pinctrl_wdog1>;
0306 /* does not work on unmodified starter kit */
0307 /* fsl,ext-reset-output; */
0308 status = "okay";
0309 };
0310
0311 &iomuxc {
0312 pinctrl-names = "default";
0313 pinctrl-0 = <&pinctrl_hog>;
0314
0315 pinctrl_audmux: audmuxgrp {
0316 fsl,pins = <
0317 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
0318 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
0319 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
0320 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
0321 >;
0322 };
0323
0324 pinctrl_can1: can1grp {
0325 fsl,pins = <
0326 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
0327 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
0328 >;
0329 };
0330
0331 pinctrl_can2: can2grp {
0332 fsl,pins = <
0333 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
0334 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
0335 >;
0336 };
0337
0338 pinctrl_codec: codecgrp {
0339 fsl,pins = <
0340 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
0341 >;
0342 };
0343
0344 pinctrl_ecspi1_mba6: ecspimba6grp {
0345 fsl,pins = <
0346 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
0347 >;
0348 };
0349
0350 pinctrl_enet: enetgrp {
0351 fsl,pins = <
0352 /* FEC phy IRQ */
0353 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
0354 /* FEC phy reset */
0355 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
0356 /* DSE = 100, 100k up, SPEED = MED */
0357 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
0358 MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
0359 /* DSE = 111, pull 100k up */
0360 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
0361 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
0362 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
0363 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
0364 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
0365 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
0366 /* DSE = 111, pull external */
0367 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
0368 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
0369 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
0370 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
0371 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
0372 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
0373 /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
0374 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
0375 >;
0376 };
0377
0378 pinctrl_gpiobeeper: gpiobeepergrp {
0379 fsl,pins = <
0380 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
0381 >;
0382 };
0383
0384 pinctrl_gpiobuttons: gpiobuttongrp {
0385 fsl,pins = <
0386 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
0387 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
0388 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
0389 >;
0390 };
0391
0392 pinctrl_gpioled: gpioledgrp {
0393 fsl,pins = <
0394 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
0395 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
0396 >;
0397 };
0398
0399 pinctrl_hog: hoggrp {
0400 fsl,pins = <
0401 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
0402
0403 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
0404 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
0405 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
0406
0407 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
0408 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
0409 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
0410 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
0411 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
0412 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
0413 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
0414
0415 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
0416 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
0417 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
0418 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
0419 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
0420
0421 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
0422 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
0423 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
0424 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
0425
0426 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
0427 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
0428 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
0429
0430 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
0431 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
0432 >;
0433 };
0434
0435 pinctrl_pcie: pciegrp {
0436 fsl,pins = <
0437 /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
0438 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
0439 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
0440 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
0441 >;
0442 };
0443
0444 pinctrl_pwm1: pwm1grp {
0445 fsl,pins = <
0446 /* 100 k PD, DSE 120 OHM, SPPEED LO */
0447 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
0448 >;
0449 };
0450
0451 pinctrl_pwm3: pwm3grp {
0452 fsl,pins = <
0453 /* 100 k PD, DSE 120 OHM, SPPEED LO */
0454 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
0455 >;
0456 };
0457
0458 pinctrl_pwm4: pwm4grp {
0459 fsl,pins = <
0460 /* 100 k PD, DSE 120 OHM, SPPEED LO */
0461 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
0462 >;
0463 };
0464
0465 pinctrl_regpcie: regpciegrp {
0466 fsl,pins = <
0467 /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
0468 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
0469 >;
0470 };
0471
0472 pinctrl_uart2: uart2grp {
0473 fsl,pins = <
0474 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
0475 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
0476 >;
0477 };
0478
0479 pinctrl_uart3: uart3grp {
0480 fsl,pins = <
0481 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
0482 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
0483 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
0484 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
0485 >;
0486 };
0487
0488 pinctrl_uart4: uart4grp {
0489 fsl,pins = <
0490 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
0491 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
0492 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
0493 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
0494 >;
0495 };
0496
0497 pinctrl_uart5: uart5grp {
0498 fsl,pins = <
0499 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
0500 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
0501 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
0502 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
0503 >;
0504 };
0505
0506 pinctrl_usdhc2: usdhc2grp {
0507 fsl,pins = <
0508 /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
0509 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
0510 /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
0511 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
0512 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
0513 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
0514 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
0515 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
0516
0517 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
0518 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
0519 >;
0520 };
0521
0522 pinctrl_usbotg: usbotggrp {
0523 fsl,pins = <
0524 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
0525 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
0526 MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
0527 >;
0528 };
0529
0530 pinctrl_wdog1: wdog1grp {
0531 fsl,pins = <
0532 /* Watchdog out */
0533 MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
0534 >;
0535 };
0536 };
