0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright 2019 Gateworks Corporation
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/linux-event-codes.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009
0010 / {
0011 /* these are used by bootloader for disabling nodes */
0012 aliases {
0013 led0 = &led0;
0014 led1 = &led1;
0015 led2 = &led2;
0016 };
0017
0018 chosen {
0019 stdout-path = &uart2;
0020 };
0021
0022 memory@10000000 {
0023 device_type = "memory";
0024 reg = <0x10000000 0x20000000>;
0025 };
0026
0027 gpio-keys {
0028 compatible = "gpio-keys";
0029
0030 user-pb {
0031 label = "user_pb";
0032 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
0033 linux,code = <BTN_0>;
0034 };
0035
0036 user-pb1x {
0037 label = "user_pb1x";
0038 linux,code = <BTN_1>;
0039 interrupt-parent = <&gsc>;
0040 interrupts = <0>;
0041 };
0042
0043 key-erased {
0044 label = "key-erased";
0045 linux,code = <BTN_2>;
0046 interrupt-parent = <&gsc>;
0047 interrupts = <1>;
0048 };
0049
0050 eeprom-wp {
0051 label = "eeprom_wp";
0052 linux,code = <BTN_3>;
0053 interrupt-parent = <&gsc>;
0054 interrupts = <2>;
0055 };
0056
0057 tamper {
0058 label = "tamper";
0059 linux,code = <BTN_4>;
0060 interrupt-parent = <&gsc>;
0061 interrupts = <5>;
0062 };
0063
0064 switch-hold {
0065 label = "switch_hold";
0066 linux,code = <BTN_5>;
0067 interrupt-parent = <&gsc>;
0068 interrupts = <7>;
0069 };
0070 };
0071
0072 leds {
0073 compatible = "gpio-leds";
0074 pinctrl-names = "default";
0075 pinctrl-0 = <&pinctrl_gpio_leds>;
0076
0077 led0: user1 {
0078 label = "user1";
0079 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
0080 default-state = "on";
0081 linux,default-trigger = "heartbeat";
0082 };
0083
0084 led1: user2 {
0085 label = "user2";
0086 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
0087 default-state = "off";
0088 };
0089
0090 led2: user3 {
0091 label = "user3";
0092 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
0093 default-state = "off";
0094 };
0095 };
0096
0097 pps {
0098 compatible = "pps-gpio";
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&pinctrl_pps>;
0101 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
0102 status = "okay";
0103 };
0104
0105 reg_3p3v: regulator-3p3v {
0106 compatible = "regulator-fixed";
0107 regulator-name = "3P3V";
0108 regulator-min-microvolt = <3300000>;
0109 regulator-max-microvolt = <3300000>;
0110 regulator-always-on;
0111 };
0112
0113 reg_5p0v: regulator-5p0v {
0114 compatible = "regulator-fixed";
0115 regulator-name = "5P0V";
0116 regulator-min-microvolt = <5000000>;
0117 regulator-max-microvolt = <5000000>;
0118 regulator-always-on;
0119 };
0120
0121 reg_wl: regulator-wl {
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&pinctrl_reg_wl>;
0124 compatible = "regulator-fixed";
0125 regulator-name = "wl";
0126 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
0127 startup-delay-us = <100>;
0128 enable-active-high;
0129 regulator-min-microvolt = <3300000>;
0130 regulator-max-microvolt = <3300000>;
0131 };
0132 };
0133
0134
0135 &ecspi3 {
0136 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
0137 pinctrl-names = "default";
0138 pinctrl-0 = <&pinctrl_ecspi3>;
0139 status = "okay";
0140 };
0141
0142 &fec {
0143 pinctrl-names = "default";
0144 pinctrl-0 = <&pinctrl_enet>;
0145 phy-mode = "rgmii-id";
0146 status = "okay";
0147 };
0148
0149 &gpmi {
0150 pinctrl-names = "default";
0151 pinctrl-0 = <&pinctrl_gpmi_nand>;
0152 status = "okay";
0153 };
0154
0155 &i2c1 {
0156 clock-frequency = <100000>;
0157 pinctrl-names = "default";
0158 pinctrl-0 = <&pinctrl_i2c1>;
0159 status = "okay";
0160
0161 gsc: gsc@20 {
0162 compatible = "gw,gsc";
0163 reg = <0x20>;
0164 interrupt-parent = <&gpio1>;
0165 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0166 interrupt-controller;
0167 #interrupt-cells = <1>;
0168 #size-cells = <0>;
0169
0170 adc {
0171 compatible = "gw,gsc-adc";
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174
0175 channel@6 {
0176 gw,mode = <0>;
0177 reg = <0x06>;
0178 label = "temp";
0179 };
0180
0181 channel@8 {
0182 gw,mode = <3>;
0183 reg = <0x08>;
0184 label = "vdd_bat";
0185 };
0186
0187 channel@82 {
0188 gw,mode = <2>;
0189 reg = <0x82>;
0190 label = "vdd_vin";
0191 gw,voltage-divider-ohms = <22100 1000>;
0192 gw,voltage-offset-microvolt = <800000>;
0193 };
0194
0195 channel@84 {
0196 gw,mode = <2>;
0197 reg = <0x84>;
0198 label = "vdd_5p0";
0199 gw,voltage-divider-ohms = <22100 10000>;
0200 };
0201
0202 channel@86 {
0203 gw,mode = <2>;
0204 reg = <0x86>;
0205 label = "vdd_3p3";
0206 gw,voltage-divider-ohms = <10000 10000>;
0207 };
0208
0209 channel@88 {
0210 gw,mode = <2>;
0211 reg = <0x88>;
0212 label = "vdd_2p5";
0213 gw,voltage-divider-ohms = <10000 10000>;
0214 };
0215
0216 channel@8c {
0217 gw,mode = <2>;
0218 reg = <0x8c>;
0219 label = "vdd_3p0";
0220 };
0221
0222 channel@8e {
0223 gw,mode = <2>;
0224 reg = <0x8e>;
0225 label = "vdd_arm";
0226 };
0227
0228 channel@90 {
0229 gw,mode = <2>;
0230 reg = <0x90>;
0231 label = "vdd_soc";
0232 };
0233
0234 channel@92 {
0235 gw,mode = <2>;
0236 reg = <0x92>;
0237 label = "vdd_1p5";
0238 };
0239
0240 channel@98 {
0241 gw,mode = <2>;
0242 reg = <0x98>;
0243 label = "vdd_1p8";
0244 };
0245
0246 channel@9a {
0247 gw,mode = <2>;
0248 reg = <0x9a>;
0249 label = "vdd_1p0";
0250 gw,voltage-divider-ohms = <10000 10000>;
0251 };
0252
0253 channel@9c {
0254 gw,mode = <2>;
0255 reg = <0x9c>;
0256 label = "vdd_an1";
0257 gw,voltage-divider-ohms = <10000 10000>;
0258 };
0259
0260 channel@a2 {
0261 gw,mode = <2>;
0262 reg = <0xa2>;
0263 label = "vdd_gsc";
0264 gw,voltage-divider-ohms = <10000 10000>;
0265 };
0266 };
0267 };
0268
0269 gsc_gpio: gpio@23 {
0270 compatible = "nxp,pca9555";
0271 reg = <0x23>;
0272 gpio-controller;
0273 #gpio-cells = <2>;
0274 interrupt-parent = <&gsc>;
0275 interrupts = <4>;
0276 };
0277
0278 eeprom@50 {
0279 compatible = "atmel,24c02";
0280 reg = <0x50>;
0281 pagesize = <16>;
0282 };
0283
0284 eeprom@51 {
0285 compatible = "atmel,24c02";
0286 reg = <0x51>;
0287 pagesize = <16>;
0288 };
0289
0290 eeprom@52 {
0291 compatible = "atmel,24c02";
0292 reg = <0x52>;
0293 pagesize = <16>;
0294 };
0295
0296 eeprom@53 {
0297 compatible = "atmel,24c02";
0298 reg = <0x53>;
0299 pagesize = <16>;
0300 };
0301
0302 rtc@68 {
0303 compatible = "dallas,ds1672";
0304 reg = <0x68>;
0305 };
0306 };
0307
0308 &i2c2 {
0309 clock-frequency = <100000>;
0310 pinctrl-names = "default";
0311 pinctrl-0 = <&pinctrl_i2c2>;
0312 status = "okay";
0313 };
0314
0315 &i2c3 {
0316 clock-frequency = <100000>;
0317 pinctrl-names = "default";
0318 pinctrl-0 = <&pinctrl_i2c3>;
0319 status = "okay";
0320
0321 accel@19 {
0322 pinctrl-names = "default";
0323 pinctrl-0 = <&pinctrl_accel>;
0324 compatible = "st,lis2de12";
0325 reg = <0x19>;
0326 st,drdy-int-pin = <1>;
0327 interrupt-parent = <&gpio7>;
0328 interrupts = <13 0>;
0329 interrupt-names = "INT1";
0330 };
0331 };
0332
0333 &pcie {
0334 pinctrl-names = "default";
0335 pinctrl-0 = <&pinctrl_pcie>;
0336 reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
0337 status = "okay";
0338 };
0339
0340 &pwm2 {
0341 pinctrl-names = "default";
0342 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
0343 status = "disabled";
0344 };
0345
0346 &pwm3 {
0347 pinctrl-names = "default";
0348 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
0349 status = "disabled";
0350 };
0351
0352 /* off-board RS232 */
0353 &uart1 {
0354 pinctrl-names = "default";
0355 pinctrl-0 = <&pinctrl_uart1>;
0356 status = "okay";
0357 };
0358
0359 /* serial console */
0360 &uart2 {
0361 pinctrl-names = "default";
0362 pinctrl-0 = <&pinctrl_uart2>;
0363 status = "okay";
0364 };
0365
0366 /* cc1352 */
0367 &uart3 {
0368 pinctrl-names = "default";
0369 pinctrl-0 = <&pinctrl_uart3>;
0370 uart-has-rtscts;
0371 status = "okay";
0372 };
0373
0374 /* Sterling-LWB Bluetooth */
0375 &uart4 {
0376 pinctrl-names = "default";
0377 pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
0378 uart-has-rtscts;
0379 status = "okay";
0380
0381 bluetooth {
0382 compatible = "brcm,bcm4330-bt";
0383 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
0384 };
0385 };
0386
0387 /* GPS */
0388 &uart5 {
0389 pinctrl-names = "default";
0390 pinctrl-0 = <&pinctrl_uart5>;
0391 status = "okay";
0392 };
0393
0394 &usbotg {
0395 vbus-supply = <®_5p0v>;
0396 pinctrl-names = "default";
0397 pinctrl-0 = <&pinctrl_usbotg>;
0398 disable-over-current;
0399 status = "okay";
0400 };
0401
0402 &usbh1 {
0403 status = "okay";
0404 };
0405
0406 /* Sterling-LWB SDIO WiFi */
0407 &usdhc2 {
0408 pinctrl-names = "default";
0409 pinctrl-0 = <&pinctrl_usdhc2>;
0410 vmmc-supply = <®_wl>;
0411 non-removable;
0412 bus-width = <4>;
0413 status = "okay";
0414 };
0415
0416 &usdhc3 {
0417 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0418 pinctrl-0 = <&pinctrl_usdhc3>;
0419 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0420 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0421 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
0422 vmmc-supply = <®_3p3v>;
0423 status = "okay";
0424 };
0425
0426 &wdog1 {
0427 pinctrl-names = "default";
0428 pinctrl-0 = <&pinctrl_wdog>;
0429 fsl,ext-reset-output;
0430 };
0431
0432 &iomuxc {
0433 pinctrl_accel: accelmuxgrp {
0434 fsl,pins = <
0435 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
0436 >;
0437 };
0438
0439 pinctrl_bten: btengrp {
0440 fsl,pins = <
0441 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
0442 >;
0443 };
0444
0445 pinctrl_ecspi3: escpi3grp {
0446 fsl,pins = <
0447 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
0448 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
0449 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
0450 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
0451 >;
0452 };
0453
0454 pinctrl_enet: enetgrp {
0455 fsl,pins = <
0456 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0457 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0458 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0459 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0460 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0461 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0462 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0463 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0464 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0465 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0466 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0467 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0468 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0469 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0470 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0471 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
0472 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
0473 >;
0474 };
0475
0476 pinctrl_gpio_leds: gpioledsgrp {
0477 fsl,pins = <
0478 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
0479 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
0480 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
0481 >;
0482 };
0483
0484 pinctrl_gpmi_nand: gpminandgrp {
0485 fsl,pins = <
0486 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0487 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0488 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
0489 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0490 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0491 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0492 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0493 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0494 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0495 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0496 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0497 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0498 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0499 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0500 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0501 >;
0502 };
0503
0504 pinctrl_i2c1: i2c1grp {
0505 fsl,pins = <
0506 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
0507 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
0508 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
0509 >;
0510 };
0511
0512 pinctrl_i2c2: i2c2grp {
0513 fsl,pins = <
0514 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0515 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0516 >;
0517 };
0518
0519 pinctrl_i2c3: i2c3grp {
0520 fsl,pins = <
0521 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
0522 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0523 >;
0524 };
0525
0526 pinctrl_pcie: pciegrp {
0527 fsl,pins = <
0528 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
0529 >;
0530 };
0531
0532 pinctrl_pps: ppsgrp {
0533 fsl,pins = <
0534 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
0535 >;
0536 };
0537
0538 pinctrl_pwm2: pwm2grp {
0539 fsl,pins = <
0540 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
0541 >;
0542 };
0543
0544 pinctrl_pwm3: pwm3grp {
0545 fsl,pins = <
0546 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
0547 >;
0548 };
0549
0550 pinctrl_reg_wl: regwlgrp {
0551 fsl,pins = <
0552 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
0553 >;
0554 };
0555
0556 pinctrl_uart1: uart1grp {
0557 fsl,pins = <
0558 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
0559 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
0560 >;
0561 };
0562
0563 pinctrl_uart2: uart2grp {
0564 fsl,pins = <
0565 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
0566 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
0567 >;
0568 };
0569
0570 pinctrl_uart3: uart3grp {
0571 fsl,pins = <
0572 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
0573 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
0574 MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
0575 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
0576 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
0577 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
0578 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
0579 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
0580 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
0581 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
0582 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
0583 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
0584 >;
0585 };
0586
0587 pinctrl_uart4: uart4grp {
0588 fsl,pins = <
0589 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
0590 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
0591 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
0592 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
0593 >;
0594 };
0595
0596 pinctrl_uart5: uart5grp {
0597 fsl,pins = <
0598 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
0599 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
0600 >;
0601 };
0602
0603 pinctrl_usbotg: usbotggrp {
0604 fsl,pins = <
0605 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
0606 >;
0607 };
0608
0609 pinctrl_usdhc2: usdhc2grp {
0610 fsl,pins = <
0611 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0612 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0613 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0614 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0615 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0616 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0617 >;
0618 };
0619
0620 pinctrl_usdhc3: usdhc3grp {
0621 fsl,pins = <
0622 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0623 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0624 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0625 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0626 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0627 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0628 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
0629 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
0630 >;
0631 };
0632
0633 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
0634 fsl,pins = <
0635 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
0636 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
0637 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
0638 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
0639 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
0640 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
0641 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
0642 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
0643 >;
0644 };
0645
0646 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
0647 fsl,pins = <
0648 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
0649 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
0650 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
0651 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
0652 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
0653 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
0654 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
0655 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
0656 >;
0657 };
0658
0659 pinctrl_wdog: wdoggrp {
0660 fsl,pins = <
0661 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
0662 >;
0663 };
0664 };
