0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright 2013 Gateworks Corporation
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/linux-event-codes.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009
0010 / {
0011 /* these are used by bootloader for disabling nodes */
0012 aliases {
0013 led0 = &led0;
0014 led1 = &led1;
0015 led2 = &led2;
0016 nand = &gpmi;
0017 ssi0 = &ssi1;
0018 usb0 = &usbh1;
0019 usb1 = &usbotg;
0020 };
0021
0022 chosen {
0023 bootargs = "console=ttymxc1,115200";
0024 };
0025
0026 backlight {
0027 compatible = "pwm-backlight";
0028 pwms = <&pwm4 0 5000000>;
0029 brightness-levels = <0 4 8 16 32 64 128 255>;
0030 default-brightness-level = <7>;
0031 };
0032
0033 gpio-keys {
0034 compatible = "gpio-keys";
0035
0036 user-pb {
0037 label = "user_pb";
0038 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
0039 linux,code = <BTN_0>;
0040 };
0041
0042 user-pb1x {
0043 label = "user_pb1x";
0044 linux,code = <BTN_1>;
0045 interrupt-parent = <&gsc>;
0046 interrupts = <0>;
0047 };
0048
0049 key-erased {
0050 label = "key-erased";
0051 linux,code = <BTN_2>;
0052 interrupt-parent = <&gsc>;
0053 interrupts = <1>;
0054 };
0055
0056 eeprom-wp {
0057 label = "eeprom_wp";
0058 linux,code = <BTN_3>;
0059 interrupt-parent = <&gsc>;
0060 interrupts = <2>;
0061 };
0062
0063 tamper {
0064 label = "tamper";
0065 linux,code = <BTN_4>;
0066 interrupt-parent = <&gsc>;
0067 interrupts = <5>;
0068 };
0069
0070 switch-hold {
0071 label = "switch_hold";
0072 linux,code = <BTN_5>;
0073 interrupt-parent = <&gsc>;
0074 interrupts = <7>;
0075 };
0076 };
0077
0078 leds {
0079 compatible = "gpio-leds";
0080 pinctrl-names = "default";
0081 pinctrl-0 = <&pinctrl_gpio_leds>;
0082
0083 led0: user1 {
0084 label = "user1";
0085 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
0086 default-state = "on";
0087 linux,default-trigger = "heartbeat";
0088 };
0089
0090 led1: user2 {
0091 label = "user2";
0092 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
0093 default-state = "off";
0094 };
0095
0096 led2: user3 {
0097 label = "user3";
0098 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
0099 default-state = "off";
0100 };
0101 };
0102
0103 memory@10000000 {
0104 device_type = "memory";
0105 reg = <0x10000000 0x40000000>;
0106 };
0107
0108 pps {
0109 compatible = "pps-gpio";
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_pps>;
0112 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
0113 status = "okay";
0114 };
0115
0116 reg_1p0v: regulator-1p0v {
0117 compatible = "regulator-fixed";
0118 regulator-name = "1P0V";
0119 regulator-min-microvolt = <1000000>;
0120 regulator-max-microvolt = <1000000>;
0121 regulator-always-on;
0122 };
0123
0124 reg_3p3v: regulator-3p3v {
0125 compatible = "regulator-fixed";
0126 regulator-name = "3P3V";
0127 regulator-min-microvolt = <3300000>;
0128 regulator-max-microvolt = <3300000>;
0129 regulator-always-on;
0130 };
0131
0132 reg_usb_h1_vbus: regulator-usb-h1-vbus {
0133 compatible = "regulator-fixed";
0134 regulator-name = "usb_h1_vbus";
0135 regulator-min-microvolt = <5000000>;
0136 regulator-max-microvolt = <5000000>;
0137 regulator-always-on;
0138 };
0139
0140 reg_usb_otg_vbus: regulator-usb-otg-vbus {
0141 compatible = "regulator-fixed";
0142 regulator-name = "usb_otg_vbus";
0143 regulator-min-microvolt = <5000000>;
0144 regulator-max-microvolt = <5000000>;
0145 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0146 enable-active-high;
0147 };
0148
0149 sound {
0150 compatible = "fsl,imx6q-ventana-sgtl5000",
0151 "fsl,imx-audio-sgtl5000";
0152 model = "sgtl5000-audio";
0153 ssi-controller = <&ssi1>;
0154 audio-codec = <&codec>;
0155 audio-routing =
0156 "MIC_IN", "Mic Jack",
0157 "Mic Jack", "Mic Bias",
0158 "Headphone Jack", "HP_OUT";
0159 mux-int-port = <1>;
0160 mux-ext-port = <4>;
0161 };
0162 };
0163
0164 &audmux {
0165 pinctrl-names = "default";
0166 pinctrl-0 = <&pinctrl_audmux>;
0167 status = "okay";
0168 };
0169
0170 &can1 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&pinctrl_flexcan1>;
0173 status = "okay";
0174 };
0175
0176 &clks {
0177 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
0178 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
0179 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
0180 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
0181 };
0182
0183 &fec {
0184 pinctrl-names = "default";
0185 pinctrl-0 = <&pinctrl_enet>;
0186 phy-mode = "rgmii-id";
0187 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
0188 status = "okay";
0189 };
0190
0191 &gpmi {
0192 pinctrl-names = "default";
0193 pinctrl-0 = <&pinctrl_gpmi_nand>;
0194 status = "okay";
0195 };
0196
0197 &hdmi {
0198 ddc-i2c-bus = <&i2c3>;
0199 status = "okay";
0200 };
0201
0202 &i2c1 {
0203 clock-frequency = <100000>;
0204 pinctrl-names = "default";
0205 pinctrl-0 = <&pinctrl_i2c1>;
0206 status = "okay";
0207
0208 gsc: gsc@20 {
0209 compatible = "gw,gsc";
0210 reg = <0x20>;
0211 interrupt-parent = <&gpio1>;
0212 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0213 interrupt-controller;
0214 #interrupt-cells = <1>;
0215 #size-cells = <0>;
0216
0217 adc {
0218 compatible = "gw,gsc-adc";
0219 #address-cells = <1>;
0220 #size-cells = <0>;
0221
0222 channel@0 {
0223 gw,mode = <0>;
0224 reg = <0x00>;
0225 label = "temp";
0226 };
0227
0228 channel@2 {
0229 gw,mode = <1>;
0230 reg = <0x02>;
0231 label = "vdd_vin";
0232 };
0233
0234 channel@5 {
0235 gw,mode = <1>;
0236 reg = <0x05>;
0237 label = "vdd_3p3";
0238 };
0239
0240 channel@8 {
0241 gw,mode = <1>;
0242 reg = <0x08>;
0243 label = "vdd_bat";
0244 };
0245
0246 channel@b {
0247 gw,mode = <1>;
0248 reg = <0x0b>;
0249 label = "vdd_5p0";
0250 };
0251
0252 channel@e {
0253 gw,mode = <1>;
0254 reg = <0xe>;
0255 label = "vdd_arm";
0256 };
0257
0258 channel@11 {
0259 gw,mode = <1>;
0260 reg = <0x11>;
0261 label = "vdd_soc";
0262 };
0263
0264 channel@14 {
0265 gw,mode = <1>;
0266 reg = <0x14>;
0267 label = "vdd_3p0";
0268 };
0269
0270 channel@17 {
0271 gw,mode = <1>;
0272 reg = <0x17>;
0273 label = "vdd_1p5";
0274 };
0275
0276 channel@1d {
0277 gw,mode = <1>;
0278 reg = <0x1d>;
0279 label = "vdd_1p8";
0280 };
0281
0282 channel@20 {
0283 gw,mode = <1>;
0284 reg = <0x20>;
0285 label = "vdd_1p0";
0286 };
0287
0288 channel@23 {
0289 gw,mode = <1>;
0290 reg = <0x23>;
0291 label = "vdd_2p5";
0292 };
0293
0294 channel@26 {
0295 gw,mode = <1>;
0296 reg = <0x26>;
0297 label = "vdd_gps";
0298 };
0299
0300 channel@29 {
0301 gw,mode = <1>;
0302 reg = <0x29>;
0303 label = "vdd_an1";
0304 };
0305 };
0306 };
0307
0308 gsc_gpio: gpio@23 {
0309 compatible = "nxp,pca9555";
0310 reg = <0x23>;
0311 gpio-controller;
0312 #gpio-cells = <2>;
0313 interrupt-parent = <&gsc>;
0314 interrupts = <4>;
0315 };
0316
0317 eeprom1: eeprom@50 {
0318 compatible = "atmel,24c02";
0319 reg = <0x50>;
0320 pagesize = <16>;
0321 };
0322
0323 eeprom2: eeprom@51 {
0324 compatible = "atmel,24c02";
0325 reg = <0x51>;
0326 pagesize = <16>;
0327 };
0328
0329 eeprom3: eeprom@52 {
0330 compatible = "atmel,24c02";
0331 reg = <0x52>;
0332 pagesize = <16>;
0333 };
0334
0335 eeprom4: eeprom@53 {
0336 compatible = "atmel,24c02";
0337 reg = <0x53>;
0338 pagesize = <16>;
0339 };
0340
0341 rtc: ds1672@68 {
0342 compatible = "dallas,ds1672";
0343 reg = <0x68>;
0344 };
0345 };
0346
0347 &i2c2 {
0348 clock-frequency = <100000>;
0349 pinctrl-names = "default";
0350 pinctrl-0 = <&pinctrl_i2c2>;
0351 status = "okay";
0352
0353 ltc3676: pmic@3c {
0354 compatible = "lltc,ltc3676";
0355 reg = <0x3c>;
0356 interrupt-parent = <&gpio1>;
0357 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
0358
0359 regulators {
0360 /* VDD_SOC (1+R1/R2 = 1.635) */
0361 reg_vdd_soc: sw1 {
0362 regulator-name = "vddsoc";
0363 regulator-min-microvolt = <674400>;
0364 regulator-max-microvolt = <1308000>;
0365 lltc,fb-voltage-divider = <127000 200000>;
0366 regulator-ramp-delay = <7000>;
0367 regulator-boot-on;
0368 regulator-always-on;
0369 };
0370
0371 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
0372 reg_1p8v: sw2 {
0373 regulator-name = "vdd1p8";
0374 regulator-min-microvolt = <1033310>;
0375 regulator-max-microvolt = <2004000>;
0376 lltc,fb-voltage-divider = <301000 200000>;
0377 regulator-ramp-delay = <7000>;
0378 regulator-boot-on;
0379 regulator-always-on;
0380 };
0381
0382 /* VDD_ARM (1+R1/R2 = 1.635) */
0383 reg_vdd_arm: sw3 {
0384 regulator-name = "vddarm";
0385 regulator-min-microvolt = <674400>;
0386 regulator-max-microvolt = <1308000>;
0387 lltc,fb-voltage-divider = <127000 200000>;
0388 regulator-ramp-delay = <7000>;
0389 regulator-boot-on;
0390 regulator-always-on;
0391 };
0392
0393 /* VDD_DDR (1+R1/R2 = 2.105) */
0394 reg_vdd_ddr: sw4 {
0395 regulator-name = "vddddr";
0396 regulator-min-microvolt = <868310>;
0397 regulator-max-microvolt = <1684000>;
0398 lltc,fb-voltage-divider = <221000 200000>;
0399 regulator-ramp-delay = <7000>;
0400 regulator-boot-on;
0401 regulator-always-on;
0402 };
0403
0404 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
0405 reg_2p5v: ldo2 {
0406 regulator-name = "vdd2p5";
0407 regulator-min-microvolt = <2490375>;
0408 regulator-max-microvolt = <2490375>;
0409 lltc,fb-voltage-divider = <487000 200000>;
0410 regulator-boot-on;
0411 regulator-always-on;
0412 };
0413
0414 /* VDD_AUD_1P8: Audio codec */
0415 reg_aud_1p8v: ldo3 {
0416 regulator-name = "vdd1p8a";
0417 regulator-min-microvolt = <1800000>;
0418 regulator-max-microvolt = <1800000>;
0419 regulator-boot-on;
0420 };
0421
0422 /* VDD_HIGH (1+R1/R2 = 4.17) */
0423 reg_3p0v: ldo4 {
0424 regulator-name = "vdd3p0";
0425 regulator-min-microvolt = <3023250>;
0426 regulator-max-microvolt = <3023250>;
0427 lltc,fb-voltage-divider = <634000 200000>;
0428 regulator-boot-on;
0429 regulator-always-on;
0430 };
0431 };
0432 };
0433 };
0434
0435 &i2c3 {
0436 clock-frequency = <100000>;
0437 pinctrl-names = "default";
0438 pinctrl-0 = <&pinctrl_i2c3>;
0439 status = "okay";
0440
0441 codec: sgtl5000@a {
0442 compatible = "fsl,sgtl5000";
0443 reg = <0x0a>;
0444 clocks = <&clks IMX6QDL_CLK_CKO>;
0445 VDDA-supply = <®_1p8v>;
0446 VDDIO-supply = <®_3p3v>;
0447 };
0448
0449 touchscreen: egalax_ts@4 {
0450 compatible = "eeti,egalax_ts";
0451 reg = <0x04>;
0452 interrupt-parent = <&gpio1>;
0453 interrupts = <11 2>;
0454 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
0455 };
0456
0457 accel@1e {
0458 compatible = "nxp,fxos8700";
0459 reg = <0x1e>;
0460 };
0461 };
0462
0463 &ldb {
0464 status = "okay";
0465
0466 lvds-channel@0 {
0467 fsl,data-mapping = "spwg";
0468 fsl,data-width = <18>;
0469 status = "okay";
0470
0471 display-timings {
0472 native-mode = <&timing0>;
0473 timing0: hsd100pxn1 {
0474 clock-frequency = <65000000>;
0475 hactive = <1024>;
0476 vactive = <768>;
0477 hback-porch = <220>;
0478 hfront-porch = <40>;
0479 vback-porch = <21>;
0480 vfront-porch = <7>;
0481 hsync-len = <60>;
0482 vsync-len = <10>;
0483 };
0484 };
0485 };
0486 };
0487
0488 &pcie {
0489 pinctrl-names = "default";
0490 pinctrl-0 = <&pinctrl_pcie>;
0491 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
0492 status = "okay";
0493 };
0494
0495 &pwm2 {
0496 pinctrl-names = "default";
0497 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
0498 status = "disabled";
0499 };
0500
0501 &pwm3 {
0502 pinctrl-names = "default";
0503 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
0504 status = "disabled";
0505 };
0506
0507 &pwm4 {
0508 #pwm-cells = <2>;
0509 pinctrl-names = "default";
0510 pinctrl-0 = <&pinctrl_pwm4>;
0511 status = "okay";
0512 };
0513
0514 &ssi1 {
0515 status = "okay";
0516 };
0517
0518 &uart1 {
0519 pinctrl-names = "default";
0520 pinctrl-0 = <&pinctrl_uart1>;
0521 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
0522 status = "okay";
0523 };
0524
0525 &uart2 {
0526 pinctrl-names = "default";
0527 pinctrl-0 = <&pinctrl_uart2>;
0528 status = "okay";
0529 };
0530
0531 &uart5 {
0532 pinctrl-names = "default";
0533 pinctrl-0 = <&pinctrl_uart5>;
0534 status = "okay";
0535 };
0536
0537 &usbotg {
0538 vbus-supply = <®_usb_otg_vbus>;
0539 pinctrl-names = "default";
0540 pinctrl-0 = <&pinctrl_usbotg>;
0541 disable-over-current;
0542 status = "okay";
0543 };
0544
0545 &usbh1 {
0546 vbus-supply = <®_usb_h1_vbus>;
0547 status = "okay";
0548 };
0549
0550 &usdhc3 {
0551 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0552 pinctrl-0 = <&pinctrl_usdhc3>;
0553 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0554 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0555 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
0556 vmmc-supply = <®_3p3v>;
0557 no-1-8-v; /* firmware will remove if board revision supports */
0558 status = "okay";
0559 };
0560
0561 &wdog1 {
0562 pinctrl-names = "default";
0563 pinctrl-0 = <&pinctrl_wdog>;
0564 fsl,ext-reset-output;
0565 };
0566
0567 &iomuxc {
0568 pinctrl_audmux: audmuxgrp {
0569 fsl,pins = <
0570 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
0571 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
0572 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
0573 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
0574 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
0575 >;
0576 };
0577
0578 pinctrl_enet: enetgrp {
0579 fsl,pins = <
0580 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0581 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0582 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0583 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0584 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0585 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0586 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0587 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0588 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0589 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0590 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0591 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0592 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0593 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0594 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0595 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
0596 >;
0597 };
0598
0599 pinctrl_flexcan1: flexcan1grp {
0600 fsl,pins = <
0601 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
0602 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
0603 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
0604 >;
0605 };
0606
0607 pinctrl_gpio_leds: gpioledsgrp {
0608 fsl,pins = <
0609 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
0610 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
0611 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
0612 >;
0613 };
0614
0615 pinctrl_gpmi_nand: gpminandgrp {
0616 fsl,pins = <
0617 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0618 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0619 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
0620 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0621 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0622 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0623 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0624 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0625 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0626 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0627 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0628 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0629 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0630 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0631 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0632 >;
0633 };
0634
0635 pinctrl_i2c1: i2c1grp {
0636 fsl,pins = <
0637 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
0638 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
0639 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
0640 >;
0641 };
0642
0643 pinctrl_i2c2: i2c2grp {
0644 fsl,pins = <
0645 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0646 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0647 >;
0648 };
0649
0650 pinctrl_i2c3: i2c3grp {
0651 fsl,pins = <
0652 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
0653 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0654 >;
0655 };
0656
0657 pinctrl_pcie: pciegrp {
0658 fsl,pins = <
0659 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
0660 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
0661 >;
0662 };
0663
0664 pinctrl_pmic: pmicgrp {
0665 fsl,pins = <
0666 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
0667 >;
0668 };
0669
0670 pinctrl_pps: ppsgrp {
0671 fsl,pins = <
0672 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
0673 >;
0674 };
0675
0676 pinctrl_pwm2: pwm2grp {
0677 fsl,pins = <
0678 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
0679 >;
0680 };
0681
0682 pinctrl_pwm3: pwm3grp {
0683 fsl,pins = <
0684 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
0685 >;
0686 };
0687
0688 pinctrl_pwm4: pwm4grp {
0689 fsl,pins = <
0690 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
0691 >;
0692 };
0693
0694 pinctrl_uart1: uart1grp {
0695 fsl,pins = <
0696 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
0697 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
0698 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
0699 >;
0700 };
0701
0702 pinctrl_uart2: uart2grp {
0703 fsl,pins = <
0704 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
0705 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
0706 >;
0707 };
0708
0709 pinctrl_uart5: uart5grp {
0710 fsl,pins = <
0711 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
0712 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
0713 >;
0714 };
0715
0716 pinctrl_usbotg: usbotggrp {
0717 fsl,pins = <
0718 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
0719 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
0720 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
0721 >;
0722 };
0723
0724 pinctrl_usdhc3: usdhc3grp {
0725 fsl,pins = <
0726 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0727 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0728 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0729 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0730 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0731 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0732 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
0733 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
0734 >;
0735 };
0736
0737 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
0738 fsl,pins = <
0739 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
0740 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
0741 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
0742 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
0743 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
0744 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
0745 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
0746 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
0747 >;
0748 };
0749
0750 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
0751 fsl,pins = <
0752 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
0753 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
0754 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
0755 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
0756 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
0757 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
0758 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
0759 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
0760 >;
0761 };
0762
0763 pinctrl_wdog: wdoggrp {
0764 fsl,pins = <
0765 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
0766 >;
0767 };
0768 };
