0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright 2013 Gateworks Corporation
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/linux-event-codes.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009
0010 / {
0011 /* these are used by bootloader for disabling nodes */
0012 aliases {
0013 led0 = &led0;
0014 led1 = &led1;
0015 led2 = &led2;
0016 nand = &gpmi;
0017 ssi0 = &ssi1;
0018 usb0 = &usbh1;
0019 usb1 = &usbotg;
0020 };
0021
0022 chosen {
0023 bootargs = "console=ttymxc1,115200";
0024 };
0025
0026 backlight {
0027 compatible = "pwm-backlight";
0028 pwms = <&pwm4 0 5000000>;
0029 brightness-levels = <0 4 8 16 32 64 128 255>;
0030 default-brightness-level = <7>;
0031 };
0032
0033 gpio-keys {
0034 compatible = "gpio-keys";
0035
0036 user-pb {
0037 label = "user_pb";
0038 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
0039 linux,code = <BTN_0>;
0040 };
0041
0042 user-pb1x {
0043 label = "user_pb1x";
0044 linux,code = <BTN_1>;
0045 interrupt-parent = <&gsc>;
0046 interrupts = <0>;
0047 };
0048
0049 key-erased {
0050 label = "key-erased";
0051 linux,code = <BTN_2>;
0052 interrupt-parent = <&gsc>;
0053 interrupts = <1>;
0054 };
0055
0056 eeprom-wp {
0057 label = "eeprom_wp";
0058 linux,code = <BTN_3>;
0059 interrupt-parent = <&gsc>;
0060 interrupts = <2>;
0061 };
0062
0063 tamper {
0064 label = "tamper";
0065 linux,code = <BTN_4>;
0066 interrupt-parent = <&gsc>;
0067 interrupts = <5>;
0068 };
0069
0070 switch-hold {
0071 label = "switch_hold";
0072 linux,code = <BTN_5>;
0073 interrupt-parent = <&gsc>;
0074 interrupts = <7>;
0075 };
0076 };
0077
0078 leds {
0079 compatible = "gpio-leds";
0080 pinctrl-names = "default";
0081 pinctrl-0 = <&pinctrl_gpio_leds>;
0082
0083 led0: user1 {
0084 label = "user1";
0085 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
0086 default-state = "on";
0087 linux,default-trigger = "heartbeat";
0088 };
0089
0090 led1: user2 {
0091 label = "user2";
0092 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
0093 default-state = "off";
0094 };
0095
0096 led2: user3 {
0097 label = "user3";
0098 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
0099 default-state = "off";
0100 };
0101 };
0102
0103 memory@10000000 {
0104 device_type = "memory";
0105 reg = <0x10000000 0x20000000>;
0106 };
0107
0108 pps {
0109 compatible = "pps-gpio";
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_pps>;
0112 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
0113 status = "okay";
0114 };
0115
0116 reg_1p0v: regulator-1p0v {
0117 compatible = "regulator-fixed";
0118 regulator-name = "1P0V";
0119 regulator-min-microvolt = <1000000>;
0120 regulator-max-microvolt = <1000000>;
0121 regulator-always-on;
0122 };
0123
0124 reg_3p3v: regulator-3p3v {
0125 compatible = "regulator-fixed";
0126 regulator-name = "3P3V";
0127 regulator-min-microvolt = <3300000>;
0128 regulator-max-microvolt = <3300000>;
0129 regulator-always-on;
0130 };
0131
0132 reg_5p0v: regulator-5p0v {
0133 compatible = "regulator-fixed";
0134 regulator-name = "5P0V";
0135 regulator-min-microvolt = <5000000>;
0136 regulator-max-microvolt = <5000000>;
0137 regulator-always-on;
0138 };
0139
0140 reg_usb_otg_vbus: regulator-usb-otg-vbus {
0141 compatible = "regulator-fixed";
0142 regulator-name = "usb_otg_vbus";
0143 regulator-min-microvolt = <5000000>;
0144 regulator-max-microvolt = <5000000>;
0145 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0146 enable-active-high;
0147 };
0148
0149 sound {
0150 compatible = "fsl,imx6q-ventana-sgtl5000",
0151 "fsl,imx-audio-sgtl5000";
0152 model = "sgtl5000-audio";
0153 ssi-controller = <&ssi1>;
0154 audio-codec = <&codec>;
0155 audio-routing =
0156 "MIC_IN", "Mic Jack",
0157 "Mic Jack", "Mic Bias",
0158 "Headphone Jack", "HP_OUT";
0159 mux-int-port = <1>;
0160 mux-ext-port = <4>;
0161 };
0162 };
0163
0164 &audmux {
0165 pinctrl-names = "default";
0166 pinctrl-0 = <&pinctrl_audmux>;
0167 status = "okay";
0168 };
0169
0170 &can1 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&pinctrl_flexcan1>;
0173 status = "okay";
0174 };
0175
0176 &clks {
0177 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
0178 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
0179 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
0180 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
0181 };
0182
0183 &ecspi3 {
0184 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
0185 pinctrl-names = "default";
0186 pinctrl-0 = <&pinctrl_ecspi3>;
0187 status = "okay";
0188 };
0189
0190 &fec {
0191 pinctrl-names = "default";
0192 pinctrl-0 = <&pinctrl_enet>;
0193 phy-mode = "rgmii-id";
0194 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
0195 status = "okay";
0196 };
0197
0198 &gpmi {
0199 pinctrl-names = "default";
0200 pinctrl-0 = <&pinctrl_gpmi_nand>;
0201 status = "okay";
0202 };
0203
0204 &hdmi {
0205 ddc-i2c-bus = <&i2c3>;
0206 status = "okay";
0207 };
0208
0209 &i2c1 {
0210 clock-frequency = <100000>;
0211 pinctrl-names = "default";
0212 pinctrl-0 = <&pinctrl_i2c1>;
0213 status = "okay";
0214
0215 gsc: gsc@20 {
0216 compatible = "gw,gsc";
0217 reg = <0x20>;
0218 interrupt-parent = <&gpio1>;
0219 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0220 interrupt-controller;
0221 #interrupt-cells = <1>;
0222 #size-cells = <0>;
0223
0224 adc {
0225 compatible = "gw,gsc-adc";
0226 #address-cells = <1>;
0227 #size-cells = <0>;
0228
0229 channel@0 {
0230 gw,mode = <0>;
0231 reg = <0x00>;
0232 label = "temp";
0233 };
0234
0235 channel@2 {
0236 gw,mode = <1>;
0237 reg = <0x02>;
0238 label = "vdd_vin";
0239 };
0240
0241 channel@5 {
0242 gw,mode = <1>;
0243 reg = <0x05>;
0244 label = "vdd_3p3";
0245 };
0246
0247 channel@8 {
0248 gw,mode = <1>;
0249 reg = <0x08>;
0250 label = "vdd_bat";
0251 };
0252
0253 channel@b {
0254 gw,mode = <1>;
0255 reg = <0x0b>;
0256 label = "vdd_5p0";
0257 };
0258
0259 channel@e {
0260 gw,mode = <1>;
0261 reg = <0xe>;
0262 label = "vdd_arm";
0263 };
0264
0265 channel@11 {
0266 gw,mode = <1>;
0267 reg = <0x11>;
0268 label = "vdd_soc";
0269 };
0270
0271 channel@14 {
0272 gw,mode = <1>;
0273 reg = <0x14>;
0274 label = "vdd_3p0";
0275 };
0276
0277 channel@17 {
0278 gw,mode = <1>;
0279 reg = <0x17>;
0280 label = "vdd_1p5";
0281 };
0282
0283 channel@1d {
0284 gw,mode = <1>;
0285 reg = <0x1d>;
0286 label = "vdd_1p8";
0287 };
0288
0289 channel@20 {
0290 gw,mode = <1>;
0291 reg = <0x20>;
0292 label = "vdd_1p0";
0293 };
0294
0295 channel@23 {
0296 gw,mode = <1>;
0297 reg = <0x23>;
0298 label = "vdd_2p5";
0299 };
0300
0301 channel@29 {
0302 gw,mode = <1>;
0303 reg = <0x29>;
0304 label = "vdd_an1";
0305 };
0306 };
0307 };
0308
0309 gsc_gpio: gpio@23 {
0310 compatible = "nxp,pca9555";
0311 reg = <0x23>;
0312 gpio-controller;
0313 #gpio-cells = <2>;
0314 interrupt-parent = <&gsc>;
0315 interrupts = <4>;
0316 };
0317
0318 eeprom1: eeprom@50 {
0319 compatible = "atmel,24c02";
0320 reg = <0x50>;
0321 pagesize = <16>;
0322 };
0323
0324 eeprom2: eeprom@51 {
0325 compatible = "atmel,24c02";
0326 reg = <0x51>;
0327 pagesize = <16>;
0328 };
0329
0330 eeprom3: eeprom@52 {
0331 compatible = "atmel,24c02";
0332 reg = <0x52>;
0333 pagesize = <16>;
0334 };
0335
0336 eeprom4: eeprom@53 {
0337 compatible = "atmel,24c02";
0338 reg = <0x53>;
0339 pagesize = <16>;
0340 };
0341
0342 rtc: ds1672@68 {
0343 compatible = "dallas,ds1672";
0344 reg = <0x68>;
0345 };
0346 };
0347
0348 &i2c2 {
0349 clock-frequency = <100000>;
0350 pinctrl-names = "default";
0351 pinctrl-0 = <&pinctrl_i2c2>;
0352 status = "okay";
0353
0354 ltc3676: pmic@3c {
0355 compatible = "lltc,ltc3676";
0356 reg = <0x3c>;
0357 pinctrl-names = "default";
0358 pinctrl-0 = <&pinctrl_pmic>;
0359 interrupt-parent = <&gpio1>;
0360 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
0361
0362 regulators {
0363 /* VDD_SOC (1+R1/R2 = 1.635) */
0364 reg_vdd_soc: sw1 {
0365 regulator-name = "vddsoc";
0366 regulator-min-microvolt = <674400>;
0367 regulator-max-microvolt = <1308000>;
0368 lltc,fb-voltage-divider = <127000 200000>;
0369 regulator-ramp-delay = <7000>;
0370 regulator-boot-on;
0371 regulator-always-on;
0372 };
0373
0374 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
0375 reg_1p8v: sw2 {
0376 regulator-name = "vdd1p8";
0377 regulator-min-microvolt = <1033310>;
0378 regulator-max-microvolt = <2004000>;
0379 lltc,fb-voltage-divider = <301000 200000>;
0380 regulator-ramp-delay = <7000>;
0381 regulator-boot-on;
0382 regulator-always-on;
0383 };
0384
0385 /* VDD_ARM (1+R1/R2 = 1.635) */
0386 reg_vdd_arm: sw3 {
0387 regulator-name = "vddarm";
0388 regulator-min-microvolt = <674400>;
0389 regulator-max-microvolt = <1308000>;
0390 lltc,fb-voltage-divider = <127000 200000>;
0391 regulator-ramp-delay = <7000>;
0392 regulator-boot-on;
0393 regulator-always-on;
0394 };
0395
0396 /* VDD_DDR (1+R1/R2 = 2.105) */
0397 reg_vdd_ddr: sw4 {
0398 regulator-name = "vddddr";
0399 regulator-min-microvolt = <868310>;
0400 regulator-max-microvolt = <1684000>;
0401 lltc,fb-voltage-divider = <221000 200000>;
0402 regulator-ramp-delay = <7000>;
0403 regulator-boot-on;
0404 regulator-always-on;
0405 };
0406
0407 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
0408 reg_2p5v: ldo2 {
0409 regulator-name = "vdd2p5";
0410 regulator-min-microvolt = <2490375>;
0411 regulator-max-microvolt = <2490375>;
0412 lltc,fb-voltage-divider = <487000 200000>;
0413 regulator-boot-on;
0414 regulator-always-on;
0415 };
0416
0417 /* VDD_AUD_1P8: Audio codec */
0418 reg_aud_1p8v: ldo3 {
0419 regulator-name = "vdd1p8a";
0420 regulator-min-microvolt = <1800000>;
0421 regulator-max-microvolt = <1800000>;
0422 regulator-boot-on;
0423 };
0424
0425 /* VDD_HIGH (1+R1/R2 = 4.17) */
0426 reg_3p0v: ldo4 {
0427 regulator-name = "vdd3p0";
0428 regulator-min-microvolt = <3023250>;
0429 regulator-max-microvolt = <3023250>;
0430 lltc,fb-voltage-divider = <634000 200000>;
0431 regulator-boot-on;
0432 regulator-always-on;
0433 };
0434 };
0435 };
0436 };
0437
0438 &i2c3 {
0439 clock-frequency = <100000>;
0440 pinctrl-names = "default";
0441 pinctrl-0 = <&pinctrl_i2c3>;
0442 status = "okay";
0443
0444 codec: sgtl5000@a {
0445 compatible = "fsl,sgtl5000";
0446 reg = <0x0a>;
0447 clocks = <&clks IMX6QDL_CLK_CKO>;
0448 VDDA-supply = <®_1p8v>;
0449 VDDIO-supply = <®_3p3v>;
0450 };
0451
0452 touchscreen: egalax_ts@4 {
0453 compatible = "eeti,egalax_ts";
0454 reg = <0x04>;
0455 interrupt-parent = <&gpio7>;
0456 interrupts = <12 2>;
0457 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
0458 };
0459
0460 accel@1e {
0461 compatible = "nxp,fxos8700";
0462 reg = <0x1e>;
0463 };
0464 };
0465
0466 &ldb {
0467 status = "okay";
0468
0469 lvds-channel@0 {
0470 fsl,data-mapping = "spwg";
0471 fsl,data-width = <18>;
0472 status = "okay";
0473
0474 display-timings {
0475 native-mode = <&timing0>;
0476 timing0: hsd100pxn1 {
0477 clock-frequency = <65000000>;
0478 hactive = <1024>;
0479 vactive = <768>;
0480 hback-porch = <220>;
0481 hfront-porch = <40>;
0482 vback-porch = <21>;
0483 vfront-porch = <7>;
0484 hsync-len = <60>;
0485 vsync-len = <10>;
0486 };
0487 };
0488 };
0489 };
0490
0491 &pcie {
0492 pinctrl-names = "default";
0493 pinctrl-0 = <&pinctrl_pcie>;
0494 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
0495 status = "okay";
0496 };
0497
0498 &pwm2 {
0499 pinctrl-names = "default";
0500 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
0501 status = "disabled";
0502 };
0503
0504 &pwm3 {
0505 pinctrl-names = "default";
0506 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
0507 status = "disabled";
0508 };
0509
0510 &pwm4 {
0511 #pwm-cells = <2>;
0512 pinctrl-names = "default";
0513 pinctrl-0 = <&pinctrl_pwm4>;
0514 status = "okay";
0515 };
0516
0517 &ssi1 {
0518 status = "okay";
0519 };
0520
0521 &uart1 {
0522 pinctrl-names = "default";
0523 pinctrl-0 = <&pinctrl_uart1>;
0524 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
0525 status = "okay";
0526 };
0527
0528 &uart2 {
0529 pinctrl-names = "default";
0530 pinctrl-0 = <&pinctrl_uart2>;
0531 status = "okay";
0532 };
0533
0534 &uart5 {
0535 pinctrl-names = "default";
0536 pinctrl-0 = <&pinctrl_uart5>;
0537 status = "okay";
0538 };
0539
0540 &usbotg {
0541 vbus-supply = <®_usb_otg_vbus>;
0542 pinctrl-names = "default";
0543 pinctrl-0 = <&pinctrl_usbotg>;
0544 disable-over-current;
0545 status = "okay";
0546 };
0547
0548 &usbh1 {
0549 status = "okay";
0550 };
0551
0552 &usdhc3 {
0553 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0554 pinctrl-0 = <&pinctrl_usdhc3>;
0555 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0556 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0557 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
0558 vmmc-supply = <®_3p3v>;
0559 no-1-8-v; /* firmware will remove if board revision supports */
0560 status = "okay";
0561 };
0562
0563 &wdog1 {
0564 pinctrl-names = "default";
0565 pinctrl-0 = <&pinctrl_wdog>;
0566 fsl,ext-reset-output;
0567 };
0568
0569 &iomuxc {
0570 pinctrl_audmux: audmuxgrp {
0571 fsl,pins = <
0572 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
0573 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
0574 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
0575 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
0576 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
0577 >;
0578 };
0579
0580 pinctrl_ecspi3: escpi3grp {
0581 fsl,pins = <
0582 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
0583 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
0584 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
0585 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
0586 >;
0587 };
0588
0589 pinctrl_enet: enetgrp {
0590 fsl,pins = <
0591 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0592 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0593 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0594 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0595 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0596 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0597 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0598 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0599 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0600 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0601 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0602 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0603 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0604 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0605 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0606 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
0607 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
0608 >;
0609 };
0610
0611 pinctrl_flexcan1: flexcan1grp {
0612 fsl,pins = <
0613 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
0614 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
0615 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
0616 >;
0617 };
0618
0619 pinctrl_gpio_leds: gpioledsgrp {
0620 fsl,pins = <
0621 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
0622 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
0623 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
0624 >;
0625 };
0626
0627 pinctrl_gpmi_nand: gpminandgrp {
0628 fsl,pins = <
0629 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0630 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0631 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
0632 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0633 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0634 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0635 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0636 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0637 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0638 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0639 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0640 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0641 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0642 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0643 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0644 >;
0645 };
0646
0647 pinctrl_i2c1: i2c1grp {
0648 fsl,pins = <
0649 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
0650 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
0651 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
0652 >;
0653 };
0654
0655 pinctrl_i2c2: i2c2grp {
0656 fsl,pins = <
0657 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0658 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0659 >;
0660 };
0661
0662 pinctrl_i2c3: i2c3grp {
0663 fsl,pins = <
0664 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
0665 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0666 >;
0667 };
0668
0669 pinctrl_pcie: pciegrp {
0670 fsl,pins = <
0671 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
0672 >;
0673 };
0674
0675 pinctrl_pmic: pmicgrp {
0676 fsl,pins = <
0677 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
0678 >;
0679 };
0680
0681 pinctrl_pps: ppsgrp {
0682 fsl,pins = <
0683 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
0684 >;
0685 };
0686
0687 pinctrl_pwm2: pwm2grp {
0688 fsl,pins = <
0689 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
0690 >;
0691 };
0692
0693 pinctrl_pwm3: pwm3grp {
0694 fsl,pins = <
0695 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
0696 >;
0697 };
0698
0699 pinctrl_pwm4: pwm4grp {
0700 fsl,pins = <
0701 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
0702 >;
0703 };
0704
0705 pinctrl_uart1: uart1grp {
0706 fsl,pins = <
0707 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
0708 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
0709 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
0710 >;
0711 };
0712
0713 pinctrl_uart2: uart2grp {
0714 fsl,pins = <
0715 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
0716 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
0717 >;
0718 };
0719
0720 pinctrl_uart5: uart5grp {
0721 fsl,pins = <
0722 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
0723 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
0724 >;
0725 };
0726
0727 pinctrl_usbotg: usbotggrp {
0728 fsl,pins = <
0729 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
0730 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
0731 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059
0732 >;
0733 };
0734
0735 pinctrl_usdhc3: usdhc3grp {
0736 fsl,pins = <
0737 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0738 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0739 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0740 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0741 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0742 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0743 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
0744 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
0745 >;
0746 };
0747
0748 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
0749 fsl,pins = <
0750 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
0751 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
0752 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
0753 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
0754 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
0755 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
0756 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
0757 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
0758 >;
0759 };
0760
0761 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
0762 fsl,pins = <
0763 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
0764 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
0765 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
0766 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
0767 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
0768 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
0769 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
0770 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
0771 >;
0772 };
0773
0774 pinctrl_wdog: wdoggrp {
0775 fsl,pins = <
0776 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
0777 >;
0778 };
0779 };
