0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2021 Dillon Min <dillon.minfei@gmail.com>
0004 //
0005 // Based on imx6qdl-sabresd.dtsi which is:
0006 // Copyright 2012 Freescale Semiconductor, Inc.
0007 // Copyright 2011 Linaro Ltd.
0008
0009 #include <dt-bindings/clock/imx6qdl-clock.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/input/input.h>
0012
0013 / {
0014 chosen {
0015 stdout-path = &uart4;
0016 };
0017
0018 memory@10000000 {
0019 device_type = "memory";
0020 reg = <0x10000000 0x80000000>;
0021 };
0022
0023 reg_usb_otg_vbus: regulator-usb-otg-vbus {
0024 compatible = "regulator-fixed";
0025 regulator-name = "usb_otg_vbus";
0026 regulator-min-microvolt = <5000000>;
0027 regulator-max-microvolt = <5000000>;
0028 };
0029
0030 reg_usb_h1_vbus: regulator-usb-h1-vbus {
0031 compatible = "regulator-fixed";
0032 regulator-name = "usb_h1_vbus";
0033 regulator-min-microvolt = <5000000>;
0034 regulator-max-microvolt = <5000000>;
0035 };
0036
0037 leds {
0038 compatible = "gpio-leds";
0039 pinctrl-names = "default";
0040 pinctrl-0 = <&pinctrl_gpio_leds>;
0041
0042 led-0 {
0043 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
0044 default-state = "on";
0045 linux,default-trigger = "heartbeat";
0046 };
0047 };
0048 };
0049
0050 &ipu1_csi0_from_ipu1_csi0_mux {
0051 bus-width = <8>;
0052 data-shift = <12>; /* Lines 19:12 used */
0053 hsync-active = <1>;
0054 vsync-active = <1>;
0055 };
0056
0057 &ipu1_csi0_mux_from_parallel_sensor {
0058 remote-endpoint = <&ov2659_to_ipu1_csi0_mux>;
0059 };
0060
0061 &ipu1_csi0 {
0062 pinctrl-names = "default";
0063 pinctrl-0 = <&pinctrl_ipu1_csi0>;
0064 status = "okay";
0065 };
0066
0067 &ecspi1 {
0068 cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
0069 pinctrl-names = "default";
0070 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>;
0071 status = "okay";
0072
0073 m25p80: flash@0 {
0074 #address-cells = <1>;
0075 #size-cells = <1>;
0076 compatible = "st,m25p80", "jedec,spi-nor";
0077 spi-max-frequency = <20000000>;
0078 reg = <0>;
0079 };
0080 };
0081
0082 &fec {
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&pinctrl_enet>;
0085 phy-mode = "rgmii-id";
0086 phy-handle = <&phy>;
0087 fsl,magic-packet;
0088 status = "okay";
0089
0090 mdio {
0091 #address-cells = <1>;
0092 #size-cells = <0>;
0093
0094 phy: ethernet-phy@1 {
0095 reg = <1>;
0096 qca,clk-out-frequency = <125000000>;
0097 reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
0098 reset-assert-us = <10000>;
0099 };
0100 };
0101 };
0102
0103 &hdmi {
0104 pinctrl-names = "default";
0105 pinctrl-0 = <&pinctrl_hdmi_cec>;
0106 ddc-i2c-bus = <&i2c3>;
0107 status = "okay";
0108 };
0109
0110 &i2c2 {
0111 clock-frequency = <100000>;
0112 pinctrl-names = "default";
0113 pinctrl-0 = <&pinctrl_i2c2>;
0114 status = "okay";
0115
0116 pfuze100: pmic@8 {
0117 compatible = "fsl,pfuze100";
0118 reg = <0x08>;
0119
0120 regulators {
0121 sw1a_reg: sw1ab {
0122 regulator-min-microvolt = <300000>;
0123 regulator-max-microvolt = <1875000>;
0124 regulator-boot-on;
0125 regulator-always-on;
0126 regulator-ramp-delay = <6250>;
0127 };
0128
0129 sw1c_reg: sw1c {
0130 regulator-min-microvolt = <300000>;
0131 regulator-max-microvolt = <1875000>;
0132 regulator-boot-on;
0133 regulator-always-on;
0134 regulator-ramp-delay = <6250>;
0135 };
0136
0137 sw2_reg: sw2 {
0138 regulator-min-microvolt = <800000>;
0139 regulator-max-microvolt = <3300000>;
0140 regulator-boot-on;
0141 regulator-always-on;
0142 regulator-ramp-delay = <6250>;
0143 };
0144
0145 sw3a_reg: sw3a {
0146 regulator-min-microvolt = <400000>;
0147 regulator-max-microvolt = <1975000>;
0148 regulator-boot-on;
0149 regulator-always-on;
0150 };
0151
0152 sw3b_reg: sw3b {
0153 regulator-min-microvolt = <400000>;
0154 regulator-max-microvolt = <1975000>;
0155 regulator-boot-on;
0156 regulator-always-on;
0157 };
0158
0159 sw4_reg: sw4 {
0160 regulator-min-microvolt = <800000>;
0161 regulator-max-microvolt = <3300000>;
0162 regulator-always-on;
0163 };
0164
0165 swbst_reg: swbst {
0166 regulator-min-microvolt = <5000000>;
0167 regulator-max-microvolt = <5150000>;
0168 };
0169
0170 snvs_reg: vsnvs {
0171 regulator-min-microvolt = <1000000>;
0172 regulator-max-microvolt = <3000000>;
0173 regulator-boot-on;
0174 regulator-always-on;
0175 };
0176
0177 vref_reg: vrefddr {
0178 regulator-boot-on;
0179 regulator-always-on;
0180 };
0181
0182 vgen1_reg: vgen1 {
0183 regulator-min-microvolt = <800000>;
0184 regulator-max-microvolt = <1550000>;
0185 };
0186
0187 vgen2_reg: vgen2 {
0188 regulator-min-microvolt = <800000>;
0189 regulator-max-microvolt = <1550000>;
0190 };
0191
0192 vgen3_reg: vgen3 {
0193 regulator-min-microvolt = <1800000>;
0194 regulator-max-microvolt = <3300000>;
0195 };
0196
0197 vgen4_reg: vgen4 {
0198 regulator-min-microvolt = <1800000>;
0199 regulator-max-microvolt = <3300000>;
0200 regulator-always-on;
0201 };
0202
0203 vgen5_reg: vgen5 {
0204 regulator-min-microvolt = <1800000>;
0205 regulator-max-microvolt = <3300000>;
0206 regulator-always-on;
0207 };
0208
0209 vgen6_reg: vgen6 {
0210 regulator-min-microvolt = <1800000>;
0211 regulator-max-microvolt = <3300000>;
0212 regulator-always-on;
0213 };
0214 };
0215 };
0216 };
0217
0218 &i2c3 {
0219 clock-frequency = <100000>;
0220 pinctrl-names = "default";
0221 pinctrl-0 = <&pinctrl_i2c3>;
0222 status = "okay";
0223
0224 ov2659: camera@30 {
0225 compatible = "ovti,ov2659";
0226 pinctrl-names = "default";
0227 pinctrl-0 = <&pinctrl_ov2659>;
0228 clocks = <&clks IMX6QDL_CLK_CKO>;
0229 clock-names = "xvclk";
0230 reg = <0x30>;
0231 powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
0232 reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
0233 status = "okay";
0234
0235 port {
0236 ov2659_to_ipu1_csi0_mux: endpoint {
0237 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
0238 link-frequencies = /bits/ 64 <70000000>;
0239 bus-width = <8>;
0240 hsync-active = <1>;
0241 vsync-active = <1>;
0242 };
0243 };
0244 };
0245 };
0246
0247 &iomuxc {
0248 pinctrl_ecspi1: ecspi1grp {
0249 fsl,pins = <
0250 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
0251 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
0252 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0253 >;
0254 };
0255
0256 pinctrl_ecspi1_gpio: ecspi1grpgpiogrp {
0257 fsl,pins = <
0258 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
0259 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
0260 >;
0261 };
0262
0263 pinctrl_enet: enetgrp {
0264 fsl,pins = <
0265 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0266 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0267 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0268 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0269 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0270 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0271 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0272 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0273 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0274 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0275 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0276 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0277 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0278 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0279 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0280 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
0281 >;
0282 };
0283
0284 pinctrl_hdmi_cec: hdmicecgrp {
0285 fsl,pins = <
0286 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
0287 >;
0288 };
0289
0290 pinctrl_i2c2: i2c2grp {
0291 fsl,pins = <
0292 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
0293 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0294 >;
0295 };
0296
0297 pinctrl_i2c3: i2c3grp {
0298 fsl,pins = <
0299 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
0300 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0301 >;
0302 };
0303
0304 pinctrl_ipu1_csi0: ipu1csi0grp {
0305 fsl,pins = <
0306 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
0307 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
0308 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
0309 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
0310 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
0311 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
0312 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
0313 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
0314 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
0315 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
0316 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
0317 >;
0318 };
0319
0320 pinctrl_ov2659: ov2659grp {
0321 fsl,pins = <
0322 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0
0323 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
0324 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
0325 >;
0326 };
0327
0328 pinctrl_uart4: uart4grp {
0329 fsl,pins = <
0330 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
0331 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
0332 >;
0333 };
0334
0335 pinctrl_usbotg: usbotggrp {
0336 fsl,pins = <
0337 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
0338 >;
0339 };
0340
0341 pinctrl_usdhc1: usdhc1grp {
0342 fsl,pins = <
0343 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
0344 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
0345 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
0346 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
0347 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
0348 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
0349 >;
0350 };
0351
0352 pinctrl_usdhc1_gpio: usdhc1grpgpiogrp {
0353 fsl,pins = <
0354 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
0355 >;
0356 };
0357
0358 pinctrl_usdhc2: usdhc2grp {
0359 fsl,pins = <
0360 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0361 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0362 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0363 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0364 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0365 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0366 >;
0367 };
0368
0369 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
0370 fsl,pins = <
0371 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
0372 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
0373 >;
0374 };
0375
0376 pinctrl_usdhc3: usdhc3grp {
0377 fsl,pins = <
0378 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0379 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0380 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0381 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0382 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0383 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0384 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
0385 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
0386 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
0387 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
0388 >;
0389 };
0390
0391 pinctrl_wdog: wdoggrp {
0392 fsl,pins = <
0393 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
0394 >;
0395 };
0396
0397 pinctrl_gpio_leds: gpioledsgrp {
0398 fsl,pins = <
0399 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
0400 >;
0401 };
0402 };
0403
0404 &uart4 {
0405 pinctrl-names = "default";
0406 pinctrl-0 = <&pinctrl_uart4>;
0407 status = "okay";
0408 };
0409
0410 &usbh1 {
0411 vbus-supply = <®_usb_h1_vbus>;
0412 status = "okay";
0413 };
0414
0415 &usbotg {
0416 vbus-supply = <®_usb_otg_vbus>;
0417 pinctrl-names = "default";
0418 pinctrl-0 = <&pinctrl_usbotg>;
0419 disable-over-current;
0420 status = "okay";
0421 };
0422
0423 &usdhc1 {
0424 pinctrl-names = "default";
0425 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
0426 bus-width = <4>;
0427 cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
0428 status = "okay";
0429 };
0430
0431 &usdhc2 {
0432 pinctrl-names = "default";
0433 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0434 bus-width = <4>;
0435 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
0436 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
0437 status = "disabled";
0438 };
0439
0440 &usdhc3 {
0441 pinctrl-names = "default";
0442 pinctrl-0 = <&pinctrl_usdhc3>;
0443 bus-width = <8>;
0444 non-removable;
0445 no-1-8-v;
0446 status = "okay";
0447 };
0448
0449 &wdog1 {
0450 status = "disabled";
0451 };
0452
0453 &wdog2 {
0454 pinctrl-names = "default";
0455 pinctrl-0 = <&pinctrl_wdog>;
0456 fsl,ext-reset-output;
0457 status = "okay";
0458 };
