0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (C) 2015-2021 DH electronics GmbH
0004 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
0005 */
0006
0007 #include <dt-bindings/pwm/pwm.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/clock/imx6qdl-clock.h>
0010 #include <dt-bindings/input/input.h>
0011
0012 / {
0013 aliases {
0014 i2c0 = &i2c2;
0015 i2c1 = &i2c1;
0016 i2c2 = &i2c3;
0017 mmc0 = &usdhc2;
0018 mmc1 = &usdhc3;
0019 mmc2 = &usdhc4;
0020 mmc3 = &usdhc1;
0021 rtc0 = &rtc_i2c;
0022 rtc1 = &snvs_rtc;
0023 serial0 = &uart1;
0024 serial1 = &uart5;
0025 serial2 = &uart4;
0026 serial3 = &uart2;
0027 serial4 = &uart3;
0028 };
0029
0030 memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
0031 device_type = "memory";
0032 reg = <0x10000000 0x20000000>;
0033 };
0034
0035 reg_3p3v: regulator-3P3V {
0036 compatible = "regulator-fixed";
0037 regulator-always-on;
0038 regulator-min-microvolt = <3300000>;
0039 regulator-max-microvolt = <3300000>;
0040 regulator-name = "3P3V";
0041 };
0042
0043 reg_eth_vio: regulator-eth-vio {
0044 compatible = "regulator-fixed";
0045 gpio = <&gpio1 7 0>;
0046 pinctrl-0 = <&pinctrl_enet_vio>;
0047 pinctrl-names = "default";
0048 regulator-always-on;
0049 regulator-boot-on;
0050 regulator-min-microvolt = <3300000>;
0051 regulator-max-microvolt = <3300000>;
0052 regulator-name = "eth_vio";
0053 vin-supply = <&sw2_reg>;
0054 };
0055
0056 /* OE pin of the latch is low active */
0057 reg_latch_oe_on: regulator-latch-oe-on {
0058 compatible = "regulator-fixed";
0059 gpio = <&gpio3 22 0>;
0060 regulator-always-on;
0061 regulator-name = "latch_oe_on";
0062 };
0063
0064 reg_usb_h1_vbus: regulator-usb-h1-vbus {
0065 compatible = "regulator-fixed";
0066 enable-active-high;
0067 gpio = <&gpio3 31 0>;
0068 regulator-min-microvolt = <5000000>;
0069 regulator-max-microvolt = <5000000>;
0070 regulator-name = "usb_h1_vbus";
0071 };
0072
0073 reg_usb_otg_vbus: regulator-usb-otg-vbus {
0074 compatible = "regulator-fixed";
0075 regulator-min-microvolt = <5000000>;
0076 regulator-max-microvolt = <5000000>;
0077 regulator-name = "usb_otg_vbus";
0078 };
0079 };
0080
0081 &can1 {
0082 pinctrl-0 = <&pinctrl_flexcan1>;
0083 pinctrl-names = "default";
0084 status = "okay";
0085 };
0086
0087 /*
0088 * Special SoM hardware required which uses the pins from micro SD card. The
0089 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
0090 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on
0091 * the board device tree file, the micro SD card must be disabled and the uart1
0092 * rts/cts must be disabled or output on other DHCOM pins.
0093 */
0094 &can2 {
0095 pinctrl-0 = <&pinctrl_flexcan2>;
0096 pinctrl-names = "default";
0097 status = "disabled";
0098 };
0099
0100 &ecspi1 {
0101 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
0102 pinctrl-0 = <&pinctrl_ecspi1>;
0103 pinctrl-names = "default";
0104 status = "okay";
0105
0106 flash@0 { /* S25FL116K */
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 compatible = "jedec,spi-nor";
0110 m25p,fast-read;
0111 reg = <0>;
0112 spi-max-frequency = <50000000>;
0113 };
0114 };
0115
0116 &ecspi2 {
0117 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
0118 pinctrl-0 = <&pinctrl_ecspi2>;
0119 pinctrl-names = "default";
0120 status = "disabled";
0121 };
0122
0123 &fec {
0124 phy-mode = "rmii";
0125 phy-handle = <ðphy0>;
0126 pinctrl-0 = <&pinctrl_enet_100M>;
0127 pinctrl-names = "default";
0128 status = "okay";
0129
0130 mdio {
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133
0134 ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
0135 compatible = "ethernet-phy-id0007.c0f0",
0136 "ethernet-phy-ieee802.3-c22";
0137 interrupt-parent = <&gpio4>;
0138 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
0139 pinctrl-0 = <&pinctrl_ethphy0>;
0140 pinctrl-names = "default";
0141 reg = <0>;
0142 reset-assert-us = <500>;
0143 reset-deassert-us = <500>;
0144 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
0145 smsc,disable-energy-detect; /* Make plugin detection reliable */
0146 };
0147 };
0148 };
0149
0150 &gpio1 {
0151 gpio-line-names =
0152 "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
0153 "", "", "", "", "", "", "", "",
0154 "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
0155 "", "", "", "", "", "", "", "";
0156 };
0157
0158 &gpio2 {
0159 gpio-line-names =
0160 "", "", "", "", "", "", "", "",
0161 "", "", "", "", "", "", "", "",
0162 "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
0163 "", "", "", "", "", "", "", "";
0164 };
0165
0166 &gpio3 {
0167 gpio-line-names =
0168 "", "", "", "", "", "", "", "",
0169 "", "", "", "", "", "", "", "",
0170 "", "", "", "", "", "", "", "",
0171 "", "", "", "DHCOM-G", "", "", "", "";
0172 };
0173
0174 &gpio4 {
0175 gpio-line-names =
0176 "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
0177 "DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
0178 "", "", "", "", "DHCOM-F", "", "", "",
0179 "", "", "", "", "", "", "", "";
0180 };
0181
0182 &gpio5 {
0183 gpio-line-names =
0184 "", "", "", "", "", "", "", "",
0185 "", "", "", "", "", "", "", "",
0186 "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
0187 "", "", "", "", "", "", "", "";
0188 };
0189
0190 &gpio6 {
0191 gpio-line-names =
0192 "", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
0193 "", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
0194 "", "", "", "", "", "", "", "",
0195 "", "", "", "", "", "", "", "";
0196 };
0197
0198 &gpio7 {
0199 gpio-line-names =
0200 "DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
0201 "", "", "", "", "", "DHCOM-P", "", "",
0202 "", "", "", "", "", "", "", "",
0203 "", "", "", "", "", "", "", "";
0204 };
0205
0206 &i2c1 {
0207 /*
0208 * Info: According to erratum ERR007805 clock frequency limit is 375000.
0209 * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
0210 * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
0211 * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
0212 */
0213 clock-frequency = <100000>;
0214 pinctrl-0 = <&pinctrl_i2c1>;
0215 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0216 pinctrl-names = "default", "gpio";
0217 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0218 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0219 status = "okay";
0220 };
0221
0222 &i2c2 {
0223 /* Info: Clock frequency limit is 375000 (for details see i2c1) */
0224 clock-frequency = <100000>;
0225 pinctrl-0 = <&pinctrl_i2c2>;
0226 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0227 pinctrl-names = "default", "gpio";
0228 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0229 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0230 status = "okay";
0231 };
0232
0233 &i2c3 {
0234 /* Info: Clock frequency limit is 375000 (for details see i2c1) */
0235 clock-frequency = <100000>;
0236 pinctrl-0 = <&pinctrl_i2c3>;
0237 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0238 pinctrl-names = "default", "gpio";
0239 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0240 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0241 status = "okay";
0242
0243 ltc3676: pmic@3c {
0244 compatible = "lltc,ltc3676";
0245 interrupt-parent = <&gpio5>;
0246 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
0247 pinctrl-0 = <&pinctrl_pmic>;
0248 pinctrl-names = "default";
0249 reg = <0x3c>;
0250
0251 regulators {
0252 sw1_reg: sw1 {
0253 lltc,fb-voltage-divider = <100000 110000>;
0254 regulator-always-on;
0255 regulator-boot-on;
0256 regulator-max-microvolt = <1527272>;
0257 regulator-min-microvolt = <787500>;
0258 regulator-ramp-delay = <7000>;
0259 regulator-suspend-mem-microvolt = <1040000>;
0260 };
0261
0262 sw2_reg: sw2 {
0263 lltc,fb-voltage-divider = <100000 28000>;
0264 regulator-always-on;
0265 regulator-boot-on;
0266 regulator-max-microvolt = <3657142>;
0267 regulator-min-microvolt = <1885714>;
0268 regulator-ramp-delay = <7000>;
0269 };
0270
0271 sw3_reg: sw3 {
0272 lltc,fb-voltage-divider = <100000 110000>;
0273 regulator-always-on;
0274 regulator-boot-on;
0275 regulator-max-microvolt = <1527272>;
0276 regulator-min-microvolt = <787500>;
0277 regulator-ramp-delay = <7000>;
0278 regulator-suspend-mem-microvolt = <980000>;
0279 };
0280
0281 sw4_reg: sw4 {
0282 lltc,fb-voltage-divider = <100000 93100>;
0283 regulator-always-on;
0284 regulator-boot-on;
0285 regulator-max-microvolt = <1659291>;
0286 regulator-min-microvolt = <855571>;
0287 regulator-ramp-delay = <7000>;
0288 };
0289
0290 ldo1_reg: ldo1 {
0291 lltc,fb-voltage-divider = <102000 29400>;
0292 regulator-always-on;
0293 regulator-boot-on;
0294 regulator-max-microvolt = <3240306>;
0295 regulator-min-microvolt = <3240306>;
0296 };
0297
0298 ldo2_reg: ldo2 {
0299 lltc,fb-voltage-divider = <100000 41200>;
0300 regulator-always-on;
0301 regulator-boot-on;
0302 regulator-max-microvolt = <2484708>;
0303 regulator-min-microvolt = <2484708>;
0304 };
0305 };
0306 };
0307
0308 touchscreen@49 { /* TSC2004 */
0309 compatible = "ti,tsc2004";
0310 interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
0311 pinctrl-0 = <&pinctrl_tsc2004>;
0312 pinctrl-names = "default";
0313 reg = <0x49>;
0314 vio-supply = <®_3p3v>;
0315 status = "disabled";
0316 };
0317
0318 eeprom@50 {
0319 compatible = "atmel,24c02";
0320 pagesize = <16>;
0321 reg = <0x50>;
0322 };
0323
0324 rtc_i2c: rtc@56 {
0325 compatible = "microcrystal,rv3029";
0326 interrupt-parent = <&gpio7>;
0327 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
0328 pinctrl-0 = <&pinctrl_rtc>;
0329 pinctrl-names = "default";
0330 reg = <0x56>;
0331 };
0332 };
0333
0334 &pcie {
0335 pinctrl-0 = <&pinctrl_pcie>;
0336 pinctrl-names = "default";
0337 };
0338
0339 &pwm1 {
0340 pinctrl-0 = <&pinctrl_pwm1>;
0341 pinctrl-names = "default";
0342 };
0343
0344 ®_arm {
0345 vin-supply = <&sw3_reg>;
0346 };
0347
0348 ®_pu {
0349 vin-supply = <&sw1_reg>;
0350 };
0351
0352 ®_soc {
0353 vin-supply = <&sw1_reg>;
0354 };
0355
0356 ®_vdd1p1 {
0357 vin-supply = <&sw2_reg>;
0358 };
0359
0360 ®_vdd2p5 {
0361 vin-supply = <&sw2_reg>;
0362 };
0363
0364 &uart1 { /* DHCOM UART1 */
0365 dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
0366 dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
0367 dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
0368 rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
0369 pinctrl-0 = <&pinctrl_uart1>;
0370 pinctrl-names = "default";
0371 uart-has-rtscts;
0372 status = "okay";
0373 };
0374
0375 &uart4 { /* DHCOM UART3 */
0376 pinctrl-0 = <&pinctrl_uart4>;
0377 pinctrl-names = "default";
0378 status = "okay";
0379 };
0380
0381 &uart5 { /* DHCOM UART2 */
0382 pinctrl-0 = <&pinctrl_uart5>;
0383 pinctrl-names = "default";
0384 uart-has-rtscts;
0385 status = "okay";
0386 };
0387
0388 &usbh1 {
0389 dr_mode = "host";
0390 pinctrl-0 = <&pinctrl_usbh1>;
0391 pinctrl-names = "default";
0392 vbus-supply = <®_usb_h1_vbus>;
0393 status = "okay";
0394 };
0395
0396 &usbotg {
0397 disable-over-current;
0398 dr_mode = "otg";
0399 pinctrl-0 = <&pinctrl_usbotg>;
0400 pinctrl-names = "default";
0401 vbus-supply = <®_usb_otg_vbus>;
0402 status = "okay";
0403 };
0404
0405 &usdhc2 { /* External SD card via DHCOM */
0406 cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
0407 keep-power-in-suspend;
0408 pinctrl-0 = <&pinctrl_usdhc2>;
0409 pinctrl-names = "default";
0410 status = "disabled";
0411 };
0412
0413 &usdhc3 { /* Micro SD card on module */
0414 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
0415 fsl,wp-controller;
0416 keep-power-in-suspend;
0417 pinctrl-0 = <&pinctrl_usdhc3>;
0418 pinctrl-names = "default";
0419 status = "okay";
0420 };
0421
0422 &usdhc4 { /* eMMC on module */
0423 bus-width = <8>;
0424 keep-power-in-suspend;
0425 no-1-8-v;
0426 non-removable;
0427 pinctrl-0 = <&pinctrl_usdhc4>;
0428 pinctrl-names = "default";
0429 status = "okay";
0430 };
0431
0432 &weim {
0433 #address-cells = <2>;
0434 #size-cells = <1>;
0435 fsl,weim-cs-gpr = <&gpr>;
0436 pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
0437 pinctrl-names = "default";
0438 /* It is necessary to setup 2x 64MB otherwise setting gpr fails */
0439 ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
0440 <1 0 0x0c000000 0x04000000>; /* CS1 */
0441 status = "disabled";
0442 };
0443
0444 &iomuxc {
0445 pinctrl-0 = <
0446 &pinctrl_hog_base
0447 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
0448 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
0449 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
0450 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
0451 &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
0452 &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
0453 &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
0454 &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
0455 >;
0456 pinctrl-names = "default";
0457
0458 pinctrl_hog_base: hog-base-grp {
0459 fsl,pins = <
0460 /* GPIOs for memory coding */
0461 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
0462 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
0463 /* GPIOs for hardware coding */
0464 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
0465 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
0466 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
0467 >;
0468 };
0469
0470 /* DHCOM GPIOs */
0471 pinctrl_dhcom_a: dhcom-a-grp {
0472 fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>;
0473 };
0474
0475 pinctrl_dhcom_b: dhcom-b-grp {
0476 fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>;
0477 };
0478
0479 pinctrl_dhcom_c: dhcom-c-grp {
0480 fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>;
0481 };
0482
0483 pinctrl_dhcom_d: dhcom-d-grp {
0484 fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>;
0485 };
0486
0487 pinctrl_dhcom_e: dhcom-e-grp {
0488 fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>;
0489 };
0490
0491 pinctrl_dhcom_f: dhcom-f-grp {
0492 fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
0493 };
0494
0495 pinctrl_dhcom_g: dhcom-g-grp {
0496 fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>;
0497 };
0498
0499 pinctrl_dhcom_h: dhcom-h-grp {
0500 fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>;
0501 };
0502
0503 pinctrl_dhcom_i: dhcom-i-grp {
0504 fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>;
0505 };
0506
0507 pinctrl_dhcom_j: dhcom-j-grp {
0508 fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>;
0509 };
0510
0511 pinctrl_dhcom_k: dhcom-k-grp {
0512 fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>;
0513 };
0514
0515 pinctrl_dhcom_l: dhcom-l-grp {
0516 fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>;
0517 };
0518
0519 pinctrl_dhcom_m: dhcom-m-grp {
0520 fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>;
0521 };
0522
0523 pinctrl_dhcom_n: dhcom-n-grp {
0524 fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>;
0525 };
0526
0527 pinctrl_dhcom_o: dhcom-o-grp {
0528 fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;
0529 };
0530
0531 pinctrl_dhcom_p: dhcom-p-grp {
0532 fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>;
0533 };
0534
0535 pinctrl_dhcom_q: dhcom-q-grp {
0536 fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>;
0537 };
0538
0539 pinctrl_dhcom_r: dhcom-r-grp {
0540 fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>;
0541 };
0542
0543 pinctrl_dhcom_s: dhcom-s-grp {
0544 fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>;
0545 };
0546
0547 pinctrl_dhcom_t: dhcom-t-grp {
0548 fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>;
0549 };
0550
0551 pinctrl_dhcom_u: dhcom-u-grp {
0552 fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>;
0553 };
0554
0555 pinctrl_dhcom_v: dhcom-v-grp {
0556 fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>;
0557 };
0558
0559 pinctrl_dhcom_w: dhcom-w-grp {
0560 fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>;
0561 };
0562
0563 pinctrl_dhcom_int: dhcom-int-grp {
0564 fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>;
0565 };
0566
0567 pinctrl_ecspi1: ecspi1-grp {
0568 fsl,pins = <
0569 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
0570 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0571 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
0572 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
0573 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
0574 >;
0575 };
0576
0577 pinctrl_ecspi2: ecspi2-grp {
0578 fsl,pins = <
0579 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
0580 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
0581 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
0582 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
0583 >;
0584 };
0585
0586 pinctrl_enet_100M: enet-100M-grp {
0587 fsl,pins = <
0588 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
0589 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0590 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0591 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
0592 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
0593 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
0594 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
0595 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
0596 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
0597 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
0598 >;
0599 };
0600
0601 pinctrl_enet_vio: enet-vio-grp {
0602 fsl,pins = <
0603 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
0604 >;
0605 };
0606
0607 pinctrl_ethphy0: ethphy0-grp {
0608 fsl,pins = <
0609 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */
0610 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */
0611 >;
0612 };
0613
0614 pinctrl_flexcan1: flexcan1-grp {
0615 fsl,pins = <
0616 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
0617 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
0618 >;
0619 };
0620
0621 pinctrl_flexcan2: flexcan2-grp {
0622 fsl,pins = <
0623 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
0624 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
0625 >;
0626 };
0627
0628 pinctrl_i2c1: i2c1-grp {
0629 fsl,pins = <
0630 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
0631 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
0632 >;
0633 };
0634
0635 pinctrl_i2c1_gpio: i2c1-gpio-grp {
0636 fsl,pins = <
0637 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
0638 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
0639 >;
0640 };
0641
0642 pinctrl_i2c2: i2c2-grp {
0643 fsl,pins = <
0644 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0645 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0646 >;
0647 };
0648
0649 pinctrl_i2c2_gpio: i2c2-gpio-grp {
0650 fsl,pins = <
0651 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
0652 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
0653 >;
0654 };
0655
0656 pinctrl_i2c3: i2c3-grp {
0657 fsl,pins = <
0658 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
0659 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0660 >;
0661 };
0662
0663 pinctrl_i2c3_gpio: i2c3-gpio-grp {
0664 fsl,pins = <
0665 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
0666 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
0667 >;
0668 };
0669
0670 pinctrl_pcie: pcie-grp {
0671 fsl,pins = <
0672 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
0673 >;
0674 };
0675
0676 pinctrl_pmic: pmic-grp {
0677 fsl,pins = <
0678 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
0679 >;
0680 };
0681
0682 pinctrl_pwm1: pwm1-grp {
0683 fsl,pins = <
0684 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
0685 >;
0686 };
0687
0688 pinctrl_rtc: rtc-grp {
0689 fsl,pins = <
0690 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0
0691 >;
0692 };
0693
0694 pinctrl_tsc2004: tsc2004-grp {
0695 fsl,pins = <
0696 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0
0697 >;
0698 };
0699
0700 pinctrl_uart1: uart1-grp {
0701 fsl,pins = <
0702 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
0703 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
0704 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
0705 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
0706 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
0707 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
0708 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
0709 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
0710 >;
0711 };
0712
0713 pinctrl_uart4: uart4-grp {
0714 fsl,pins = <
0715 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
0716 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
0717 >;
0718 };
0719
0720 pinctrl_uart5: uart5-grp {
0721 fsl,pins = <
0722 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
0723 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
0724 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
0725 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
0726 >;
0727 };
0728
0729 pinctrl_usbh1: usbh1-grp {
0730 fsl,pins = <
0731 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
0732 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1
0733 >;
0734 };
0735
0736 pinctrl_usbotg: usbotg-grp {
0737 fsl,pins = <
0738 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
0739 >;
0740 };
0741
0742 pinctrl_usdhc2: usdhc2-grp {
0743 fsl,pins = <
0744 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0
0745 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0746 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0747 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0748 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0749 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0750 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0751 >;
0752 };
0753
0754 pinctrl_usdhc3: usdhc3-grp {
0755 fsl,pins = <
0756 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0757 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0758 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0759 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0760 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0761 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0762 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0
0763 >;
0764 };
0765
0766 pinctrl_usdhc4: usdhc4-grp {
0767 fsl,pins = <
0768 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
0769 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
0770 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
0771 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
0772 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
0773 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
0774 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
0775 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
0776 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
0777 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
0778 >;
0779 };
0780
0781 pinctrl_weim: weim-grp {
0782 fsl,pins = <
0783 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6
0784 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6
0785 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6
0786 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6
0787 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6
0788 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6
0789 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6
0790 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6
0791 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6
0792 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6
0793 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6
0794 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6
0795 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6
0796 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6
0797 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6
0798 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6
0799 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
0800 MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */
0801 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6
0802 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */
0803 >;
0804 };
0805
0806 pinctrl_weim_cs0: weim-cs0-grp {
0807 fsl,pins = <
0808 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
0809 >;
0810 };
0811
0812 pinctrl_weim_cs1: weim-cs1-grp {
0813 fsl,pins = <
0814 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
0815 >;
0816 };
0817 };
