0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 /*
0003 * Copyright 2014-2022 Toradex
0004 * Copyright 2012 Freescale Semiconductor, Inc.
0005 * Copyright 2011 Linaro Ltd.
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/pwm/pwm.h>
0010
0011 / {
0012 model = "Toradex Colibri iMX6DL/S Module";
0013 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
0014
0015 backlight: backlight {
0016 compatible = "pwm-backlight";
0017 brightness-levels = <0 45 63 88 119 158 203 255>;
0018 default-brightness-level = <4>;
0019 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
0020 pinctrl-names = "default";
0021 pinctrl-0 = <&pinctrl_gpio_bl_on>;
0022 power-supply = <®_module_3v3>;
0023 pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>;
0024 status = "disabled";
0025 };
0026
0027 gpio-keys {
0028 compatible = "gpio-keys";
0029 pinctrl-names = "default";
0030 pinctrl-0 = <&pinctrl_gpio_keys>;
0031
0032 wakeup {
0033 debounce-interval = <10>;
0034 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
0035 label = "Wake-Up";
0036 linux,code = <KEY_WAKEUP>;
0037 wakeup-source;
0038 };
0039 };
0040
0041 lcd_display: disp0 {
0042 compatible = "fsl,imx-parallel-display";
0043 interface-pix-fmt = "bgr666";
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
0046 status = "disabled";
0047
0048 #address-cells = <1>;
0049 #size-cells = <0>;
0050
0051 port@0 {
0052 reg = <0>;
0053
0054 lcd_display_in: endpoint {
0055 remote-endpoint = <&ipu1_di0_disp0>;
0056 };
0057 };
0058
0059 port@1 {
0060 reg = <1>;
0061
0062 lcd_display_out: endpoint {
0063 remote-endpoint = <&lcd_panel_in>;
0064 };
0065 };
0066 };
0067
0068 /* Will be filled by the bootloader */
0069 memory@10000000 {
0070 device_type = "memory";
0071 reg = <0x10000000 0>;
0072 };
0073
0074 panel_dpi: panel-dpi {
0075 /*
0076 * edt,et057090dhu: EDT 5.7" LCD TFT
0077 * edt,et070080dh6: EDT 7.0" LCD TFT
0078 */
0079 compatible = "edt,et057090dhu";
0080 backlight = <&backlight>;
0081 status = "disabled";
0082
0083 port {
0084 lcd_panel_in: endpoint {
0085 remote-endpoint = <&lcd_display_out>;
0086 };
0087 };
0088 };
0089
0090 reg_module_3v3: regulator-module-3v3 {
0091 compatible = "regulator-fixed";
0092 regulator-name = "+V3.3";
0093 regulator-min-microvolt = <3300000>;
0094 regulator-max-microvolt = <3300000>;
0095 regulator-always-on;
0096 };
0097
0098 reg_module_3v3_audio: regulator-module-3v3-audio {
0099 compatible = "regulator-fixed";
0100 regulator-name = "+V3.3_AUDIO";
0101 regulator-min-microvolt = <3300000>;
0102 regulator-max-microvolt = <3300000>;
0103 regulator-always-on;
0104 };
0105
0106 reg_usb_host_vbus: regulator-usb-host-vbus {
0107 compatible = "regulator-fixed";
0108 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
0111 regulator-max-microvolt = <5000000>;
0112 regulator-min-microvolt = <5000000>;
0113 regulator-name = "usb_host_vbus";
0114 status = "disabled";
0115 };
0116
0117 sound {
0118 compatible = "fsl,imx-audio-sgtl5000";
0119 audio-codec = <&codec>;
0120 audio-routing =
0121 "Headphone Jack", "HP_OUT",
0122 "LINE_IN", "Line In Jack",
0123 "MIC_IN", "Mic Jack",
0124 "Mic Jack", "Mic Bias";
0125 model = "imx6dl-colibri-sgtl5000";
0126 mux-int-port = <1>;
0127 mux-ext-port = <5>;
0128 ssi-controller = <&ssi1>;
0129 };
0130
0131 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
0132 sound_spdif: sound-spdif {
0133 compatible = "fsl,imx-audio-spdif";
0134 spdif-controller = <&spdif>;
0135 spdif-in;
0136 spdif-out;
0137 model = "imx-spdif";
0138 status = "disabled";
0139 };
0140 };
0141
0142 &audmux {
0143 pinctrl-names = "default";
0144 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
0145 status = "okay";
0146 };
0147
0148 /* Optional on SODIMM 55/63 */
0149 &can1 {
0150 pinctrl-names = "default";
0151 pinctrl-0 = <&pinctrl_flexcan1>;
0152 status = "disabled";
0153 };
0154
0155 /* Optional on SODIMM 178/188 */
0156 &can2 {
0157 pinctrl-names = "default";
0158 pinctrl-0 = <&pinctrl_flexcan2>;
0159 status = "disabled";
0160 };
0161
0162 &clks {
0163 fsl,pmic-stby-poweroff;
0164 };
0165
0166 /* Colibri SSP */
0167 &ecspi4 {
0168 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
0169 pinctrl-names = "default";
0170 pinctrl-0 = <&pinctrl_ecspi4>;
0171 status = "disabled";
0172 };
0173
0174 &fec {
0175 phy-mode = "rmii";
0176 phy-handle = <ðphy>;
0177 pinctrl-names = "default";
0178 pinctrl-0 = <&pinctrl_enet>;
0179 status = "okay";
0180
0181 mdio {
0182 #address-cells = <1>;
0183 #size-cells = <0>;
0184
0185 ethphy: ethernet-phy@0 {
0186 reg = <0>;
0187 micrel,led-mode = <0>;
0188 };
0189 };
0190 };
0191
0192 &gpio1 {
0193 gpio-line-names = "",
0194 "SODIMM_67",
0195 "SODIMM_180",
0196 "SODIMM_196",
0197 "SODIMM_174",
0198 "SODIMM_176",
0199 "SODIMM_194",
0200 "SODIMM_55",
0201 "SODIMM_63",
0202 "SODIMM_28",
0203 "SODIMM_93",
0204 "SODIMM_69",
0205 "SODIMM_99",
0206 "SODIMM_130",
0207 "SODIMM_106",
0208 "SODIMM_98",
0209 "SODIMM_192",
0210 "SODIMM_49",
0211 "SODIMM_190",
0212 "SODIMM_51",
0213 "SODIMM_47",
0214 "SODIMM_53",
0215 "",
0216 "SODIMM_22";
0217 };
0218
0219 &gpio2 {
0220 gpio-line-names = "SODIMM_132",
0221 "SODIMM_134",
0222 "SODIMM_135",
0223 "SODIMM_133",
0224 "SODIMM_102",
0225 "SODIMM_43",
0226 "SODIMM_127",
0227 "SODIMM_37",
0228 "SODIMM_104",
0229 "SODIMM_59",
0230 "SODIMM_30",
0231 "SODIMM_100",
0232 "SODIMM_38",
0233 "SODIMM_34",
0234 "SODIMM_32",
0235 "SODIMM_36",
0236 "SODIMM_59",
0237 "SODIMM_67",
0238 "SODIMM_97",
0239 "SODIMM_79",
0240 "SODIMM_103",
0241 "SODIMM_101",
0242 "SODIMM_45",
0243 "SODIMM_105",
0244 "SODIMM_107",
0245 "SODIMM_91",
0246 "SODIMM_89",
0247 "SODIMM_150",
0248 "SODIMM_126",
0249 "SODIMM_128",
0250 "",
0251 "SODIMM_94";
0252 };
0253
0254 &gpio3 {
0255 gpio-line-names = "SODIMM_111",
0256 "SODIMM_113",
0257 "SODIMM_115",
0258 "SODIMM_117",
0259 "SODIMM_119",
0260 "SODIMM_121",
0261 "SODIMM_123",
0262 "SODIMM_125",
0263 "SODIMM_110",
0264 "SODIMM_112",
0265 "SODIMM_114",
0266 "SODIMM_116",
0267 "SODIMM_118",
0268 "SODIMM_120",
0269 "SODIMM_122",
0270 "SODIMM_124",
0271 "",
0272 "SODIMM_96",
0273 "SODIMM_77",
0274 "SODIMM_25",
0275 "SODIMM_27",
0276 "SODIMM_88",
0277 "SODIMM_90",
0278 "SODIMM_31",
0279 "SODIMM_23",
0280 "SODIMM_29",
0281 "SODIMM_71",
0282 "SODIMM_73",
0283 "SODIMM_92",
0284 "SODIMM_81",
0285 "SODIMM_131",
0286 "SODIMM_129";
0287 };
0288
0289 &gpio4 {
0290 gpio-line-names = "",
0291 "",
0292 "",
0293 "",
0294 "",
0295 "SODIMM_168",
0296 "",
0297 "",
0298 "",
0299 "",
0300 "SODIMM_184",
0301 "SODIMM_186",
0302 "HDMI_15",
0303 "HDMI_16",
0304 "SODIMM_178",
0305 "SODIMM_188",
0306 "SODIMM_56",
0307 "SODIMM_44",
0308 "SODIMM_68",
0309 "SODIMM_82",
0310 "SODIMM_24",
0311 "SODIMM_76",
0312 "SODIMM_70",
0313 "SODIMM_60",
0314 "SODIMM_58",
0315 "SODIMM_78",
0316 "SODIMM_72",
0317 "SODIMM_80",
0318 "SODIMM_46",
0319 "SODIMM_62",
0320 "SODIMM_48",
0321 "SODIMM_74";
0322 };
0323
0324 &gpio5 {
0325 gpio-line-names = "SODIMM_95",
0326 "",
0327 "SODIMM_86",
0328 "",
0329 "SODIMM_65",
0330 "SODIMM_50",
0331 "SODIMM_52",
0332 "SODIMM_54",
0333 "SODIMM_66",
0334 "SODIMM_64",
0335 "SODIMM_57",
0336 "SODIMM_61",
0337 "SODIMM_136",
0338 "SODIMM_138",
0339 "SODIMM_140",
0340 "SODIMM_142",
0341 "SODIMM_144",
0342 "SODIMM_146",
0343 "SODIMM_172",
0344 "SODIMM_170",
0345 "SODIMM_149",
0346 "SODIMM_151",
0347 "SODIMM_153",
0348 "SODIMM_155",
0349 "SODIMM_157",
0350 "SODIMM_159",
0351 "SODIMM_161",
0352 "SODIMM_163",
0353 "SODIMM_33",
0354 "SODIMM_35",
0355 "SODIMM_165",
0356 "SODIMM_167";
0357 };
0358
0359 &gpio6 {
0360 gpio-line-names = "SODIMM_169",
0361 "SODIMM_171",
0362 "SODIMM_173",
0363 "SODIMM_175",
0364 "SODIMM_177",
0365 "SODIMM_179",
0366 "SODIMM_85",
0367 "SODIMM_166",
0368 "SODIMM_160",
0369 "SODIMM_162",
0370 "SODIMM_158",
0371 "SODIMM_164",
0372 "",
0373 "",
0374 "SODIMM_156",
0375 "SODIMM_75",
0376 "SODIMM_154",
0377 "",
0378 "",
0379 "",
0380 "",
0381 "",
0382 "",
0383 "",
0384 "",
0385 "",
0386 "",
0387 "",
0388 "",
0389 "",
0390 "",
0391 "SODIMM_152";
0392 };
0393
0394 &gpio7 {
0395 gpio-line-names = "",
0396 "",
0397 "",
0398 "",
0399 "",
0400 "",
0401 "",
0402 "",
0403 "",
0404 "SODIMM_19",
0405 "SODIMM_21",
0406 "",
0407 "SODIMM_137";
0408 };
0409
0410 &hdmi {
0411 pinctrl-names = "default";
0412 pinctrl-0 = <&pinctrl_hdmi_ddc>;
0413 status = "disabled";
0414 };
0415
0416 /*
0417 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
0418 * touch screen controller
0419 */
0420 &i2c2 {
0421 clock-frequency = <100000>;
0422 pinctrl-names = "default", "gpio";
0423 pinctrl-0 = <&pinctrl_i2c2>;
0424 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0425 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0426 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0427 status = "okay";
0428
0429 pmic: pmic@8 {
0430 compatible = "fsl,pfuze100";
0431 fsl,pmic-stby-poweroff;
0432 reg = <0x08>;
0433
0434 regulators {
0435 sw1a_reg: sw1ab {
0436 regulator-always-on;
0437 regulator-boot-on;
0438 regulator-max-microvolt = <1875000>;
0439 regulator-min-microvolt = <300000>;
0440 regulator-ramp-delay = <6250>;
0441 };
0442
0443 sw1c_reg: sw1c {
0444 regulator-always-on;
0445 regulator-boot-on;
0446 regulator-max-microvolt = <1875000>;
0447 regulator-min-microvolt = <300000>;
0448 regulator-ramp-delay = <6250>;
0449 };
0450
0451 sw3a_reg: sw3a {
0452 regulator-always-on;
0453 regulator-boot-on;
0454 regulator-max-microvolt = <1975000>;
0455 regulator-min-microvolt = <400000>;
0456 };
0457
0458 swbst_reg: swbst {
0459 regulator-always-on;
0460 regulator-boot-on;
0461 regulator-max-microvolt = <5150000>;
0462 regulator-min-microvolt = <5000000>;
0463 };
0464
0465 snvs_reg: vsnvs {
0466 regulator-always-on;
0467 regulator-boot-on;
0468 regulator-max-microvolt = <3000000>;
0469 regulator-min-microvolt = <1000000>;
0470 };
0471
0472 vref_reg: vrefddr {
0473 regulator-always-on;
0474 regulator-boot-on;
0475 };
0476
0477 /* vgen1: unused */
0478
0479 vgen2_reg: vgen2 {
0480 regulator-always-on;
0481 regulator-boot-on;
0482 regulator-max-microvolt = <1550000>;
0483 regulator-min-microvolt = <800000>;
0484 };
0485
0486 /*
0487 * +V3.3_1.8_SD1 coming off VGEN3 and supplying
0488 * the i.MX 6 NVCC_SD1.
0489 */
0490 vgen3_reg: vgen3 {
0491 regulator-always-on;
0492 regulator-boot-on;
0493 regulator-max-microvolt = <3300000>;
0494 regulator-min-microvolt = <1800000>;
0495 };
0496
0497 vgen4_reg: vgen4 {
0498 regulator-always-on;
0499 regulator-boot-on;
0500 regulator-max-microvolt = <1800000>;
0501 regulator-min-microvolt = <1800000>;
0502 };
0503
0504 vgen5_reg: vgen5 {
0505 regulator-always-on;
0506 regulator-boot-on;
0507 regulator-max-microvolt = <3300000>;
0508 regulator-min-microvolt = <1800000>;
0509 };
0510
0511 vgen6_reg: vgen6 {
0512 regulator-always-on;
0513 regulator-boot-on;
0514 regulator-max-microvolt = <3300000>;
0515 regulator-min-microvolt = <1800000>;
0516 };
0517 };
0518 };
0519
0520 codec: sgtl5000@a {
0521 compatible = "fsl,sgtl5000";
0522 clocks = <&clks IMX6QDL_CLK_CKO>;
0523 lrclk-strength = <3>;
0524 pinctrl-names = "default";
0525 pinctrl-0 = <&pinctrl_sgtl5000>;
0526 reg = <0x0a>;
0527 #sound-dai-cells = <0>;
0528 VDDA-supply = <®_module_3v3_audio>;
0529 VDDIO-supply = <®_module_3v3>;
0530 VDDD-supply = <&vgen4_reg>;
0531 };
0532
0533 /* STMPE811 touch screen controller */
0534 stmpe811@41 {
0535 compatible = "st,stmpe811";
0536 blocks = <0x5>;
0537 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
0538 interrupt-parent = <&gpio6>;
0539 interrupt-controller;
0540 id = <0>;
0541 irq-trigger = <0x1>;
0542 pinctrl-names = "default";
0543 pinctrl-0 = <&pinctrl_touch_int>;
0544 reg = <0x41>;
0545 /* 3.25 MHz ADC clock speed */
0546 st,adc-freq = <1>;
0547 /* 12-bit ADC */
0548 st,mod-12b = <1>;
0549 /* internal ADC reference */
0550 st,ref-sel = <0>;
0551 /* ADC converstion time: 80 clocks */
0552 st,sample-time = <4>;
0553
0554 stmpe_ts: stmpe_touchscreen {
0555 compatible = "st,stmpe-ts";
0556 /* 8 sample average control */
0557 st,ave-ctrl = <3>;
0558 /* 7 length fractional part in z */
0559 st,fraction-z = <7>;
0560 /*
0561 * 50 mA typical 80 mA max touchscreen drivers
0562 * current limit value
0563 */
0564 st,i-drive = <1>;
0565 /* 1 ms panel driver settling time */
0566 st,settling = <3>;
0567 /* 5 ms touch detect interrupt delay */
0568 st,touch-det-delay = <5>;
0569 status = "disabled";
0570 };
0571
0572 stmpe_adc: stmpe_adc {
0573 compatible = "st,stmpe-adc";
0574 /* forbid to use ADC channels 3-0 (touch) */
0575 st,norequest-mask = <0x0F>;
0576 };
0577 };
0578 };
0579
0580 /*
0581 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
0582 */
0583 &i2c3 {
0584 clock-frequency = <100000>;
0585 pinctrl-names = "default", "gpio";
0586 pinctrl-0 = <&pinctrl_i2c3>;
0587 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0588 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0589 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0590 status = "disabled";
0591
0592 atmel_mxt_ts: touchscreen@4a {
0593 compatible = "atmel,maxtouch";
0594 interrupt-parent = <&gpio2>;
0595 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
0596 pinctrl-names = "default";
0597 pinctrl-0 = <&pinctrl_atmel_conn>;
0598 reg = <0x4a>;
0599 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */
0600 status = "disabled";
0601 };
0602 };
0603
0604 &ipu1_di0_disp0 {
0605 remote-endpoint = <&lcd_display_in>;
0606 };
0607
0608 /* Colibri PWM<B> */
0609 &pwm1 {
0610 pinctrl-names = "default";
0611 pinctrl-0 = <&pinctrl_pwm1>;
0612 status = "disabled";
0613 };
0614
0615 /* Colibri PWM<D> */
0616 &pwm2 {
0617 pinctrl-names = "default";
0618 pinctrl-0 = <&pinctrl_pwm2>;
0619 status = "disabled";
0620 };
0621
0622 /* Colibri PWM<A> */
0623 &pwm3 {
0624 pinctrl-names = "default";
0625 pinctrl-0 = <&pinctrl_pwm3>;
0626 status = "disabled";
0627 };
0628
0629 /* Colibri PWM<C> */
0630 &pwm4 {
0631 pinctrl-names = "default";
0632 pinctrl-0 = <&pinctrl_pwm4>;
0633 status = "disabled";
0634 };
0635
0636 /* Optional S/PDIF out on SODIMM 137 */
0637 &spdif {
0638 pinctrl-names = "default";
0639 pinctrl-0 = <&pinctrl_spdif>;
0640 status = "disabled";
0641 };
0642
0643 &ssi1 {
0644 status = "okay";
0645 };
0646
0647 /* Colibri UART_A */
0648 &uart1 {
0649 fsl,dte-mode;
0650 pinctrl-names = "default";
0651 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
0652 uart-has-rtscts;
0653 status = "disabled";
0654 };
0655
0656 /* Colibri UART_B */
0657 &uart2 {
0658 fsl,dte-mode;
0659 pinctrl-names = "default";
0660 pinctrl-0 = <&pinctrl_uart2_dte>;
0661 uart-has-rtscts;
0662 status = "disabled";
0663 };
0664
0665 /* Colibri UART_C */
0666 &uart3 {
0667 fsl,dte-mode;
0668 pinctrl-names = "default";
0669 pinctrl-0 = <&pinctrl_uart3_dte>;
0670 status = "disabled";
0671 };
0672
0673 &usbotg {
0674 disable-over-current;
0675 dr_mode = "peripheral";
0676 status = "disabled";
0677 };
0678
0679 /* Colibri MMC */
0680 &usdhc1 {
0681 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
0682 bus-width = <4>;
0683 no-1-8-v;
0684 disable-wp;
0685 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
0686 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
0687 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
0688 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
0689 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>;
0690 vmmc-supply = <®_module_3v3>;
0691 vqmmc-supply = <&vgen3_reg>;
0692 status = "disabled";
0693 };
0694
0695 /* eMMC */
0696 &usdhc3 {
0697 bus-width = <8>;
0698 no-1-8-v;
0699 non-removable;
0700 pinctrl-names = "default";
0701 pinctrl-0 = <&pinctrl_usdhc3>;
0702 vqmmc-supply = <®_module_3v3>;
0703 status = "okay";
0704 };
0705
0706 &weim {
0707 pinctrl-names = "default";
0708 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
0709 &pinctrl_weim_cs1 &pinctrl_weim_cs2
0710 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
0711 #address-cells = <2>;
0712 #size-cells = <1>;
0713 status = "disabled";
0714 };
0715
0716 &iomuxc {
0717 pinctrl-names = "default";
0718 pinctrl-0 = <&pinctrl_usbh_oc_1>;
0719
0720 /* Atmel MXT touchsceen + Capacitive Touch Adapter */
0721 /* NOTE: This pin group conflicts with pin groups
0722 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously.
0723 */
0724 pinctrl_atmel_adap: atmeladaptergrp {
0725 fsl,pins = <
0726 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */
0727 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */
0728 >;
0729 };
0730
0731 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
0732 /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and
0733 * pinctrl_weim_cs2. Don't use them simultaneously.
0734 */
0735 pinctrl_atmel_conn: atmelconnectorgrp {
0736 fsl,pins = <
0737 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */
0738 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */
0739 >;
0740 };
0741
0742 pinctrl_audmux: audmuxgrp {
0743 fsl,pins = <
0744 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
0745 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
0746 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
0747 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
0748 >;
0749 };
0750
0751 pinctrl_cam_mclk: cammclkgrp {
0752 fsl,pins = <
0753 /* Parallel Camera CAM sys_mclk */
0754 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
0755 >;
0756 };
0757
0758 /* CSI pins used as GPIOs */
0759 pinctrl_csi_gpio_1: csigpio1grp {
0760 fsl,pins = <
0761 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0
0762 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
0763 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
0764 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
0765 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
0766 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
0767 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
0768 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
0769 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0
0770 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
0771 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
0772 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
0773 >;
0774 };
0775
0776 pinctrl_csi_gpio_2: csigpio2grp {
0777 fsl,pins = <
0778 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0
0779 >;
0780 };
0781
0782 pinctrl_ecspi4: ecspi4grp {
0783 fsl,pins = <
0784 /* SPI CS */
0785 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
0786 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
0787 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
0788 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
0789 >;
0790 };
0791
0792 pinctrl_enet: enetgrp {
0793 fsl,pins = <
0794 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
0795 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0796 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0797 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
0798 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
0799 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
0800 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
0801 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
0802 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
0803 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
0804 >;
0805 };
0806
0807 pinctrl_flexcan1: flexcan1grp {
0808 fsl,pins = <
0809 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
0810 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
0811 >;
0812 };
0813
0814 pinctrl_flexcan2: flexcan2grp {
0815 fsl,pins = <
0816 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
0817 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
0818 >;
0819 };
0820
0821 pinctrl_gpio_1: gpio1grp {
0822 fsl,pins = <
0823 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
0824 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
0825 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
0826 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
0827 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
0828 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
0829 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
0830 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
0831 >;
0832 };
0833 pinctrl_gpio_2: gpio2grp {
0834 fsl,pins = <
0835 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
0836 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
0837 >;
0838 };
0839
0840 pinctrl_gpio_bl_on: gpioblongrp {
0841 fsl,pins = <
0842 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
0843 >;
0844 };
0845
0846 pinctrl_gpio_keys: gpiokeysgrp {
0847 fsl,pins = <
0848 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
0849 >;
0850 };
0851
0852 pinctrl_hdmi_ddc: hdmiddcgrp {
0853 fsl,pins = <
0854 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
0855 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
0856 >;
0857 };
0858
0859 pinctrl_i2c2: i2c2grp {
0860 fsl,pins = <
0861 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
0862 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
0863 >;
0864 };
0865
0866 pinctrl_i2c2_gpio: i2c2gpiogrp {
0867 fsl,pins = <
0868 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
0869 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
0870 >;
0871 };
0872
0873 pinctrl_i2c3: i2c3grp {
0874 fsl,pins = <
0875 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
0876 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0877 >;
0878 };
0879
0880 pinctrl_i2c3_gpio: i2c3gpiogrp {
0881 fsl,pins = <
0882 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
0883 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
0884 >;
0885 };
0886
0887 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
0888 fsl,pins = <
0889 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
0890 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
0891 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
0892 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
0893 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
0894 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
0895 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
0896 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
0897 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
0898 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
0899 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
0900 /* Disable PWM pins on camera interface */
0901 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
0902 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
0903 >;
0904 };
0905
0906 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
0907 fsl,pins = <
0908 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
0909 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
0910 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
0911 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
0912 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
0913 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
0914 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
0915 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
0916 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
0917 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
0918 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
0919 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
0920 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
0921 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
0922 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
0923 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
0924 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
0925 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
0926 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
0927 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
0928 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
0929 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
0930 >;
0931 };
0932
0933 pinctrl_lvds_transceiver: lvdstxgrp {
0934 fsl,pins = <
0935 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */
0936 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */
0937 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */
0938 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */
0939 >;
0940 };
0941
0942 pinctrl_mic_gnd: micgndgrp {
0943 fsl,pins = <
0944 /* Controls Mic GND, PU or '1' pull Mic GND to GND */
0945 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
0946 >;
0947 };
0948
0949 pinctrl_mmc_cd: mmccdgrp {
0950 fsl,pins = <
0951 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
0952 >;
0953 };
0954
0955 pinctrl_mmc_cd_sleep: mmccdslpgrp {
0956 fsl,pins = <
0957 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0
0958 >;
0959 };
0960
0961 pinctrl_pwm1: pwm1grp {
0962 fsl,pins = <
0963 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
0964 >;
0965 };
0966
0967 pinctrl_pwm2: pwm2grp {
0968 fsl,pins = <
0969 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
0970 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
0971 >;
0972 };
0973
0974 pinctrl_pwm3: pwm3grp {
0975 fsl,pins = <
0976 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
0977 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
0978 >;
0979 };
0980
0981 pinctrl_pwm4: pwm4grp {
0982 fsl,pins = <
0983 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
0984 >;
0985 };
0986
0987 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
0988 fsl,pins = <
0989 /* USBH_EN */
0990 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
0991 >;
0992 };
0993
0994 pinctrl_sgtl5000: sgtl5000grp {
0995 fsl,pins = <
0996 /* SGTL5000 sys_mclk */
0997 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
0998 >;
0999 };
1000
1001 pinctrl_spdif: spdifgrp {
1002 fsl,pins = <
1003 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1004 >;
1005 };
1006
1007 pinctrl_touch_int: gpiotouchintgrp {
1008 fsl,pins = <
1009 /* STMPE811 interrupt */
1010 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
1011 >;
1012 };
1013
1014 pinctrl_uart1_dce: uart1dcegrp {
1015 fsl,pins = <
1016 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1017 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1018 >;
1019 };
1020
1021 /* DTE mode */
1022 pinctrl_uart1_dte: uart1dtegrp {
1023 fsl,pins = <
1024 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
1025 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
1026 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
1027 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
1028 >;
1029 };
1030
1031 /* Additional DTR, DSR, DCD */
1032 pinctrl_uart1_ctrl: uart1ctrlgrp {
1033 fsl,pins = <
1034 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
1035 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
1036 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
1037 >;
1038 };
1039
1040 pinctrl_uart2_dte: uart2dtegrp {
1041 fsl,pins = <
1042 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
1043 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
1044 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
1045 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
1046 >;
1047 };
1048
1049 pinctrl_uart3_dte: uart3dtegrp {
1050 fsl,pins = <
1051 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
1052 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
1053 >;
1054 };
1055
1056 pinctrl_usbc_det: usbcdetgrp {
1057 fsl,pins = <
1058 /* USBC_DET */
1059 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
1060 /* USBC_DET_OVERWRITE */
1061 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
1062 /* USBC_DET_EN */
1063 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
1064 >;
1065 };
1066
1067 pinctrl_usbc_id_1: usbcid1grp {
1068 fsl,pins = <
1069 /* USBC_ID */
1070 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
1071 >;
1072 };
1073
1074 pinctrl_usbh_oc_1: usbhoc1grp {
1075 fsl,pins = <
1076 /* USBH_OC */
1077 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
1078 >;
1079 };
1080
1081 pinctrl_usdhc1: usdhc1grp {
1082 fsl,pins = <
1083 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
1084 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
1085 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
1086 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
1087 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
1088 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
1089 >;
1090 };
1091
1092 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1093 fsl,pins = <
1094 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
1095 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
1096 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
1097 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
1098 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
1099 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
1100 >;
1101 };
1102
1103 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1104 fsl,pins = <
1105 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
1106 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
1107 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
1108 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
1109 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
1110 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
1111 >;
1112 };
1113
1114 /* avoid backfeeding with removed card power */
1115 pinctrl_usdhc1_sleep: usdhc1sleepgrp {
1116 fsl,pins = <
1117 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000
1118 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000
1119 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000
1120 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000
1121 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000
1122 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000
1123 >;
1124 };
1125
1126 pinctrl_usdhc3: usdhc3grp {
1127 fsl,pins = <
1128 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1129 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1130 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1131 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1132 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1133 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1134 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1135 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1136 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1137 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1138 /* eMMC reset */
1139 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
1140 >;
1141 };
1142
1143 pinctrl_weim_cs0: weimcs0grp {
1144 fsl,pins = <
1145 /* nEXT_CS0 */
1146 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1147 >;
1148 };
1149
1150 pinctrl_weim_cs1: weimcs1grp {
1151 fsl,pins = <
1152 /* nEXT_CS1 */
1153 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
1154 >;
1155 };
1156
1157 pinctrl_weim_cs2: weimcs2grp {
1158 fsl,pins = <
1159 /* nEXT_CS2 */
1160 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
1161 >;
1162 };
1163
1164 /* ADDRESS[16:18] [25] used as GPIO */
1165 pinctrl_weim_gpio_1: weimgpio1grp {
1166 fsl,pins = <
1167 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
1168 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
1169 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
1170 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
1171 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
1172 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
1173 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
1174 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
1175 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
1176 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
1177 >;
1178 };
1179
1180 /* ADDRESS[19:24] used as GPIO */
1181 pinctrl_weim_gpio_2: weimgpio2grp {
1182 fsl,pins = <
1183 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
1184 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
1185 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
1186 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
1187 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
1188 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
1189 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
1190 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
1191 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
1192 >;
1193 };
1194
1195 /* DATA[16:31] used as GPIO */
1196 pinctrl_weim_gpio_3: weimgpio3grp {
1197 fsl,pins = <
1198 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
1199 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
1200 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
1201 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
1202 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
1203 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
1204 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
1205 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
1206 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
1207 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
1208 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
1209 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
1210 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
1211 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
1212 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
1213 >;
1214 };
1215
1216 /* DQM[0:3] used as GPIO */
1217 pinctrl_weim_gpio_4: weimgpio4grp {
1218 fsl,pins = <
1219 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
1220 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
1221 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
1222 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
1223 >;
1224 };
1225
1226 /* RDY used as GPIO */
1227 pinctrl_weim_gpio_5: weimgpio5grp {
1228 fsl,pins = <
1229 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
1230 >;
1231 };
1232
1233 /* ADDRESS[16] DATA[30] used as GPIO */
1234 pinctrl_weim_gpio_6: weimgpio6grp {
1235 fsl,pins = <
1236 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
1237 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
1238 >;
1239 };
1240
1241 pinctrl_weim_npwe: weimnpwegrp {
1242 fsl,pins = <
1243 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
1244 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
1245 >;
1246 };
1247
1248 pinctrl_weim_sram: weimsramgrp {
1249 fsl,pins = <
1250 /* Data */
1251 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
1252 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
1253 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
1254 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
1255 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
1256 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
1257 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
1258 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
1259 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
1260 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
1261 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
1262 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
1263 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
1264 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
1265 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
1266 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
1267 /* Address */
1268 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1269 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1270 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1271 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1272 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1273 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1274 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1275 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1276 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1277 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1278 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1279 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1280 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1281 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1282 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1283 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1284 /* Ctrl */
1285 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1286 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1287 >;
1288 };
1289
1290 pinctrl_weim_rdnwr: weimrdnwrgrp {
1291 fsl,pins = <
1292 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
1293 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
1294 >;
1295 };
1296 };
