0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Copyright 2015 Armadeus Systems <support@armadeus.com>
0004
0005 #include <dt-bindings/gpio/gpio.h>
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007
0008 / {
0009 reg_1p8v: regulator-1p8v {
0010 compatible = "regulator-fixed";
0011 regulator-name = "1P8V";
0012 regulator-min-microvolt = <1800000>;
0013 regulator-max-microvolt = <1800000>;
0014 regulator-always-on;
0015 vin-supply = <®_3p3v>;
0016 };
0017
0018 usdhc1_pwrseq: usdhc1-pwrseq {
0019 compatible = "mmc-pwrseq-simple";
0020 reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
0021 post-power-on-delay-ms = <15>;
0022 power-off-delay-us = <70>;
0023 };
0024 };
0025
0026 &fec {
0027 pinctrl-names = "default";
0028 pinctrl-0 = <&pinctrl_enet>;
0029 phy-mode = "rgmii-id";
0030 phy-reset-duration = <10>;
0031 phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
0032 phy-handle = <ðphy1>;
0033 status = "okay";
0034
0035 mdio {
0036 #address-cells = <1>;
0037 #size-cells = <0>;
0038
0039 ethphy1: ethernet-phy@1 {
0040 compatible = "ethernet-phy-ieee802.3-c22";
0041 reg = <1>;
0042 interrupt-parent = <&gpio1>;
0043 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
0044 status = "okay";
0045 };
0046 };
0047 };
0048
0049 /* Bluetooth */
0050 &uart2 {
0051 pinctrl-names = "default";
0052 pinctrl-0 = <&pinctrl_uart2>;
0053 uart-has-rtscts;
0054 status = "okay";
0055 };
0056
0057 /* Wi-Fi */
0058 &usdhc1 {
0059 pinctrl-names = "default";
0060 pinctrl-0 = <&pinctrl_usdhc1>;
0061 bus-width = <4>;
0062 mmc-pwrseq = <&usdhc1_pwrseq>;
0063 vmmc-supply = <®_3p3v>;
0064 vqmmc-supply = <®_1p8v>;
0065 cap-power-off-card;
0066 keep-power-in-suspend;
0067 non-removable;
0068 status = "okay";
0069
0070 #address-cells = <1>;
0071 #size-cells = <0>;
0072 wlcore: wlcore@2 {
0073 compatible = "ti,wl1271";
0074 reg = <2>;
0075 interrupt-parent = <&gpio2>;
0076 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
0077 ref-clock-frequency = <38400000>;
0078 tcxo-clock-frequency = <38400000>;
0079 };
0080 };
0081
0082 /* eMMC */
0083 &usdhc3 {
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_usdhc3>;
0086 bus-width = <8>;
0087 no-1-8-v;
0088 non-removable;
0089 status = "okay";
0090 };
0091
0092 &iomuxc {
0093 pinctrl_enet: enetgrp {
0094 fsl,pins = <
0095 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
0096 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0097 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0098 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
0099 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
0100 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0101 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0102 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0103 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0104 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0105 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0106 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
0107 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0108 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
0109 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
0110 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
0111 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
0112 >;
0113 };
0114
0115 pinctrl_uart2: uart2grp {
0116 fsl,pins = <
0117 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
0118 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
0119 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
0120 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
0121 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
0122 >;
0123 };
0124
0125 pinctrl_usdhc1: usdhc1grp {
0126 fsl,pins = <
0127 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
0128 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
0129 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
0130 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
0131 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
0132 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
0133 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */
0134 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */
0135 >;
0136 };
0137
0138 pinctrl_usdhc3: usdhc3grp {
0139 fsl,pins = <
0140 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0141 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0142 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0143 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0144 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0145 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0146 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
0147 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
0148 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
0149 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
0150 >;
0151 };
0152 };
