0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright 2014-2022 Toradex
0004 * Copyright 2012 Freescale Semiconductor, Inc.
0005 * Copyright 2011 Linaro Ltd.
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/pwm/pwm.h>
0010
0011 / {
0012 model = "Toradex Apalis iMX6Q/D Module";
0013 compatible = "toradex,apalis_imx6q", "fsl,imx6q";
0014
0015 /* Will be filled by the bootloader */
0016 memory@10000000 {
0017 device_type = "memory";
0018 reg = <0x10000000 0>;
0019 };
0020
0021 backlight: backlight {
0022 compatible = "pwm-backlight";
0023 brightness-levels = <0 45 63 88 119 158 203 255>;
0024 default-brightness-level = <4>;
0025 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pinctrl_gpio_bl_on>;
0028 power-supply = <®_module_3v3>;
0029 pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>;
0030 status = "disabled";
0031 };
0032
0033 clk_ov5640_osc: clk-ov5640-osc {
0034 compatible = "fixed-clock";
0035 #clock-cells = <0>;
0036 clock-frequency = <24000000>;
0037 };
0038
0039 gpio-keys {
0040 compatible = "gpio-keys";
0041 pinctrl-names = "default";
0042 pinctrl-0 = <&pinctrl_gpio_keys>;
0043
0044 wakeup {
0045 debounce-interval = <10>;
0046 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
0047 label = "Wake-Up";
0048 linux,code = <KEY_WAKEUP>;
0049 wakeup-source;
0050 };
0051 };
0052
0053 lcd_display: disp0 {
0054 compatible = "fsl,imx-parallel-display";
0055 #address-cells = <1>;
0056 #size-cells = <0>;
0057 interface-pix-fmt = "rgb24";
0058 pinctrl-names = "default";
0059 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
0060 status = "disabled";
0061
0062 port@0 {
0063 reg = <0>;
0064
0065 lcd_display_in: endpoint {
0066 remote-endpoint = <&ipu1_di1_disp1>;
0067 };
0068 };
0069
0070 port@1 {
0071 reg = <1>;
0072
0073 lcd_display_out: endpoint {
0074 remote-endpoint = <&lcd_panel_in>;
0075 };
0076 };
0077 };
0078
0079 panel_dpi: panel-dpi {
0080 compatible = "edt,et057090dhu";
0081 backlight = <&backlight>;
0082
0083 status = "disabled";
0084
0085 port {
0086 lcd_panel_in: endpoint {
0087 remote-endpoint = <&lcd_display_out>;
0088 };
0089 };
0090 };
0091
0092 panel_lvds: panel-lvds {
0093 compatible = "panel-lvds";
0094 backlight = <&backlight>;
0095 status = "disabled";
0096
0097 port {
0098 lvds_panel_in: endpoint {
0099 remote-endpoint = <&lvds0_out>;
0100 };
0101 };
0102 };
0103
0104 reg_module_3v3: regulator-module-3v3 {
0105 compatible = "regulator-fixed";
0106 regulator-always-on;
0107 regulator-max-microvolt = <3300000>;
0108 regulator-min-microvolt = <3300000>;
0109 regulator-name = "+V3.3";
0110 };
0111
0112 reg_module_3v3_audio: regulator-module-3v3-audio {
0113 compatible = "regulator-fixed";
0114 regulator-always-on;
0115 regulator-max-microvolt = <3300000>;
0116 regulator-min-microvolt = <3300000>;
0117 regulator-name = "+V3.3_AUDIO";
0118 };
0119
0120 reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd {
0121 compatible = "regulator-fixed";
0122 regulator-always-on;
0123 regulator-max-microvolt = <1800000>;
0124 regulator-min-microvolt = <1800000>;
0125 regulator-name = "DOVDD/DVDD_1.8V";
0126 /* Note: The CSI module uses on-board 3.3V_SW supply */
0127 vin-supply = <®_module_3v3>;
0128 };
0129
0130 reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd {
0131 compatible = "regulator-fixed";
0132 regulator-always-on;
0133 regulator-max-microvolt = <2800000>;
0134 regulator-min-microvolt = <2800000>;
0135 regulator-name = "AVDD/AFVDD_2.8V";
0136 /* Note: The CSI module uses on-board 3.3V_SW supply */
0137 vin-supply = <®_module_3v3>;
0138 };
0139
0140 reg_usb_otg_vbus: regulator-usb-otg-vbus {
0141 compatible = "regulator-fixed";
0142 enable-active-high;
0143 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
0146 regulator-max-microvolt = <5000000>;
0147 regulator-min-microvolt = <5000000>;
0148 regulator-name = "usb_otg_vbus";
0149 status = "disabled";
0150 };
0151
0152 /* on module USB hub */
0153 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
0154 compatible = "regulator-fixed";
0155 enable-active-high;
0156 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
0157 pinctrl-names = "default";
0158 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
0159 regulator-max-microvolt = <5000000>;
0160 regulator-min-microvolt = <5000000>;
0161 regulator-name = "usb_host_vbus_hub";
0162 startup-delay-us = <2000>;
0163 status = "okay";
0164 };
0165
0166 reg_usb_host_vbus: regulator-usb-host-vbus {
0167 compatible = "regulator-fixed";
0168 enable-active-high;
0169 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
0170 pinctrl-names = "default";
0171 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
0172 regulator-max-microvolt = <5000000>;
0173 regulator-min-microvolt = <5000000>;
0174 regulator-name = "usb_host_vbus";
0175 vin-supply = <®_usb_host_vbus_hub>;
0176 status = "disabled";
0177 };
0178
0179 sound {
0180 compatible = "fsl,imx-audio-sgtl5000";
0181 audio-codec = <&codec>;
0182 audio-routing =
0183 "LINE_IN", "Line In Jack",
0184 "MIC_IN", "Mic Jack",
0185 "Mic Jack", "Mic Bias",
0186 "Headphone Jack", "HP_OUT";
0187 model = "imx6q-apalis-sgtl5000";
0188 mux-ext-port = <4>;
0189 mux-int-port = <1>;
0190 ssi-controller = <&ssi1>;
0191 };
0192
0193 sound_spdif: sound-spdif {
0194 compatible = "fsl,imx-audio-spdif";
0195 spdif-controller = <&spdif>;
0196 spdif-in;
0197 spdif-out;
0198 model = "imx-spdif";
0199 status = "disabled";
0200 };
0201 };
0202
0203 &audmux {
0204 pinctrl-names = "default";
0205 pinctrl-0 = <&pinctrl_audmux>;
0206 status = "okay";
0207 };
0208
0209 &can1 {
0210 pinctrl-names = "default", "sleep";
0211 pinctrl-0 = <&pinctrl_flexcan1_default>;
0212 pinctrl-1 = <&pinctrl_flexcan1_sleep>;
0213 status = "disabled";
0214 };
0215
0216 &can2 {
0217 pinctrl-names = "default", "sleep";
0218 pinctrl-0 = <&pinctrl_flexcan2_default>;
0219 pinctrl-1 = <&pinctrl_flexcan2_sleep>;
0220 status = "disabled";
0221 };
0222
0223 &clks {
0224 fsl,pmic-stby-poweroff;
0225 };
0226
0227 /* Apalis SPI1 */
0228 &ecspi1 {
0229 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
0230 pinctrl-names = "default";
0231 pinctrl-0 = <&pinctrl_ecspi1>;
0232 status = "disabled";
0233 };
0234
0235 /* Apalis SPI2 */
0236 &ecspi2 {
0237 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
0238 pinctrl-names = "default";
0239 pinctrl-0 = <&pinctrl_ecspi2>;
0240 status = "disabled";
0241 };
0242
0243 &gpio1 {
0244 gpio-line-names = "MXM3_84",
0245 "MXM3_4",
0246 "MXM3_15/GPIO7",
0247 "MXM3_96",
0248 "MXM3_37",
0249 "",
0250 "MXM3_17/GPIO8",
0251 "MXM3_14",
0252 "MXM3_12",
0253 "MXM3_2",
0254 "MXM3_184",
0255 "MXM3_180",
0256 "MXM3_178",
0257 "MXM3_176",
0258 "MXM3_188",
0259 "MXM3_186",
0260 "MXM3_160",
0261 "MXM3_162",
0262 "MXM3_150",
0263 "MXM3_144",
0264 "MXM3_154",
0265 "MXM3_146",
0266 "",
0267 "",
0268 "MXM3_72";
0269 };
0270
0271 &gpio2 {
0272 gpio-line-names = "MXM3_148",
0273 "MXM3_152",
0274 "MXM3_156",
0275 "MXM3_158",
0276 "MXM3_1/GPIO1",
0277 "MXM3_3/GPIO2",
0278 "MXM3_5/GPIO3",
0279 "MXM3_7/GPIO4",
0280 "MXM3_95",
0281 "MXM3_6",
0282 "MXM3_8",
0283 "MXM3_123",
0284 "MXM3_126",
0285 "MXM3_128",
0286 "MXM3_130",
0287 "MXM3_132",
0288 "MXM3_253",
0289 "MXM3_251",
0290 "MXM3_283",
0291 "MXM3_281",
0292 "MXM3_279",
0293 "MXM3_277",
0294 "MXM3_243",
0295 "MXM3_235",
0296 "MXM3_231",
0297 "MXM3_229",
0298 "MXM3_233",
0299 "MXM3_198",
0300 "MXM3_275",
0301 "MXM3_273",
0302 "MXM3_207",
0303 "MXM3_122";
0304 };
0305
0306 &gpio3 {
0307 gpio-line-names = "MXM3_271",
0308 "MXM3_269",
0309 "MXM3_301",
0310 "MXM3_299",
0311 "MXM3_297",
0312 "MXM3_295",
0313 "MXM3_293",
0314 "MXM3_291",
0315 "MXM3_289",
0316 "MXM3_287",
0317 "MXM3_249",
0318 "MXM3_247",
0319 "MXM3_245",
0320 "MXM3_286",
0321 "MXM3_239",
0322 "MXM3_35",
0323 "MXM3_205",
0324 "MXM3_203",
0325 "MXM3_201",
0326 "MXM3_116",
0327 "MXM3_114",
0328 "MXM3_262",
0329 "MXM3_274",
0330 "MXM3_124",
0331 "MXM3_110",
0332 "MXM3_120",
0333 "MXM3_263",
0334 "MXM3_265",
0335 "",
0336 "MXM3_135",
0337 "MXM3_261",
0338 "MXM3_259";
0339 };
0340
0341 &gpio4 {
0342 gpio-line-names = "",
0343 "",
0344 "",
0345 "",
0346 "",
0347 "MXM3_194",
0348 "MXM3_136",
0349 "MXM3_134",
0350 "MXM3_140",
0351 "MXM3_138",
0352 "",
0353 "MXM3_220",
0354 "",
0355 "",
0356 "MXM3_18",
0357 "MXM3_16",
0358 "",
0359 "",
0360 "MXM3_214",
0361 "MXM3_216",
0362 "MXM3_164";
0363 };
0364
0365 &gpio5 {
0366 gpio-line-names = "MXM3_159",
0367 "",
0368 "",
0369 "",
0370 "MXM3_257",
0371 "",
0372 "",
0373 "",
0374 "",
0375 "",
0376 "MXM3_200",
0377 "MXM3_196",
0378 "MXM3_204",
0379 "MXM3_202",
0380 "",
0381 "",
0382 "",
0383 "",
0384 "MXM3_191",
0385 "MXM3_197",
0386 "MXM3_77",
0387 "MXM3_195",
0388 "MXM3_221",
0389 "MXM3_225",
0390 "MXM3_223",
0391 "MXM3_227",
0392 "MXM3_209",
0393 "MXM3_211",
0394 "MXM3_118",
0395 "MXM3_112",
0396 "MXM3_187",
0397 "MXM3_185";
0398 };
0399
0400 &gpio6 {
0401 gpio-line-names = "MXM3_183",
0402 "MXM3_181",
0403 "MXM3_179",
0404 "MXM3_177",
0405 "MXM3_175",
0406 "MXM3_173",
0407 "MXM3_255",
0408 "MXM3_83",
0409 "MXM3_91",
0410 "MXM3_13/GPIO6",
0411 "MXM3_11/GPIO5",
0412 "MXM3_79",
0413 "",
0414 "",
0415 "MXM3_190",
0416 "MXM3_193",
0417 "MXM3_89";
0418 };
0419
0420 &gpio7 {
0421 gpio-line-names = "",
0422 "",
0423 "",
0424 "",
0425 "",
0426 "",
0427 "",
0428 "",
0429 "",
0430 "MXM3_99",
0431 "MXM3_85",
0432 "MXM3_217",
0433 "MXM3_215";
0434 };
0435
0436 &gpr {
0437 ipu1_csi0_mux {
0438 #address-cells = <1>;
0439 #size-cells = <0>;
0440 status = "disabled";
0441
0442 port@1 {
0443 reg = <1>;
0444 ipu1_csi0_mux_from_parallel_sensor: endpoint {
0445 remote-endpoint = <&adv7280_to_ipu1_csi0_mux>;
0446 };
0447 };
0448 };
0449 };
0450
0451 &fec {
0452 pinctrl-names = "default";
0453 pinctrl-0 = <&pinctrl_enet>;
0454 phy-mode = "rgmii-id";
0455 phy-handle = <ðphy>;
0456 phy-reset-duration = <10>;
0457 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
0458 status = "okay";
0459
0460 mdio {
0461 #address-cells = <1>;
0462 #size-cells = <0>;
0463
0464 ethphy: ethernet-phy@7 {
0465 interrupt-parent = <&gpio1>;
0466 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
0467 reg = <7>;
0468 };
0469 };
0470 };
0471
0472 &hdmi {
0473 pinctrl-names = "default";
0474 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>;
0475 status = "disabled";
0476 };
0477
0478 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
0479 &i2c1 {
0480 clock-frequency = <100000>;
0481 pinctrl-names = "default", "gpio";
0482 pinctrl-0 = <&pinctrl_i2c1>;
0483 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0484 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0485 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0486 status = "disabled";
0487
0488 atmel_mxt_ts: touchscreen@4a {
0489 compatible = "atmel,maxtouch";
0490 /* These GPIOs are muxed with the iomuxc node */
0491 interrupt-parent = <&gpio6>;
0492 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */
0493 reg = <0x4a>;
0494 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */
0495 status = "disabled";
0496 };
0497 };
0498
0499 /*
0500 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
0501 * touch screen controller
0502 */
0503 &i2c2 {
0504 clock-frequency = <100000>;
0505 pinctrl-names = "default", "gpio";
0506 pinctrl-0 = <&pinctrl_i2c2>;
0507 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0508 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0509 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0510 status = "okay";
0511
0512 pmic: pmic@8 {
0513 compatible = "fsl,pfuze100";
0514 fsl,pmic-stby-poweroff;
0515 reg = <0x08>;
0516
0517 regulators {
0518 sw1a_reg: sw1ab {
0519 regulator-always-on;
0520 regulator-boot-on;
0521 regulator-max-microvolt = <1875000>;
0522 regulator-min-microvolt = <300000>;
0523 regulator-ramp-delay = <6250>;
0524 };
0525
0526 sw1c_reg: sw1c {
0527 regulator-always-on;
0528 regulator-boot-on;
0529 regulator-max-microvolt = <1875000>;
0530 regulator-min-microvolt = <300000>;
0531 regulator-ramp-delay = <6250>;
0532 };
0533
0534 sw3a_reg: sw3a {
0535 regulator-always-on;
0536 regulator-boot-on;
0537 regulator-max-microvolt = <1975000>;
0538 regulator-min-microvolt = <400000>;
0539 };
0540
0541 swbst_reg: swbst {
0542 regulator-always-on;
0543 regulator-boot-on;
0544 regulator-max-microvolt = <5150000>;
0545 regulator-min-microvolt = <5000000>;
0546 };
0547
0548 snvs_reg: vsnvs {
0549 regulator-always-on;
0550 regulator-boot-on;
0551 regulator-max-microvolt = <3000000>;
0552 regulator-min-microvolt = <1000000>;
0553 };
0554
0555 vref_reg: vrefddr {
0556 regulator-always-on;
0557 regulator-boot-on;
0558 };
0559
0560 vgen1_reg: vgen1 {
0561 regulator-always-on;
0562 regulator-boot-on;
0563 regulator-max-microvolt = <1550000>;
0564 regulator-min-microvolt = <800000>;
0565 };
0566
0567 vgen2_reg: vgen2 {
0568 regulator-always-on;
0569 regulator-boot-on;
0570 regulator-max-microvolt = <1550000>;
0571 regulator-min-microvolt = <800000>;
0572 };
0573
0574 vgen3_reg: vgen3 {
0575 regulator-always-on;
0576 regulator-boot-on;
0577 regulator-max-microvolt = <3300000>;
0578 regulator-min-microvolt = <1800000>;
0579 };
0580
0581 vgen4_reg: vgen4 {
0582 regulator-always-on;
0583 regulator-boot-on;
0584 regulator-max-microvolt = <1800000>;
0585 regulator-min-microvolt = <1800000>;
0586 };
0587
0588 vgen5_reg: vgen5 {
0589 regulator-always-on;
0590 regulator-boot-on;
0591 regulator-max-microvolt = <3300000>;
0592 regulator-min-microvolt = <1800000>;
0593 };
0594
0595 vgen6_reg: vgen6 {
0596 regulator-always-on;
0597 regulator-boot-on;
0598 regulator-max-microvolt = <3300000>;
0599 regulator-min-microvolt = <1800000>;
0600 };
0601 };
0602 };
0603
0604 codec: sgtl5000@a {
0605 compatible = "fsl,sgtl5000";
0606 #sound-dai-cells = <0>;
0607 clocks = <&clks IMX6QDL_CLK_CKO>;
0608 pinctrl-names = "default";
0609 pinctrl-0 = <&pinctrl_sgtl5000>;
0610 reg = <0x0a>;
0611 VDDA-supply = <®_module_3v3_audio>;
0612 VDDIO-supply = <®_module_3v3>;
0613 VDDD-supply = <&vgen4_reg>;
0614 };
0615
0616 /* STMPE811 touch screen controller */
0617 stmpe811@41 {
0618 compatible = "st,stmpe811";
0619 blocks = <0x5>;
0620 id = <0>;
0621 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
0622 interrupt-controller;
0623 interrupt-parent = <&gpio4>;
0624 irq-trigger = <0x1>;
0625 pinctrl-names = "default";
0626 pinctrl-0 = <&pinctrl_touch_int>;
0627 reg = <0x41>;
0628 /* 3.25 MHz ADC clock speed */
0629 st,adc-freq = <1>;
0630 /* 12-bit ADC */
0631 st,mod-12b = <1>;
0632 /* internal ADC reference */
0633 st,ref-sel = <0>;
0634 /* ADC conversion time: 80 clocks */
0635 st,sample-time = <4>;
0636
0637 stmpe_ts: stmpe_touchscreen {
0638 compatible = "st,stmpe-ts";
0639 /* 8 sample average control */
0640 st,ave-ctrl = <3>;
0641 /* 7 length fractional part in z */
0642 st,fraction-z = <7>;
0643 /*
0644 * 50 mA typical 80 mA max touchscreen drivers
0645 * current limit value
0646 */
0647 st,i-drive = <1>;
0648 /* 1 ms panel driver settling time */
0649 st,settling = <3>;
0650 /* 5 ms touch detect interrupt delay */
0651 st,touch-det-delay = <5>;
0652 status = "disabled";
0653 };
0654
0655 stmpe_adc: stmpe_adc {
0656 compatible = "st,stmpe-adc";
0657 #io-channel-cells = <1>;
0658 /* forbid to use ADC channels 3-0 (touch) */
0659 st,norequest-mask = <0x0F>;
0660 };
0661 };
0662 };
0663
0664 /*
0665 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
0666 * board)
0667 */
0668 &i2c3 {
0669 clock-frequency = <100000>;
0670 pinctrl-names = "default", "gpio";
0671 pinctrl-0 = <&pinctrl_i2c3>;
0672 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0673 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0674 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0675 status = "disabled";
0676
0677 adv_7280: adv7280@21 {
0678 compatible = "adi,adv7280";
0679 adv,force-bt656-4;
0680 pinctrl-names = "default";
0681 pinctrl-0 = <&pinctrl_ipu1_csi0>;
0682 reg = <0x21>;
0683 status = "disabled";
0684
0685 port {
0686 adv7280_to_ipu1_csi0_mux: endpoint {
0687 bus-width = <8>;
0688 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
0689 };
0690 };
0691 };
0692
0693 ov5640_csi_cam: ov5640_mipi@3c {
0694 compatible = "ovti,ov5640";
0695 AVDD-supply = <®_ov5640_2v8_a_vdd>;
0696 DOVDD-supply = <®_ov5640_1v8_d_o_vdd>;
0697 DVDD-supply = <®_ov5640_1v8_d_o_vdd>;
0698 clock-names = "xclk";
0699 clocks = <&clks IMX6QDL_CLK_CKO2>;
0700 pinctrl-names = "default";
0701 pinctrl-0 = <&pinctrl_cam_mclk>;
0702 /* These GPIOs are muxed with the iomuxc node */
0703 powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
0704 reg = <0x3c>;
0705 reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
0706 status = "disabled";
0707
0708 port {
0709 ov5640_to_mipi_csi2: endpoint {
0710 clock-lanes = <0>;
0711 data-lanes = <1 2>;
0712 remote-endpoint = <&mipi_csi_from_ov5640>;
0713 };
0714 };
0715 };
0716 };
0717
0718 &ipu1_di1_disp1 {
0719 remote-endpoint = <&lcd_display_in>;
0720 };
0721
0722 &ldb {
0723 lvds-channel@0 {
0724 port@4 {
0725 reg = <4>;
0726
0727 lvds0_out: endpoint {
0728 remote-endpoint = <&lvds_panel_in>;
0729 };
0730 };
0731 };
0732
0733 lvds-channel@1 {
0734 fsl,data-mapping = "spwg";
0735 fsl,data-width = <18>;
0736
0737 port@4 {
0738 reg = <4>;
0739
0740 lvds1_out: endpoint {
0741 };
0742 };
0743 };
0744 };
0745
0746 &mipi_csi {
0747 #address-cells = <1>;
0748 #size-cells = <0>;
0749 status = "disabled";
0750
0751 port@0 {
0752 reg = <0>;
0753
0754 mipi_csi_from_ov5640: endpoint {
0755 clock-lanes = <0>;
0756 data-lanes = <1 2>;
0757 remote-endpoint = <&ov5640_to_mipi_csi2>;
0758 };
0759 };
0760 };
0761
0762 &pwm1 {
0763 pinctrl-names = "default";
0764 pinctrl-0 = <&pinctrl_pwm1>;
0765 status = "disabled";
0766 };
0767
0768 &pwm2 {
0769 pinctrl-names = "default";
0770 pinctrl-0 = <&pinctrl_pwm2>;
0771 status = "disabled";
0772 };
0773
0774 &pwm3 {
0775 pinctrl-names = "default";
0776 pinctrl-0 = <&pinctrl_pwm3>;
0777 status = "disabled";
0778 };
0779
0780 &pwm4 {
0781 pinctrl-names = "default";
0782 pinctrl-0 = <&pinctrl_pwm4>;
0783 status = "disabled";
0784 };
0785
0786 &spdif {
0787 pinctrl-names = "default";
0788 pinctrl-0 = <&pinctrl_spdif>;
0789 status = "disabled";
0790 };
0791
0792 &ssi1 {
0793 status = "okay";
0794 };
0795
0796 &uart1 {
0797 fsl,dte-mode;
0798 pinctrl-names = "default";
0799 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
0800 uart-has-rtscts;
0801 status = "disabled";
0802 };
0803
0804 &uart2 {
0805 fsl,dte-mode;
0806 pinctrl-names = "default";
0807 pinctrl-0 = <&pinctrl_uart2_dte>;
0808 uart-has-rtscts;
0809 status = "disabled";
0810 };
0811
0812 &uart4 {
0813 fsl,dte-mode;
0814 pinctrl-names = "default";
0815 pinctrl-0 = <&pinctrl_uart4_dte>;
0816 status = "disabled";
0817 };
0818
0819 &uart5 {
0820 fsl,dte-mode;
0821 pinctrl-names = "default";
0822 pinctrl-0 = <&pinctrl_uart5_dte>;
0823 status = "disabled";
0824 };
0825
0826 &usbotg {
0827 disable-over-current;
0828 pinctrl-names = "default";
0829 pinctrl-0 = <&pinctrl_usbotg>;
0830 status = "disabled";
0831 };
0832
0833 /* MMC1 */
0834 &usdhc1 {
0835 bus-width = <8>;
0836 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
0837 disable-wp;
0838 no-1-8-v;
0839 pinctrl-names = "default";
0840 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
0841 vqmmc-supply = <®_module_3v3>;
0842 status = "disabled";
0843 };
0844
0845 /* SD1 */
0846 &usdhc2 {
0847 bus-width = <4>;
0848 disable-wp;
0849 no-1-8-v;
0850 pinctrl-names = "default";
0851 pinctrl-0 = <&pinctrl_usdhc2>;
0852 vqmmc-supply = <®_module_3v3>;
0853 status = "disabled";
0854 };
0855
0856 /* eMMC */
0857 &usdhc3 {
0858 bus-width = <8>;
0859 no-1-8-v;
0860 non-removable;
0861 pinctrl-names = "default";
0862 pinctrl-0 = <&pinctrl_usdhc3>;
0863 vqmmc-supply = <®_module_3v3>;
0864 status = "okay";
0865 };
0866
0867 &weim {
0868 status = "disabled";
0869 };
0870
0871 &iomuxc {
0872 /* Mux the Apalis GPIOs */
0873 pinctrl-names = "default";
0874 pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
0875 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
0876 &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
0877 &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
0878 >;
0879
0880 pinctrl_apalis_gpio1: apalisgpio1grp {
0881 fsl,pins = <
0882 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
0883 >;
0884 };
0885
0886 pinctrl_apalis_gpio2: apalisgpio2grp {
0887 fsl,pins = <
0888 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
0889 >;
0890 };
0891
0892 pinctrl_apalis_gpio3: apalisgpio3grp {
0893 fsl,pins = <
0894 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
0895 >;
0896 };
0897
0898 pinctrl_apalis_gpio4: apalisgpio4grp {
0899 fsl,pins = <
0900 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
0901 >;
0902 };
0903
0904 pinctrl_apalis_gpio5: apalisgpio5grp {
0905 fsl,pins = <
0906 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
0907 >;
0908 };
0909
0910 pinctrl_apalis_gpio6: apalisgpio6grp {
0911 fsl,pins = <
0912 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
0913 >;
0914 };
0915
0916 pinctrl_apalis_gpio7: apalisgpio7grp {
0917 fsl,pins = <
0918 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
0919 >;
0920 };
0921
0922 pinctrl_apalis_gpio8: apalisgpio8grp {
0923 fsl,pins = <
0924 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
0925 >;
0926 };
0927
0928 pinctrl_audmux: audmuxgrp {
0929 fsl,pins = <
0930 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
0931 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
0932 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
0933 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
0934 >;
0935 };
0936
0937 pinctrl_cam_mclk: cammclkgrp {
0938 fsl,pins = <
0939 /* CAM sys_mclk */
0940 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
0941 >;
0942 };
0943
0944 pinctrl_ecspi1: ecspi1grp {
0945 fsl,pins = <
0946 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
0947 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
0948 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
0949 /* SPI1 cs */
0950 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
0951 >;
0952 };
0953
0954 pinctrl_ecspi2: ecspi2grp {
0955 fsl,pins = <
0956 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
0957 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
0958 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
0959 /* SPI2 cs */
0960 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
0961 >;
0962 };
0963
0964 pinctrl_enet: enetgrp {
0965 fsl,pins = <
0966 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
0967 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
0968 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
0969 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
0970 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
0971 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
0972 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
0973 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
0974 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
0975 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0976 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0977 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0978 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0979 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0980 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0981 /* Ethernet PHY reset */
0982 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
0983 /* Ethernet PHY interrupt */
0984 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
0985 >;
0986 };
0987
0988 pinctrl_flexcan1_default: flexcan1defgrp {
0989 fsl,pins = <
0990 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
0991 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
0992 >;
0993 };
0994
0995 pinctrl_flexcan1_sleep: flexcan1slpgrp {
0996 fsl,pins = <
0997 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
0998 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
0999 >;
1000 };
1001
1002 pinctrl_flexcan2_default: flexcan2defgrp {
1003 fsl,pins = <
1004 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
1005 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
1006 >;
1007 };
1008 pinctrl_flexcan2_sleep: flexcan2slpgrp {
1009 fsl,pins = <
1010 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
1011 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
1012 >;
1013 };
1014
1015 pinctrl_gpio_bl_on: gpioblongrp {
1016 fsl,pins = <
1017 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
1018 >;
1019 };
1020
1021 pinctrl_gpio_keys: gpio1io04grp {
1022 fsl,pins = <
1023 /* Power button */
1024 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
1025 >;
1026 };
1027
1028 pinctrl_hdmi_cec: hdmicecgrp {
1029 fsl,pins = <
1030 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
1031 >;
1032 };
1033
1034 pinctrl_hdmi_ddc: hdmiddcgrp {
1035 fsl,pins = <
1036 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
1037 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
1038 >;
1039 };
1040
1041 pinctrl_i2c1: i2c1grp {
1042 fsl,pins = <
1043 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
1044 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
1045 >;
1046 };
1047
1048 pinctrl_i2c1_gpio: i2c1gpiogrp {
1049 fsl,pins = <
1050 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
1051 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
1052 >;
1053 };
1054
1055 pinctrl_i2c2: i2c2grp {
1056 fsl,pins = <
1057 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
1058 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
1059 >;
1060 };
1061
1062 pinctrl_i2c2_gpio: i2c2gpiogrp {
1063 fsl,pins = <
1064 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
1065 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
1066 >;
1067 };
1068
1069 pinctrl_i2c3: i2c3grp {
1070 fsl,pins = <
1071 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
1072 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
1073 >;
1074 };
1075
1076 pinctrl_i2c3_gpio: i2c3gpiogrp {
1077 fsl,pins = <
1078 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
1079 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
1080 >;
1081 };
1082
1083 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
1084 fsl,pins = <
1085 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
1086 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
1087 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
1088 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
1089 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
1090 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
1091 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
1092 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
1093 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
1094 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
1095 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
1096 >;
1097 };
1098
1099 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
1100 fsl,pins = <
1101 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
1102 /* DE */
1103 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
1104 /* HSync */
1105 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
1106 /* VSync */
1107 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
1108 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
1109 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
1110 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
1111 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
1112 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
1113 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
1114 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
1115 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
1116 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
1117 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
1118 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
1119 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
1120 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
1121 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
1122 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
1123 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
1124 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
1125 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
1126 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
1127 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
1128 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
1129 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
1130 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
1131 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
1132 >;
1133 };
1134
1135 pinctrl_ipu2_vdac: ipu2vdacgrp {
1136 fsl,pins = <
1137 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
1138 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
1139 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
1140 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
1141 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
1142 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
1143 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
1144 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
1145 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
1146 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
1147 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
1148 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
1149 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
1150 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
1151 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
1152 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
1153 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
1154 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
1155 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
1156 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
1157 >;
1158 };
1159
1160 pinctrl_mmc_cd: mmccdgrp {
1161 fsl,pins = <
1162 /* MMC1 CD */
1163 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
1164 >;
1165 };
1166
1167 pinctrl_pwm1: pwm1grp {
1168 fsl,pins = <
1169 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
1170 >;
1171 };
1172
1173 pinctrl_pwm2: pwm2grp {
1174 fsl,pins = <
1175 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
1176 >;
1177 };
1178
1179 pinctrl_pwm3: pwm3grp {
1180 fsl,pins = <
1181 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1182 >;
1183 };
1184
1185 pinctrl_pwm4: pwm4grp {
1186 fsl,pins = <
1187 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
1188 >;
1189 };
1190
1191 pinctrl_regulator_usbh_pwr: regusbhpwrgrp {
1192 fsl,pins = <
1193 /* USBH_EN */
1194 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
1195 >;
1196 };
1197
1198 pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp {
1199 fsl,pins = <
1200 /* USBH_HUB_EN */
1201 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
1202 >;
1203 };
1204
1205 pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp {
1206 fsl,pins = <
1207 /* USBO1 power en */
1208 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
1209 >;
1210 };
1211
1212 pinctrl_reset_moci: resetmocigrp {
1213 fsl,pins = <
1214 /* RESET_MOCI control */
1215 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
1216 >;
1217 };
1218
1219 pinctrl_sd_cd: sdcdgrp {
1220 fsl,pins = <
1221 /* SD1 CD */
1222 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
1223 >;
1224 };
1225
1226 pinctrl_sgtl5000: sgtl5000grp {
1227 fsl,pins = <
1228 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
1229 >;
1230 };
1231
1232 pinctrl_spdif: spdifgrp {
1233 fsl,pins = <
1234 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1235 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1236 >;
1237 };
1238
1239 pinctrl_touch_int: touchintgrp {
1240 fsl,pins = <
1241 /* STMPE811 interrupt */
1242 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
1243 >;
1244 };
1245
1246 /* Additional DTR, DSR, DCD */
1247 pinctrl_uart1_ctrl: uart1ctrlgrp {
1248 fsl,pins = <
1249 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
1250 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
1251 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
1252 >;
1253 };
1254
1255 pinctrl_uart1_dce: uart1dcegrp {
1256 fsl,pins = <
1257 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1258 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1259 >;
1260 };
1261
1262 /* DTE mode */
1263 pinctrl_uart1_dte: uart1dtegrp {
1264 fsl,pins = <
1265 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
1266 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
1267 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
1268 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
1269 >;
1270 };
1271
1272 pinctrl_uart2_dce: uart2dcegrp {
1273 fsl,pins = <
1274 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
1275 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
1276 >;
1277 };
1278
1279 /* DTE mode */
1280 pinctrl_uart2_dte: uart2dtegrp {
1281 fsl,pins = <
1282 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
1283 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
1284 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
1285 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
1286 >;
1287 };
1288
1289 pinctrl_uart4_dce: uart4dcegrp {
1290 fsl,pins = <
1291 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1292 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1293 >;
1294 };
1295
1296 /* DTE mode */
1297 pinctrl_uart4_dte: uart4dtegrp {
1298 fsl,pins = <
1299 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
1300 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
1301 >;
1302 };
1303
1304 pinctrl_uart5_dce: uart5dcegrp {
1305 fsl,pins = <
1306 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
1307 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
1308 >;
1309 };
1310
1311 /* DTE mode */
1312 pinctrl_uart5_dte: uart5dtegrp {
1313 fsl,pins = <
1314 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
1315 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
1316 >;
1317 };
1318
1319 pinctrl_usbotg: usbotggrp {
1320 fsl,pins = <
1321 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1322 >;
1323 };
1324
1325 pinctrl_usdhc1_4bit: usdhc1-4bitgrp {
1326 fsl,pins = <
1327 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
1328 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
1329 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
1330 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
1331 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
1332 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
1333 >;
1334 };
1335
1336 pinctrl_usdhc1_8bit: usdhc1-8bitgrp {
1337 fsl,pins = <
1338 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
1339 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
1340 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
1341 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
1342 >;
1343 };
1344
1345 pinctrl_usdhc2: usdhc2grp {
1346 fsl,pins = <
1347 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
1348 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
1349 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
1350 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
1351 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
1352 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
1353 >;
1354 };
1355
1356 pinctrl_usdhc3: usdhc3grp {
1357 fsl,pins = <
1358 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1359 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1360 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1361 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1362 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1363 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1364 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1365 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1366 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1367 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1368 /* eMMC reset */
1369 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
1370 >;
1371 };
1372 };
