0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2013 Freescale Semiconductor, Inc.
0004
0005 #include <dt-bindings/interrupt-controller/irq.h>
0006 #include "imx6q-pinfunc.h"
0007 #include "imx6qdl.dtsi"
0008
0009 / {
0010 aliases {
0011 ipu1 = &ipu2;
0012 spi4 = &ecspi5;
0013 };
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu0: cpu@0 {
0020 compatible = "arm,cortex-a9";
0021 device_type = "cpu";
0022 reg = <0>;
0023 next-level-cache = <&L2>;
0024 operating-points = <
0025 /* kHz uV */
0026 1200000 1275000
0027 996000 1250000
0028 852000 1250000
0029 792000 1175000
0030 396000 975000
0031 >;
0032 fsl,soc-operating-points = <
0033 /* ARM kHz SOC-PU uV */
0034 1200000 1275000
0035 996000 1250000
0036 852000 1250000
0037 792000 1175000
0038 396000 1175000
0039 >;
0040 clock-latency = <61036>; /* two CLK32 periods */
0041 #cooling-cells = <2>;
0042 clocks = <&clks IMX6QDL_CLK_ARM>,
0043 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
0044 <&clks IMX6QDL_CLK_STEP>,
0045 <&clks IMX6QDL_CLK_PLL1_SW>,
0046 <&clks IMX6QDL_CLK_PLL1_SYS>;
0047 clock-names = "arm", "pll2_pfd2_396m", "step",
0048 "pll1_sw", "pll1_sys";
0049 arm-supply = <®_arm>;
0050 pu-supply = <®_pu>;
0051 soc-supply = <®_soc>;
0052 nvmem-cells = <&cpu_speed_grade>;
0053 nvmem-cell-names = "speed_grade";
0054 };
0055
0056 cpu1: cpu@1 {
0057 compatible = "arm,cortex-a9";
0058 device_type = "cpu";
0059 reg = <1>;
0060 next-level-cache = <&L2>;
0061 operating-points = <
0062 /* kHz uV */
0063 1200000 1275000
0064 996000 1250000
0065 852000 1250000
0066 792000 1175000
0067 396000 975000
0068 >;
0069 fsl,soc-operating-points = <
0070 /* ARM kHz SOC-PU uV */
0071 1200000 1275000
0072 996000 1250000
0073 852000 1250000
0074 792000 1175000
0075 396000 1175000
0076 >;
0077 clock-latency = <61036>; /* two CLK32 periods */
0078 #cooling-cells = <2>;
0079 clocks = <&clks IMX6QDL_CLK_ARM>,
0080 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
0081 <&clks IMX6QDL_CLK_STEP>,
0082 <&clks IMX6QDL_CLK_PLL1_SW>,
0083 <&clks IMX6QDL_CLK_PLL1_SYS>;
0084 clock-names = "arm", "pll2_pfd2_396m", "step",
0085 "pll1_sw", "pll1_sys";
0086 arm-supply = <®_arm>;
0087 pu-supply = <®_pu>;
0088 soc-supply = <®_soc>;
0089 };
0090
0091 cpu2: cpu@2 {
0092 compatible = "arm,cortex-a9";
0093 device_type = "cpu";
0094 reg = <2>;
0095 next-level-cache = <&L2>;
0096 operating-points = <
0097 /* kHz uV */
0098 1200000 1275000
0099 996000 1250000
0100 852000 1250000
0101 792000 1175000
0102 396000 975000
0103 >;
0104 fsl,soc-operating-points = <
0105 /* ARM kHz SOC-PU uV */
0106 1200000 1275000
0107 996000 1250000
0108 852000 1250000
0109 792000 1175000
0110 396000 1175000
0111 >;
0112 clock-latency = <61036>; /* two CLK32 periods */
0113 #cooling-cells = <2>;
0114 clocks = <&clks IMX6QDL_CLK_ARM>,
0115 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
0116 <&clks IMX6QDL_CLK_STEP>,
0117 <&clks IMX6QDL_CLK_PLL1_SW>,
0118 <&clks IMX6QDL_CLK_PLL1_SYS>;
0119 clock-names = "arm", "pll2_pfd2_396m", "step",
0120 "pll1_sw", "pll1_sys";
0121 arm-supply = <®_arm>;
0122 pu-supply = <®_pu>;
0123 soc-supply = <®_soc>;
0124 };
0125
0126 cpu3: cpu@3 {
0127 compatible = "arm,cortex-a9";
0128 device_type = "cpu";
0129 reg = <3>;
0130 next-level-cache = <&L2>;
0131 operating-points = <
0132 /* kHz uV */
0133 1200000 1275000
0134 996000 1250000
0135 852000 1250000
0136 792000 1175000
0137 396000 975000
0138 >;
0139 fsl,soc-operating-points = <
0140 /* ARM kHz SOC-PU uV */
0141 1200000 1275000
0142 996000 1250000
0143 852000 1250000
0144 792000 1175000
0145 396000 1175000
0146 >;
0147 clock-latency = <61036>; /* two CLK32 periods */
0148 #cooling-cells = <2>;
0149 clocks = <&clks IMX6QDL_CLK_ARM>,
0150 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
0151 <&clks IMX6QDL_CLK_STEP>,
0152 <&clks IMX6QDL_CLK_PLL1_SW>,
0153 <&clks IMX6QDL_CLK_PLL1_SYS>;
0154 clock-names = "arm", "pll2_pfd2_396m", "step",
0155 "pll1_sw", "pll1_sys";
0156 arm-supply = <®_arm>;
0157 pu-supply = <®_pu>;
0158 soc-supply = <®_soc>;
0159 };
0160 };
0161
0162 soc: soc {
0163 ocram: sram@900000 {
0164 compatible = "mmio-sram";
0165 reg = <0x00900000 0x40000>;
0166 clocks = <&clks IMX6QDL_CLK_OCRAM>;
0167 };
0168
0169 aips1: bus@2000000 { /* AIPS1 */
0170 spba-bus@2000000 {
0171 ecspi5: spi@2018000 {
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
0175 reg = <0x02018000 0x4000>;
0176 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
0177 clocks = <&clks IMX6Q_CLK_ECSPI5>,
0178 <&clks IMX6Q_CLK_ECSPI5>;
0179 clock-names = "ipg", "per";
0180 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
0181 dma-names = "rx", "tx";
0182 status = "disabled";
0183 };
0184 };
0185 };
0186
0187 sata: sata@2200000 {
0188 compatible = "fsl,imx6q-ahci";
0189 reg = <0x02200000 0x4000>;
0190 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
0191 clocks = <&clks IMX6QDL_CLK_SATA>,
0192 <&clks IMX6QDL_CLK_SATA_REF_100M>,
0193 <&clks IMX6QDL_CLK_AHB>;
0194 clock-names = "sata", "sata_ref", "ahb";
0195 status = "disabled";
0196 };
0197
0198 gpu_vg: gpu@2204000 {
0199 compatible = "vivante,gc";
0200 reg = <0x02204000 0x4000>;
0201 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
0202 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
0203 <&clks IMX6QDL_CLK_GPU2D_CORE>;
0204 clock-names = "bus", "core";
0205 power-domains = <&pd_pu>;
0206 #cooling-cells = <2>;
0207 };
0208
0209 ipu2: ipu@2800000 {
0210 #address-cells = <1>;
0211 #size-cells = <0>;
0212 compatible = "fsl,imx6q-ipu";
0213 reg = <0x02800000 0x400000>;
0214 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
0215 <0 7 IRQ_TYPE_LEVEL_HIGH>;
0216 clocks = <&clks IMX6QDL_CLK_IPU2>,
0217 <&clks IMX6QDL_CLK_IPU2_DI0>,
0218 <&clks IMX6QDL_CLK_IPU2_DI1>;
0219 clock-names = "bus", "di0", "di1";
0220 resets = <&src 4>;
0221
0222 ipu2_csi0: port@0 {
0223 reg = <0>;
0224
0225 ipu2_csi0_from_mipi_vc2: endpoint {
0226 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
0227 };
0228 };
0229
0230 ipu2_csi1: port@1 {
0231 reg = <1>;
0232
0233 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
0234 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
0235 };
0236 };
0237
0238 ipu2_di0: port@2 {
0239 #address-cells = <1>;
0240 #size-cells = <0>;
0241 reg = <2>;
0242
0243 ipu2_di0_disp0: endpoint@0 {
0244 reg = <0>;
0245 };
0246
0247 ipu2_di0_hdmi: endpoint@1 {
0248 reg = <1>;
0249 remote-endpoint = <&hdmi_mux_2>;
0250 };
0251
0252 ipu2_di0_mipi: endpoint@2 {
0253 reg = <2>;
0254 remote-endpoint = <&mipi_mux_2>;
0255 };
0256
0257 ipu2_di0_lvds0: endpoint@3 {
0258 reg = <3>;
0259 remote-endpoint = <&lvds0_mux_2>;
0260 };
0261
0262 ipu2_di0_lvds1: endpoint@4 {
0263 reg = <4>;
0264 remote-endpoint = <&lvds1_mux_2>;
0265 };
0266 };
0267
0268 ipu2_di1: port@3 {
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271 reg = <3>;
0272
0273 ipu2_di1_hdmi: endpoint@1 {
0274 reg = <1>;
0275 remote-endpoint = <&hdmi_mux_3>;
0276 };
0277
0278 ipu2_di1_mipi: endpoint@2 {
0279 reg = <2>;
0280 remote-endpoint = <&mipi_mux_3>;
0281 };
0282
0283 ipu2_di1_lvds0: endpoint@3 {
0284 reg = <3>;
0285 remote-endpoint = <&lvds0_mux_3>;
0286 };
0287
0288 ipu2_di1_lvds1: endpoint@4 {
0289 reg = <4>;
0290 remote-endpoint = <&lvds1_mux_3>;
0291 };
0292 };
0293 };
0294 };
0295
0296 capture-subsystem {
0297 compatible = "fsl,imx-capture-subsystem";
0298 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
0299 };
0300
0301 display-subsystem {
0302 compatible = "fsl,imx-display-subsystem";
0303 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
0304 };
0305 };
0306
0307 &gpio1 {
0308 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
0309 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
0310 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
0311 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
0312 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
0313 <&iomuxc 22 116 10>;
0314 };
0315
0316 &gpio2 {
0317 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
0318 <&iomuxc 31 44 1>;
0319 };
0320
0321 &gpio3 {
0322 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
0323 };
0324
0325 &gpio4 {
0326 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
0327 };
0328
0329 &gpio5 {
0330 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
0331 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
0332 };
0333
0334 &gpio6 {
0335 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
0336 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
0337 <&iomuxc 31 86 1>;
0338 };
0339
0340 &gpio7 {
0341 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
0342 };
0343
0344 &gpr {
0345 ipu1_csi0_mux {
0346 compatible = "video-mux";
0347 mux-controls = <&mux 0>;
0348 #address-cells = <1>;
0349 #size-cells = <0>;
0350
0351 port@0 {
0352 reg = <0>;
0353
0354 ipu1_csi0_mux_from_mipi_vc0: endpoint {
0355 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
0356 };
0357 };
0358
0359 port@1 {
0360 reg = <1>;
0361
0362 ipu1_csi0_mux_from_parallel_sensor: endpoint {
0363 };
0364 };
0365
0366 port@2 {
0367 reg = <2>;
0368
0369 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
0370 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
0371 };
0372 };
0373 };
0374
0375 ipu2_csi1_mux {
0376 compatible = "video-mux";
0377 mux-controls = <&mux 1>;
0378 #address-cells = <1>;
0379 #size-cells = <0>;
0380
0381 port@0 {
0382 reg = <0>;
0383
0384 ipu2_csi1_mux_from_mipi_vc3: endpoint {
0385 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
0386 };
0387 };
0388
0389 port@1 {
0390 reg = <1>;
0391
0392 ipu2_csi1_mux_from_parallel_sensor: endpoint {
0393 };
0394 };
0395
0396 port@2 {
0397 reg = <2>;
0398
0399 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
0400 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
0401 };
0402 };
0403 };
0404 };
0405
0406 &hdmi {
0407 compatible = "fsl,imx6q-hdmi";
0408
0409 ports {
0410 port@2 {
0411 reg = <2>;
0412
0413 hdmi_mux_2: endpoint {
0414 remote-endpoint = <&ipu2_di0_hdmi>;
0415 };
0416 };
0417
0418 port@3 {
0419 reg = <3>;
0420
0421 hdmi_mux_3: endpoint {
0422 remote-endpoint = <&ipu2_di1_hdmi>;
0423 };
0424 };
0425 };
0426 };
0427
0428 &iomuxc {
0429 compatible = "fsl,imx6q-iomuxc";
0430 };
0431
0432 &ipu1_csi1 {
0433 ipu1_csi1_from_mipi_vc1: endpoint {
0434 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
0435 };
0436 };
0437
0438 &ldb {
0439 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
0440 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
0441 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
0442 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
0443 clock-names = "di0_pll", "di1_pll",
0444 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
0445 "di0", "di1";
0446
0447 lvds-channel@0 {
0448 port@2 {
0449 reg = <2>;
0450
0451 lvds0_mux_2: endpoint {
0452 remote-endpoint = <&ipu2_di0_lvds0>;
0453 };
0454 };
0455
0456 port@3 {
0457 reg = <3>;
0458
0459 lvds0_mux_3: endpoint {
0460 remote-endpoint = <&ipu2_di1_lvds0>;
0461 };
0462 };
0463 };
0464
0465 lvds-channel@1 {
0466 port@2 {
0467 reg = <2>;
0468
0469 lvds1_mux_2: endpoint {
0470 remote-endpoint = <&ipu2_di0_lvds1>;
0471 };
0472 };
0473
0474 port@3 {
0475 reg = <3>;
0476
0477 lvds1_mux_3: endpoint {
0478 remote-endpoint = <&ipu2_di1_lvds1>;
0479 };
0480 };
0481 };
0482 };
0483
0484 &mipi_csi {
0485 port@1 {
0486 reg = <1>;
0487
0488 mipi_vc0_to_ipu1_csi0_mux: endpoint {
0489 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
0490 };
0491 };
0492
0493 port@2 {
0494 reg = <2>;
0495
0496 mipi_vc1_to_ipu1_csi1: endpoint {
0497 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
0498 };
0499 };
0500
0501 port@3 {
0502 reg = <3>;
0503
0504 mipi_vc2_to_ipu2_csi0: endpoint {
0505 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
0506 };
0507 };
0508
0509 port@4 {
0510 reg = <4>;
0511
0512 mipi_vc3_to_ipu2_csi1_mux: endpoint {
0513 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
0514 };
0515 };
0516 };
0517
0518 &mipi_dsi {
0519 ports {
0520 port@2 {
0521 reg = <2>;
0522
0523 mipi_mux_2: endpoint {
0524 remote-endpoint = <&ipu2_di0_mipi>;
0525 };
0526 };
0527
0528 port@3 {
0529 reg = <3>;
0530
0531 mipi_mux_3: endpoint {
0532 remote-endpoint = <&ipu2_di1_mipi>;
0533 };
0534 };
0535 };
0536 };
0537
0538 &mux {
0539 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
0540 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
0541 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
0542 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
0543 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
0544 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
0545 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
0546 };
0547
0548 &vpu {
0549 compatible = "fsl,imx6q-vpu", "cnm,coda960";
0550 };
