0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright 2016-2017
0004 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx6q.dtsi"
0010
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/pwm/pwm.h>
0013
0014 / {
0015 model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
0016 compatible = "lwn,mccmon6", "fsl,imx6q";
0017
0018 memory@10000000 {
0019 device_type = "memory";
0020 reg = <0x10000000 0x80000000>;
0021 };
0022
0023 backlight_lvds: backlight {
0024 compatible = "pwm-backlight";
0025 pinctrl-names = "default";
0026 pinctrl-0 = <&pinctrl_backlight>;
0027 pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
0028 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
0029 10 11 12 13 14 15 16 17 18 19
0030 20 21 22 23 24 25 26 27 28 29
0031 30 31 32 33 34 35 36 37 38 39
0032 40 41 42 43 44 45 46 47 48 49
0033 50 51 52 53 54 55 56 57 58 59
0034 60 61 62 63 64 65 66 67 68 69
0035 70 71 72 73 74 75 76 77 78 79
0036 80 81 82 83 84 85 86 87 88 89
0037 90 91 92 93 94 95 96 97 98 99
0038 100 101 102 103 104 105 106 107 108 109
0039 110 111 112 113 114 115 116 117 118 119
0040 120 121 122 123 124 125 126 127 128 129
0041 130 131 132 133 134 135 136 137 138 139
0042 140 141 142 143 144 145 146 147 148 149
0043 150 151 152 153 154 155 156 157 158 159
0044 160 161 162 163 164 165 166 167 168 169
0045 170 171 172 173 174 175 176 177 178 179
0046 180 181 182 183 184 185 186 187 188 189
0047 190 191 192 193 194 195 196 197 198 199
0048 200 201 202 203 204 205 206 207 208 209
0049 210 211 212 213 214 215 216 217 218 219
0050 220 221 222 223 224 225 226 227 228 229
0051 230 231 232 233 234 235 236 237 238 239
0052 240 241 242 243 244 245 246 247 248 249
0053 250 251 252 253 254 255>;
0054 default-brightness-level = <50>;
0055 enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
0056 };
0057
0058 reg_lvds: regulator-lvds {
0059 compatible = "regulator-fixed";
0060 regulator-name = "lvds_ppen";
0061 regulator-min-microvolt = <3300000>;
0062 regulator-max-microvolt = <3300000>;
0063 regulator-boot-on;
0064 pinctrl-names = "default";
0065 pinctrl-0 = <&pinctrl_reg_lvds>;
0066 gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
0067 enable-active-high;
0068 };
0069
0070 panel-lvds0 {
0071 compatible = "innolux,g121x1-l03";
0072 backlight = <&backlight_lvds>;
0073 power-supply = <®_lvds>;
0074
0075 port {
0076 panel_in_lvds0: endpoint {
0077 remote-endpoint = <&lvds0_out>;
0078 };
0079 };
0080 };
0081 };
0082
0083 &ecspi3 {
0084 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
0085 pinctrl-names = "default";
0086 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
0087 status = "okay";
0088
0089 s25sl032p: flash@0 {
0090 #address-cells = <1>;
0091 #size-cells = <1>;
0092 compatible = "jedec,spi-nor";
0093 spi-max-frequency = <40000000>;
0094 reg = <0>;
0095 };
0096 };
0097
0098 &fec {
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&pinctrl_enet>;
0101 phy-mode = "rgmii";
0102 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
0103 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
0104 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
0105 status = "okay";
0106 };
0107
0108 &i2c1 {
0109 clock-frequency = <100000>;
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_i2c1>;
0112 status = "okay";
0113 };
0114
0115 &i2c2 {
0116 clock-frequency = <100000>;
0117 pinctrl-names = "default";
0118 pinctrl-0 = <&pinctrl_i2c2>;
0119 status = "okay";
0120
0121 pfuze100: pmic@8 {
0122 compatible = "fsl,pfuze100";
0123 reg = <0x08>;
0124
0125 regulators {
0126 sw1a_reg: sw1ab {
0127 regulator-min-microvolt = <300000>;
0128 regulator-max-microvolt = <1875000>;
0129 regulator-boot-on;
0130 regulator-always-on;
0131 regulator-ramp-delay = <6250>;
0132 };
0133
0134 sw1c_reg: sw1c {
0135 regulator-min-microvolt = <300000>;
0136 regulator-max-microvolt = <1875000>;
0137 regulator-boot-on;
0138 regulator-always-on;
0139 regulator-ramp-delay = <6250>;
0140 };
0141
0142 sw2_reg: sw2 {
0143 regulator-min-microvolt = <800000>;
0144 regulator-max-microvolt = <3950000>;
0145 regulator-boot-on;
0146 regulator-always-on;
0147 };
0148
0149 sw3a_reg: sw3a {
0150 regulator-min-microvolt = <400000>;
0151 regulator-max-microvolt = <1975000>;
0152 regulator-boot-on;
0153 regulator-always-on;
0154 };
0155
0156 sw3b_reg: sw3b {
0157 regulator-min-microvolt = <400000>;
0158 regulator-max-microvolt = <1975000>;
0159 regulator-boot-on;
0160 regulator-always-on;
0161 };
0162
0163 sw4_reg: sw4 {
0164 regulator-min-microvolt = <800000>;
0165 regulator-max-microvolt = <3300000>;
0166 };
0167
0168 swbst_reg: swbst {
0169 regulator-min-microvolt = <5000000>;
0170 regulator-max-microvolt = <5150000>;
0171 };
0172
0173 snvs_reg: vsnvs {
0174 regulator-min-microvolt = <1000000>;
0175 regulator-max-microvolt = <3000000>;
0176 regulator-boot-on;
0177 regulator-always-on;
0178 };
0179
0180 vref_reg: vrefddr {
0181 regulator-boot-on;
0182 regulator-always-on;
0183 };
0184
0185 vgen1_reg: vgen1 {
0186 regulator-min-microvolt = <800000>;
0187 regulator-max-microvolt = <1550000>;
0188 };
0189
0190 vgen2_reg: vgen2 {
0191 regulator-min-microvolt = <800000>;
0192 regulator-max-microvolt = <1550000>;
0193 };
0194
0195 vgen3_reg: vgen3 {
0196 regulator-min-microvolt = <1800000>;
0197 regulator-max-microvolt = <3300000>;
0198 };
0199
0200 vgen4_reg: vgen4 {
0201 regulator-min-microvolt = <1800000>;
0202 regulator-max-microvolt = <3300000>;
0203 regulator-always-on;
0204 };
0205
0206 vgen5_reg: vgen5 {
0207 regulator-min-microvolt = <1800000>;
0208 regulator-max-microvolt = <3300000>;
0209 regulator-always-on;
0210 };
0211
0212 vgen6_reg: vgen6 {
0213 regulator-min-microvolt = <1800000>;
0214 regulator-max-microvolt = <3300000>;
0215 regulator-always-on;
0216 };
0217 };
0218 };
0219 };
0220
0221 &ldb {
0222 status = "okay";
0223
0224 lvds0: lvds-channel@0 {
0225 fsl,data-mapping = "spwg";
0226 fsl,data-width = <24>;
0227 status = "okay";
0228
0229 port@4 {
0230 reg = <4>;
0231
0232 lvds0_out: endpoint {
0233 remote-endpoint = <&panel_in_lvds0>;
0234 };
0235 };
0236 };
0237 };
0238
0239 &pwm2 {
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pinctrl_pwm2>;
0242 status = "okay";
0243 };
0244
0245 &uart1 {
0246 pinctrl-names = "default";
0247 pinctrl-0 = <&pinctrl_uart1>;
0248 status = "okay";
0249 };
0250
0251 &uart4 {
0252 pinctrl-names = "default";
0253 pinctrl-0 = <&pinctrl_uart4>;
0254 uart-has-rtscts;
0255 status = "okay";
0256 };
0257
0258 &usdhc2 {
0259 pinctrl-names = "default";
0260 pinctrl-0 = <&pinctrl_usdhc2>;
0261 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
0262 bus-width = <4>;
0263 status = "okay";
0264 };
0265
0266 &usdhc3 {
0267 pinctrl-names = "default";
0268 pinctrl-0 = <&pinctrl_usdhc3>;
0269 bus-width = <8>;
0270 non-removable;
0271 status = "okay";
0272 };
0273
0274 &weim {
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
0277 ranges = <0 0 0x08000000 0x08000000>;
0278 status = "okay";
0279
0280 nor@0,0 {
0281 compatible = "cfi-flash";
0282 reg = <0 0 0x02000000>;
0283 #address-cells = <1>;
0284 #size-cells = <1>;
0285 bank-width = <2>;
0286 use-advanced-sector-protection;
0287 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0288 0x0000c000 0x1404a38e 0x00000000>;
0289 };
0290 };
0291
0292 &iomuxc {
0293 pinctrl-names = "default";
0294
0295 pinctrl_backlight: dispgrp {
0296 fsl,pins = <
0297 /* BLEN_OUT */
0298 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
0299 >;
0300 };
0301
0302 pinctrl_ecspi3: ecspi3grp {
0303 fsl,pins = <
0304 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
0305 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
0306 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
0307 >;
0308 };
0309
0310 pinctrl_ecspi3_cs: ecspi3csgrp {
0311 fsl,pins = <
0312 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
0313 >;
0314 };
0315
0316 pinctrl_ecspi3_flwp: ecspi3flwpgrp {
0317 fsl,pins = <
0318 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
0319 >;
0320 };
0321
0322 pinctrl_enet: enetgrp {
0323 fsl,pins = <
0324 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0325 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0326 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
0327 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
0328 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
0329 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
0330 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
0331 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
0332 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0333 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
0334 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
0335 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
0336 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
0337 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
0338 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
0339 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
0340 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
0341 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
0342 >;
0343 };
0344
0345 pinctrl_i2c1: i2c1grp {
0346 fsl,pins = <
0347 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
0348 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
0349 >;
0350 };
0351
0352 pinctrl_i2c2: i2c2grp {
0353 fsl,pins = <
0354 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0355 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0356 >;
0357 };
0358
0359 pinctrl_pwm2: pwm2grp {
0360 fsl,pins = <
0361 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
0362 >;
0363 };
0364
0365 pinctrl_reg_lvds: reqlvdsgrp {
0366 fsl,pins = <
0367 /* LVDS_PPEN_OUT */
0368 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
0369 >;
0370 };
0371
0372 pinctrl_uart1: uart1grp {
0373 fsl,pins = <
0374 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
0375 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
0376 >;
0377 };
0378
0379 pinctrl_uart4: uart4grp {
0380 fsl,pins = <
0381 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
0382 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
0383 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
0384 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
0385 >;
0386 };
0387
0388 pinctrl_usdhc2: usdhc2grp {
0389 fsl,pins = <
0390 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0391 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0392 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0393 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0394 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0395 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0396 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1
0397 >;
0398 };
0399
0400 pinctrl_usdhc3: usdhc3grp {
0401 fsl,pins = <
0402 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0403 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0404 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0405 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0406 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0407 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0408 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
0409 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
0410 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
0411 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
0412 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
0413 >;
0414 };
0415
0416 pinctrl_weim_cs0: weimcs0grp {
0417 fsl,pins = <
0418 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
0419 >;
0420 };
0421
0422 pinctrl_weim_nor: weimnorgrp {
0423 fsl,pins = <
0424 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
0425 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
0426 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
0427 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
0428 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
0429 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
0430 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
0431 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
0432 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
0433 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
0434 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
0435 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
0436 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
0437 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
0438 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
0439 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
0440 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
0441 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
0442 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
0443 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
0444 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
0445 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
0446 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
0447 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
0448 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
0449 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
0450 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
0451 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
0452 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
0453 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
0454 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
0455 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
0456 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
0457 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
0458 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
0459 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
0460 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
0461 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
0462 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
0463 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
0464 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
0465 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
0466 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
0467 >;
0468 };
0469 };
