0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2018
0004 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx6q.dtsi"
0010
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/pwm/pwm.h>
0013 #include <dt-bindings/sound/fsl-imx-audmux.h>
0014
0015 / {
0016 backlight_lcd: backlight-lcd {
0017 compatible = "pwm-backlight";
0018 pwms = <&pwm1 0 5000000>;
0019 brightness-levels = <0 255>;
0020 num-interpolated-steps = <255>;
0021 default-brightness-level = <250>;
0022 };
0023
0024 beeper {
0025 compatible = "pwm-beeper";
0026 pwms = <&pwm2 0 500000>;
0027 };
0028
0029 lcd_display: display {
0030 compatible = "fsl,imx-parallel-display";
0031 #address-cells = <1>;
0032 #size-cells = <0>;
0033 interface-pix-fmt = "rgb24";
0034 pinctrl-names = "default";
0035 pinctrl-0 = <&pinctrl_ipu1>;
0036
0037 port@0 {
0038 reg = <0>;
0039
0040 lcd_display_in: endpoint {
0041 remote-endpoint = <&ipu1_di0_disp0>;
0042 };
0043 };
0044
0045 port@1 {
0046 reg = <1>;
0047
0048 lcd_display_out: endpoint {
0049 remote-endpoint = <&lcd_panel_in>;
0050 };
0051 };
0052 };
0053
0054 lcd_panel: lcd-panel {
0055 compatible = "auo,g070vvn01";
0056 backlight = <&backlight_lcd>;
0057 power-supply = <®_display>;
0058
0059 port {
0060 lcd_panel_in: endpoint {
0061 remote-endpoint = <&lcd_display_out>;
0062 };
0063 };
0064 };
0065
0066 leds {
0067 compatible = "gpio-leds";
0068
0069 green {
0070 label = "led1";
0071 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
0072 linux,default-trigger = "gpio";
0073 default-state = "off";
0074 };
0075
0076 red {
0077 label = "led0";
0078 gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
0079 linux,default-trigger = "gpio";
0080 default-state = "off";
0081 };
0082 };
0083
0084 reg_3p3v: regulator-3p3v {
0085 compatible = "regulator-fixed";
0086 regulator-name = "3P3V";
0087 regulator-min-microvolt = <3300000>;
0088 regulator-max-microvolt = <3300000>;
0089 regulator-always-on;
0090 };
0091
0092 reg_audio: regulator-audio {
0093 compatible = "regulator-fixed";
0094 regulator-name = "sgtl5000-supply";
0095 gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
0096 enable-active-high;
0097 regulator-always-on;
0098 };
0099
0100 reg_display: regulator-display {
0101 compatible = "regulator-fixed";
0102 regulator-name = "display-supply";
0103 regulator-min-microvolt = <3300000>;
0104 regulator-max-microvolt = <3300000>;
0105 regulator-always-on;
0106 };
0107
0108 reg_usb_h1_vbus: regulator-usb_h1_vbus {
0109 compatible = "regulator-fixed";
0110 regulator-name = "usb_h1_vbus";
0111 regulator-min-microvolt = <5000000>;
0112 regulator-max-microvolt = <5000000>;
0113 enable-active-high;
0114 };
0115
0116 sound {
0117 compatible = "simple-audio-card";
0118 simple-audio-card,name = "imx6q-sgtl5000-audio";
0119 simple-audio-card,format = "i2s";
0120 simple-audio-card,bitclock-master = <&codec_dai>;
0121 simple-audio-card,frame-master = <&codec_dai>;
0122
0123 cpu_dai: simple-audio-card,cpu {
0124 sound-dai = <&ssi1>;
0125 };
0126
0127 codec_dai: simple-audio-card,codec {
0128 sound-dai = <&sgtl5000>;
0129 };
0130 };
0131 };
0132
0133 &audmux {
0134 pinctrl-names = "default";
0135 pinctrl-0 = <&pinctrl_audmux>;
0136 status = "okay";
0137
0138 ssi1 {
0139 fsl,audmux-port = <0>;
0140 fsl,port-config = <
0141 (IMX_AUDMUX_V2_PTCR_SYN |
0142 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
0143 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
0144 IMX_AUDMUX_V2_PTCR_TFSDIR |
0145 IMX_AUDMUX_V2_PTCR_TCLKDIR)
0146 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
0147 >;
0148 };
0149
0150 aud3 {
0151 fsl,audmux-port = <2>;
0152 fsl,port-config = <
0153 IMX_AUDMUX_V2_PTCR_SYN
0154 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
0155 >;
0156 };
0157 };
0158
0159 &can1 {
0160 pinctrl-names = "default";
0161 pinctrl-0 = <&pinctrl_flexcan1>;
0162 };
0163
0164 &can2 {
0165 pinctrl-names = "default";
0166 pinctrl-0 = <&pinctrl_flexcan2>;
0167 };
0168
0169 &fec {
0170 pinctrl-names = "default";
0171 pinctrl-0 = <&pinctrl_enet>;
0172 phy-mode = "rgmii";
0173 fsl,magic-packet;
0174 status = "okay";
0175 };
0176
0177 &i2c1 {
0178 clock-frequency = <400000>;
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_i2c1>;
0181 status = "okay";
0182
0183 touchscreen@5d {
0184 compatible = "goodix,gt911";
0185 reg = <0x5d>;
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&pinctrl_ts>;
0188 interrupt-parent = <&gpio1>;
0189 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
0190 irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0191 reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
0192 };
0193
0194 ds1307: rtc@32 {
0195 compatible = "dallas,ds1307";
0196 reg = <0x32>;
0197 };
0198 };
0199
0200 &i2c2 {
0201 clock-frequency = <400000>;
0202 pinctrl-names = "default";
0203 pinctrl-0 = <&pinctrl_i2c2>;
0204 status = "okay";
0205
0206 sgtl5000: audio-codec@a {
0207 compatible = "fsl,sgtl5000";
0208 #sound-dai-cells = <0>;
0209 reg = <0x0a>;
0210 pinctrl-names = "default";
0211 pinctrl-0 = <&pinctrl_codec>;
0212 clocks = <&clks IMX6QDL_CLK_CKO>;
0213 VDDA-supply = <®_3p3v>;
0214 VDDIO-supply = <®_3p3v>;
0215 };
0216 };
0217
0218 &iomuxc {
0219 pinctrl_audmux: audmuxgrp {
0220 fsl,pins = <
0221 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
0222 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
0223 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
0224 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
0225 >;
0226 };
0227
0228 pinctrl_codec: codecgrp {
0229 fsl,pins = <
0230 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
0231 /* sgtl5000 sys_mclk clock routed to CLKO1 */
0232 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
0233 >;
0234 };
0235
0236 pinctrl_enet: enetgrp {
0237 fsl,pins = <
0238 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0239 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0240 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
0241 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
0242 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
0243 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
0244 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
0245 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
0246 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0247 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
0248 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
0249 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
0250 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
0251 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
0252 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
0253 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
0254 >;
0255 };
0256
0257 pinctrl_flexcan1: can1grp {
0258 fsl,pins = <
0259 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
0260 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
0261 >;
0262 };
0263
0264 pinctrl_flexcan2: can2grp {
0265 fsl,pins = <
0266 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
0267 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
0268 >;
0269 };
0270
0271 pinctrl_i2c1: i2c1grp {
0272 fsl,pins = <
0273 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
0274 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
0275 >;
0276 };
0277
0278 pinctrl_i2c2: i2c2grp {
0279 fsl,pins = <
0280 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0281 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0282 >;
0283 };
0284
0285 pinctrl_ipu1: ipu1grp {
0286 fsl,pins = <
0287 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
0288 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
0289 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
0290 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
0291 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
0292 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
0293 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
0294 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
0295 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
0296 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
0297 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
0298 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
0299 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
0300 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
0301 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
0302 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
0303 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
0304 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
0305 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
0306 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
0307 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
0308 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
0309 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
0310 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
0311 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
0312 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
0313 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
0314 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
0315 >;
0316 };
0317
0318 pinctrl_pwm1: pwm1grp {
0319 fsl,pins = <
0320 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
0321 >;
0322 };
0323
0324 pinctrl_pwm2: pwm2grp {
0325 fsl,pins = <
0326 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
0327 >;
0328 };
0329
0330 pinctrl_ts: tsgrp {
0331 fsl,pins = <
0332 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
0333 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
0334 >;
0335 };
0336
0337 pinctrl_uart1: uart1grp {
0338 fsl,pins = <
0339 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
0340 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
0341 >;
0342 };
0343
0344 pinctrl_uart2: uart2grp {
0345 fsl,pins = <
0346 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
0347 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
0348 MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
0349 MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
0350 >;
0351 };
0352
0353 pinctrl_usdhc2: usdhc2grp {
0354 fsl,pins = <
0355 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0356 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0357 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0358 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0359 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0360 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0361 >;
0362 };
0363
0364 pinctrl_usdhc4: usdhc4grp {
0365 fsl,pins = <
0366 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
0367 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
0368 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
0369 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
0370 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
0371 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
0372 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
0373 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
0374 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
0375 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
0376 >;
0377 };
0378 };
0379
0380 &pwm1 {
0381 #pwm-cells = <2>;
0382 pinctrl-names = "default";
0383 pinctrl-0 = <&pinctrl_pwm1>;
0384 status = "okay";
0385 };
0386
0387 &pwm2 {
0388 #pwm-cells = <2>;
0389 pinctrl-names = "default";
0390 pinctrl-0 = <&pinctrl_pwm2>;
0391 status = "okay";
0392 };
0393
0394 &ssi1 {
0395 status = "okay";
0396 };
0397
0398 &uart1 {
0399 pinctrl-names = "default";
0400 pinctrl-0 = <&pinctrl_uart1>;
0401 status = "okay";
0402 };
0403
0404 &uart2 {
0405 pinctrl-names = "default";
0406 pinctrl-0 = <&pinctrl_uart2>;
0407 uart-has-rtscts;
0408 };
0409
0410 &usbh1 {
0411 status = "okay";
0412 };
0413
0414 &usdhc2 {
0415 pinctrl-names = "default";
0416 pinctrl-0 = <&pinctrl_usdhc2>;
0417 bus-width = <4>;
0418 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
0419 status = "okay";
0420 };
0421
0422 &usdhc4 {
0423 pinctrl-names = "default";
0424 pinctrl-0 = <&pinctrl_usdhc4>;
0425 bus-width = <8>;
0426 non-removable;
0427 no-1-8-v;
0428 keep-power-in-suspend;
0429 status = "okay";
0430 };
0431
0432 &wdog1 {
0433 status = "okay";
0434 };
