0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright 2013 Gateworks Corporation
0004 */
0005
0006 /dts-v1/;
0007 #include "imx6q.dtsi"
0008 #include "imx6qdl-gw54xx.dtsi"
0009 #include <dt-bindings/media/tda1997x.h>
0010
0011 / {
0012 model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
0013 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
0014
0015 sound-digital {
0016 compatible = "simple-audio-card";
0017 simple-audio-card,name = "tda1997x-audio";
0018 simple-audio-card,format = "i2s";
0019 simple-audio-card,bitclock-master = <&sound_codec>;
0020 simple-audio-card,frame-master = <&sound_codec>;
0021
0022 sound_cpu: simple-audio-card,cpu {
0023 sound-dai = <&ssi2>;
0024 };
0025
0026 sound_codec: simple-audio-card,codec {
0027 sound-dai = <&hdmi_receiver>;
0028 };
0029 };
0030 };
0031
0032 &i2c3 {
0033 adv7180: camera@20 {
0034 compatible = "adi,adv7180";
0035 pinctrl-names = "default";
0036 pinctrl-0 = <&pinctrl_adv7180>;
0037 reg = <0x20>;
0038 powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
0039 interrupt-parent = <&gpio3>;
0040 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
0041
0042 port {
0043 adv7180_to_ipu2_csi1_mux: endpoint {
0044 remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
0045 bus-width = <8>;
0046 };
0047 };
0048 };
0049
0050 hdmi_receiver: hdmi-receiver@48 {
0051 compatible = "nxp,tda19971";
0052 pinctrl-names = "default";
0053 pinctrl-0 = <&pinctrl_tda1997x>;
0054 reg = <0x48>;
0055 interrupt-parent = <&gpio1>;
0056 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
0057 DOVDD-supply = <®_3p3v>;
0058 AVDD-supply = <&sw4_reg>;
0059 DVDD-supply = <&sw4_reg>;
0060 #sound-dai-cells = <0>;
0061 nxp,audout-format = "i2s";
0062 nxp,audout-layout = <0>;
0063 nxp,audout-width = <16>;
0064 nxp,audout-mclk-fs = <128>;
0065 /*
0066 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
0067 * and Y[11:4] across 16bits in the same cycle
0068 * which we map to VP[15:08]<->CSI_DATA[19:12]
0069 */
0070 nxp,vidout-portcfg =
0071 /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
0072 < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
0073 /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
0074 < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
0075 /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
0076 < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
0077 /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
0078 < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
0079
0080 port {
0081 tda1997x_to_ipu1_csi0_mux: endpoint {
0082 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
0083 bus-width = <16>;
0084 hsync-active = <1>;
0085 vsync-active = <1>;
0086 data-active = <1>;
0087 };
0088 };
0089 };
0090 };
0091
0092 &ipu1_csi0_from_ipu1_csi0_mux {
0093 bus-width = <16>;
0094 };
0095
0096 &ipu1_csi0_mux_from_parallel_sensor {
0097 remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
0098 bus-width = <16>;
0099 };
0100
0101 &ipu1_csi0 {
0102 pinctrl-names = "default";
0103 pinctrl-0 = <&pinctrl_ipu1_csi0>;
0104 };
0105
0106 &ipu2_csi1_from_ipu2_csi1_mux {
0107 bus-width = <8>;
0108 };
0109
0110 &ipu2_csi1_mux_from_parallel_sensor {
0111 remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
0112 bus-width = <8>;
0113 };
0114
0115 &ipu2_csi1 {
0116 pinctrl-names = "default";
0117 pinctrl-0 = <&pinctrl_ipu2_csi1>;
0118 };
0119
0120 &sata {
0121 status = "okay";
0122 };
0123
0124 &iomuxc {
0125 pinctrl_adv7180: adv7180grp {
0126 fsl,pins = <
0127 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
0128 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
0129 >;
0130 };
0131
0132 pinctrl_ipu1_csi0: ipu1_csi0grp {
0133 fsl,pins = <
0134 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
0135 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
0136 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
0137 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
0138 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
0139 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
0140 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
0141 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
0142 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
0143 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
0144 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
0145 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
0146 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
0147 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
0148 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
0149 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
0150 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
0151 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
0152 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
0153 >;
0154 };
0155
0156 pinctrl_ipu2_csi1: ipu2_csi1grp {
0157 fsl,pins = <
0158 MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
0159 MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
0160 MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
0161 MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
0162 MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
0163 MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
0164 MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
0165 MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
0166 MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
0167 MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
0168 MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
0169 >;
0170 };
0171
0172 pinctrl_tda1997x: tda1997xgrp {
0173 fsl,pins = <
0174 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
0175 >;
0176 };
0177 };
