0001 /*
0002 * Copyright 2016 United Western Technologies.
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * Or, alternatively,
0020 *
0021 * b) Permission is hereby granted, free of charge, to any person
0022 * obtaining a copy of this software and associated documentation
0023 * files (the "Software"), to deal in the Software without
0024 * restriction, including without limitation the rights to use,
0025 * copy, modify, merge, publish, distribute, sublicense, and/or
0026 * sell copies of the Software, and to permit persons to whom the
0027 * Software is furnished to do so, subject to the following
0028 * conditions:
0029 *
0030 * The above copyright notice and this permission notice shall be
0031 * included in all copies or substantial portions of the Software.
0032 *
0033 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0034 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0035 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0036 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0037 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0038 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0039 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0040 * OTHER DEALINGS IN THE SOFTWARE.
0041 *
0042 */
0043
0044 /dts-v1/;
0045 #include "imx6q.dtsi"
0046 #include <dt-bindings/gpio/gpio.h>
0047 #include <dt-bindings/interrupt-controller/irq.h>
0048
0049 / {
0050 model = "Uniwest Evi";
0051 compatible = "uniwest,imx6q-evi", "fsl,imx6q";
0052
0053 memory@10000000 {
0054 device_type = "memory";
0055 reg = <0x10000000 0x40000000>;
0056 };
0057
0058 reg_usbh1_vbus: regulator-usbhubreset {
0059 compatible = "regulator-fixed";
0060 regulator-name = "usbh1_vbus";
0061 regulator-min-microvolt = <5000000>;
0062 regulator-max-microvolt = <5000000>;
0063 enable-active-high;
0064 startup-delay-us = <2>;
0065 pinctrl-names = "default";
0066 pinctrl-0 = <&pinctrl_usbh1_hubreset>;
0067 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
0068 };
0069
0070 reg_usb_otg_vbus: regulator-usbotgvbus {
0071 compatible = "regulator-fixed";
0072 regulator-name = "usb_otg_vbus";
0073 regulator-min-microvolt = <5000000>;
0074 regulator-max-microvolt = <5000000>;
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_usbotgvbus>;
0077 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
0078 enable-active-high;
0079 regulator-always-on;
0080 };
0081
0082 panel {
0083 compatible = "sharp,lq101k1ly04";
0084
0085 port {
0086 panel_in: endpoint {
0087 remote-endpoint = <&lvds0_out>;
0088 };
0089 };
0090 };
0091 };
0092
0093 &ecspi1 {
0094 cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
0095 pinctrl-names = "default";
0096 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
0097 status = "okay";
0098
0099 fpga: fpga@0 {
0100 compatible = "altr,fpga-passive-serial";
0101 spi-max-frequency = <20000000>;
0102 reg = <0>;
0103 pinctrl-0 = <&pinctrl_fpgaspi>;
0104 nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
0105 nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
0106 };
0107 };
0108
0109 &ecspi3 {
0110 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
0111 <&gpio4 25 GPIO_ACTIVE_LOW>,
0112 <&gpio4 26 GPIO_ACTIVE_LOW>;
0113 pinctrl-names = "default";
0114 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>;
0115 status = "okay";
0116 };
0117
0118 &ecspi5 {
0119 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
0120 <&gpio1 13 GPIO_ACTIVE_LOW>,
0121 <&gpio1 12 GPIO_ACTIVE_LOW>,
0122 <&gpio2 9 GPIO_ACTIVE_HIGH>;
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>;
0125 status = "okay";
0126
0127 eeprom: m95m02@1 {
0128 compatible = "st,m95m02", "atmel,at25";
0129 size = <262144>;
0130 pagesize = <256>;
0131 address-width = <24>;
0132 spi-max-frequency = <5000000>;
0133 reg = <1>;
0134 };
0135
0136 pb_rtc: rtc@3 {
0137 compatible = "nxp,rtc-pcf2123";
0138 spi-max-frequency = <2450000>;
0139 spi-cs-high;
0140 reg = <3>;
0141 };
0142 };
0143
0144 &fec {
0145 pinctrl-names = "default";
0146 pinctrl-0 = <&pinctrl_enet>;
0147 phy-mode = "rgmii";
0148 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
0149 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
0150 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
0151 fsl,err006687-workaround-present;
0152 status = "okay";
0153 };
0154
0155 &gpmi {
0156 pinctrl-names = "default";
0157 pinctrl-0 = <&pinctrl_gpminand>;
0158 status = "okay";
0159 };
0160
0161 &i2c2 {
0162 pinctrl-names = "default";
0163 pinctrl-0 = <&pinctrl_i2c2>;
0164 clock-frequency = <100000>;
0165 status = "okay";
0166 };
0167
0168 &i2c3 {
0169 pinctrl-names = "default", "gpio";
0170 pinctrl-0 = <&pinctrl_i2c3>;
0171 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0172 clock-frequency = <100000>;
0173 scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
0174 sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
0175 status = "okay";
0176
0177 battery: sbs-battery@b {
0178 compatible = "sbs,sbs-battery";
0179 reg = <0x0b>;
0180 sbs,poll-retry-count = <100>;
0181 sbs,i2c-retry-count = <100>;
0182 };
0183 };
0184
0185 &ldb {
0186 status = "okay";
0187
0188 lvds0: lvds-channel@0 {
0189 status = "okay";
0190
0191 port@4 {
0192 reg = <4>;
0193 lvds0_out: endpoint {
0194 remote-endpoint = <&panel_in>;
0195 };
0196 };
0197 };
0198 };
0199
0200 &ssi1 {
0201 status = "okay";
0202 };
0203
0204 &uart1 {
0205 pinctrl-names = "default";
0206 pinctrl-0 = <&pinctrl_uart1>;
0207 status = "okay";
0208 };
0209
0210 &uart2 {
0211 pinctrl-names = "default";
0212 pinctrl-0 = <&pinctrl_uart2>;
0213 status = "okay";
0214 };
0215
0216 &usbh1 {
0217 vbus-supply = <®_usbh1_vbus>;
0218 pinctrl-names = "default";
0219 pinctrl-0 = <&pinctrl_usbh1>;
0220 dr_mode = "host";
0221 disable-over-current;
0222 status = "okay";
0223 };
0224
0225 &usbotg {
0226 vbus-supply = <®_usb_otg_vbus>;
0227 pinctrl-names = "default";
0228 pinctrl-0 = <&pinctrl_usbotg>;
0229 disable-over-current;
0230 dr_mode = "otg";
0231 status = "okay";
0232 };
0233
0234 &usdhc1 {
0235 pinctrl-names = "default";
0236 pinctrl-0 = <&pinctrl_usdhc1>;
0237 non-removable;
0238 status = "okay";
0239 };
0240
0241 &weim {
0242 ranges = <0 0 0x08000000 0x08000000>;
0243 pinctrl-names = "default";
0244 pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
0245 status = "okay";
0246 };
0247
0248 &iomuxc {
0249 pinctrl-names = "default";
0250 pinctrl-0 = <&pinctrl_hog>;
0251
0252 pinctrl_hog: hoggrp {
0253 fsl,pins = <
0254 /* pwr mcu alert irq */
0255 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
0256 /* remainder ???? */
0257 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
0258 >;
0259 };
0260
0261 pinctrl_ecspi1: ecspi1grp {
0262 fsl,pins = <
0263 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
0264 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
0265 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
0266 >;
0267 };
0268
0269 pinctrl_ecspi1cs: ecspi1csgrp {
0270 fsl,pins = <
0271 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
0272 >;
0273 };
0274
0275 pinctrl_ecspi3: ecspi3grp {
0276 fsl,pins = <
0277 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068
0278 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068
0279 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068
0280 >;
0281 };
0282
0283 pinctrl_ecspi3cs: ecspi3csgrp {
0284 fsl,pins = <
0285 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
0286 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0
0287 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
0288 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
0289 >;
0290 };
0291
0292 pinctrl_ecspi5: ecspi5grp {
0293 fsl,pins = <
0294 MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1
0295 MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1
0296 MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1
0297 >;
0298 };
0299
0300 pinctrl_ecspi5cs: ecspi5csgrp {
0301 fsl,pins = <
0302 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
0303 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
0304 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
0305 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
0306 >;
0307 };
0308
0309 pinctrl_enet: enetgrp {
0310 fsl,pins = <
0311 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0312 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0313 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0314 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0315 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0316 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0317 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0318 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0319 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0320 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0321 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0322 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0323 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0324 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0325 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0326 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
0327 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
0328 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
0329 >;
0330 };
0331
0332 pinctrl_fpgaspi: fpgaspigrp {
0333 fsl,pins = <
0334 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
0335 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
0336 >;
0337 };
0338
0339 pinctrl_gpminand: gpminandgrp {
0340 fsl,pins = <
0341 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
0342 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
0343 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
0344 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
0345 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
0346 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
0347 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
0348 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
0349 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
0350 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
0351 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
0352 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
0353 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
0354 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
0355 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
0356 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
0357 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
0358 >;
0359 };
0360
0361 pinctrl_i2c2: i2c2grp {
0362 fsl,pins = <
0363 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0364 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0365 >;
0366 };
0367
0368 pinctrl_i2c3: i2c3grp {
0369 fsl,pins = <
0370 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
0371 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
0372 >;
0373 };
0374
0375 pinctrl_i2c3_gpio: i2c3gpiogrp {
0376 fsl,pins = <
0377 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
0378 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1
0379 >;
0380 };
0381
0382 pinctrl_weimcs: weimcsgrp {
0383 fsl,pins = <
0384 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
0385 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
0386 >;
0387 };
0388
0389 pinctrl_weimfpga: weimfpgagrp {
0390 fsl,pins = <
0391 /* weim misc */
0392 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
0393 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
0394 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
0395 MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1
0396 MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1
0397 MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1
0398 MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1
0399 MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1
0400 MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1
0401 /* weim data */
0402 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
0403 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
0404 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
0405 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
0406 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
0407 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
0408 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
0409 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
0410 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
0411 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
0412 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
0413 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
0414 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
0415 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
0416 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
0417 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
0418 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
0419 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
0420 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
0421 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
0422 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
0423 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
0424 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
0425 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
0426 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
0427 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
0428 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
0429 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
0430 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
0431 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
0432 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
0433 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
0434 /* weim address */
0435 MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1
0436 MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1
0437 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
0438 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
0439 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
0440 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
0441 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
0442 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
0443 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
0444 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
0445 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
0446 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
0447 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
0448 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
0449 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
0450 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
0451 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
0452 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
0453 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
0454 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
0455 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
0456 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
0457 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
0458 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
0459 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
0460 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
0461 >;
0462 };
0463
0464 pinctrl_uart1: uart1grp {
0465 fsl,pins = <
0466 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
0467 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
0468 >;
0469 };
0470
0471 pinctrl_uart2: uart2grp {
0472 fsl,pins = <
0473 MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
0474 MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
0475 MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1
0476 MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1
0477 >;
0478 };
0479
0480 pinctrl_usbh1: usbh1grp {
0481 fsl,pins = <
0482 MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0
0483 /* usbh1_b OC */
0484 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
0485 >;
0486 };
0487
0488 pinctrl_usbh1_hubreset: usbh1hubresetgrp {
0489 fsl,pins = <
0490 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
0491 >;
0492 };
0493
0494 pinctrl_usbotg: usbotggrp {
0495 fsl,pins = <
0496 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
0497 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
0498 >;
0499 };
0500
0501 pinctrl_usbotgvbus: usbotgvbusgrp {
0502 fsl,pins = <
0503 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
0504 >;
0505 };
0506
0507 pinctrl_usdhc1: usdhc1grp {
0508 fsl,pins = <
0509 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
0510 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
0511 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
0512 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
0513 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
0514 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
0515 >;
0516 };
0517 };
