0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2013 Freescale Semiconductor, Inc.
0004
0005 #include <dt-bindings/interrupt-controller/irq.h>
0006 #include "imx6dl-pinfunc.h"
0007 #include "imx6qdl.dtsi"
0008
0009 / {
0010 aliases {
0011 i2c3 = &i2c4;
0012 };
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 cpu0: cpu@0 {
0019 compatible = "arm,cortex-a9";
0020 device_type = "cpu";
0021 reg = <0>;
0022 next-level-cache = <&L2>;
0023 operating-points = <
0024 /* kHz uV */
0025 996000 1250000
0026 792000 1175000
0027 396000 1150000
0028 >;
0029 fsl,soc-operating-points = <
0030 /* ARM kHz SOC-PU uV */
0031 996000 1175000
0032 792000 1175000
0033 396000 1175000
0034 >;
0035 clock-latency = <61036>; /* two CLK32 periods */
0036 #cooling-cells = <2>;
0037 clocks = <&clks IMX6QDL_CLK_ARM>,
0038 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
0039 <&clks IMX6QDL_CLK_STEP>,
0040 <&clks IMX6QDL_CLK_PLL1_SW>,
0041 <&clks IMX6QDL_CLK_PLL1_SYS>;
0042 clock-names = "arm", "pll2_pfd2_396m", "step",
0043 "pll1_sw", "pll1_sys";
0044 arm-supply = <®_arm>;
0045 pu-supply = <®_pu>;
0046 soc-supply = <®_soc>;
0047 nvmem-cells = <&cpu_speed_grade>;
0048 nvmem-cell-names = "speed_grade";
0049 };
0050
0051 cpu@1 {
0052 compatible = "arm,cortex-a9";
0053 device_type = "cpu";
0054 reg = <1>;
0055 next-level-cache = <&L2>;
0056 operating-points = <
0057 /* kHz uV */
0058 996000 1250000
0059 792000 1175000
0060 396000 1150000
0061 >;
0062 fsl,soc-operating-points = <
0063 /* ARM kHz SOC-PU uV */
0064 996000 1175000
0065 792000 1175000
0066 396000 1175000
0067 >;
0068 clock-latency = <61036>; /* two CLK32 periods */
0069 #cooling-cells = <2>;
0070 clocks = <&clks IMX6QDL_CLK_ARM>,
0071 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
0072 <&clks IMX6QDL_CLK_STEP>,
0073 <&clks IMX6QDL_CLK_PLL1_SW>,
0074 <&clks IMX6QDL_CLK_PLL1_SYS>;
0075 clock-names = "arm", "pll2_pfd2_396m", "step",
0076 "pll1_sw", "pll1_sys";
0077 arm-supply = <®_arm>;
0078 pu-supply = <®_pu>;
0079 soc-supply = <®_soc>;
0080 };
0081 };
0082
0083 soc: soc {
0084 ocram: sram@900000 {
0085 compatible = "mmio-sram";
0086 reg = <0x00900000 0x20000>;
0087 clocks = <&clks IMX6QDL_CLK_OCRAM>;
0088 };
0089
0090 aips1: bus@2000000 {
0091 pxp: pxp@20f0000 {
0092 reg = <0x020f0000 0x4000>;
0093 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
0094 };
0095
0096 epdc: epdc@20f4000 {
0097 reg = <0x020f4000 0x4000>;
0098 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
0099 };
0100 };
0101
0102 aips2: bus@2100000 {
0103 i2c4: i2c@21f8000 {
0104 #address-cells = <1>;
0105 #size-cells = <0>;
0106 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
0107 reg = <0x021f8000 0x4000>;
0108 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
0109 clocks = <&clks IMX6DL_CLK_I2C4>;
0110 status = "disabled";
0111 };
0112 };
0113 };
0114
0115 capture-subsystem {
0116 compatible = "fsl,imx-capture-subsystem";
0117 ports = <&ipu1_csi0>, <&ipu1_csi1>;
0118 };
0119
0120 display-subsystem {
0121 compatible = "fsl,imx-display-subsystem";
0122 ports = <&ipu1_di0>, <&ipu1_di1>;
0123 };
0124 };
0125
0126 &gpio1 {
0127 gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
0128 <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
0129 <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
0130 <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
0131 <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
0132 <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
0133 <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
0134 };
0135
0136 &gpio2 {
0137 gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
0138 <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
0139 <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
0140 <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
0141 <&iomuxc 28 113 4>;
0142 };
0143
0144 &gpio3 {
0145 gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
0146 <&iomuxc 16 81 16>;
0147 };
0148
0149 &gpio4 {
0150 gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
0151 <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
0152 <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
0153 <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
0154 <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
0155 };
0156
0157 &gpio5 {
0158 gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
0159 <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
0160 <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
0161 <&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
0162 };
0163
0164 &gpio6 {
0165 gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
0166 <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
0167 <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
0168 <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
0169 <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
0170 <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
0171 };
0172
0173 &gpio7 {
0174 gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
0175 <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
0176 <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
0177 };
0178
0179 &gpr {
0180 ipu1_csi0_mux {
0181 compatible = "video-mux";
0182 mux-controls = <&mux 0>;
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185
0186 port@0 {
0187 reg = <0>;
0188
0189 ipu1_csi0_mux_from_mipi_vc0: endpoint {
0190 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
0191 };
0192 };
0193
0194 port@1 {
0195 reg = <1>;
0196
0197 ipu1_csi0_mux_from_mipi_vc1: endpoint {
0198 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
0199 };
0200 };
0201
0202 port@2 {
0203 reg = <2>;
0204
0205 ipu1_csi0_mux_from_mipi_vc2: endpoint {
0206 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
0207 };
0208 };
0209
0210 port@3 {
0211 reg = <3>;
0212
0213 ipu1_csi0_mux_from_mipi_vc3: endpoint {
0214 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
0215 };
0216 };
0217
0218 port@4 {
0219 reg = <4>;
0220
0221 ipu1_csi0_mux_from_parallel_sensor: endpoint {
0222 };
0223 };
0224
0225 port@5 {
0226 reg = <5>;
0227
0228 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
0229 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
0230 };
0231 };
0232 };
0233
0234 ipu1_csi1_mux {
0235 compatible = "video-mux";
0236 mux-controls = <&mux 1>;
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239
0240 port@0 {
0241 reg = <0>;
0242
0243 ipu1_csi1_mux_from_mipi_vc0: endpoint {
0244 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
0245 };
0246 };
0247
0248 port@1 {
0249 reg = <1>;
0250
0251 ipu1_csi1_mux_from_mipi_vc1: endpoint {
0252 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
0253 };
0254 };
0255
0256 port@2 {
0257 reg = <2>;
0258
0259 ipu1_csi1_mux_from_mipi_vc2: endpoint {
0260 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
0261 };
0262 };
0263
0264 port@3 {
0265 reg = <3>;
0266
0267 ipu1_csi1_mux_from_mipi_vc3: endpoint {
0268 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
0269 };
0270 };
0271
0272 port@4 {
0273 reg = <4>;
0274
0275 ipu1_csi1_mux_from_parallel_sensor: endpoint {
0276 };
0277 };
0278
0279 port@5 {
0280 reg = <5>;
0281
0282 ipu1_csi1_mux_to_ipu1_csi1: endpoint {
0283 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
0284 };
0285 };
0286 };
0287 };
0288
0289 &gpt {
0290 compatible = "fsl,imx6dl-gpt";
0291 };
0292
0293 &hdmi {
0294 compatible = "fsl,imx6dl-hdmi";
0295 };
0296
0297 &iomuxc {
0298 compatible = "fsl,imx6dl-iomuxc";
0299 };
0300
0301 &ipu1_csi1 {
0302 ipu1_csi1_from_ipu1_csi1_mux: endpoint {
0303 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
0304 };
0305 };
0306
0307 &ldb {
0308 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
0309 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
0310 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
0311 clock-names = "di0_pll", "di1_pll",
0312 "di0_sel", "di1_sel",
0313 "di0", "di1";
0314 };
0315
0316 &mipi_csi {
0317 port@1 {
0318 reg = <1>;
0319 #address-cells = <1>;
0320 #size-cells = <0>;
0321
0322 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
0323 reg = <0>;
0324 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
0325 };
0326
0327 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
0328 reg = <1>;
0329 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
0330 };
0331 };
0332
0333 port@2 {
0334 reg = <2>;
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337
0338 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
0339 reg = <0>;
0340 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
0341 };
0342
0343 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
0344 reg = <1>;
0345 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
0346 };
0347 };
0348
0349 port@3 {
0350 reg = <3>;
0351 #address-cells = <1>;
0352 #size-cells = <0>;
0353
0354 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
0355 reg = <0>;
0356 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
0357 };
0358
0359 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
0360 reg = <1>;
0361 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
0362 };
0363 };
0364
0365 port@4 {
0366 reg = <4>;
0367 #address-cells = <1>;
0368 #size-cells = <0>;
0369
0370 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
0371 reg = <0>;
0372 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
0373 };
0374
0375 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
0376 reg = <1>;
0377 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
0378 };
0379 };
0380 };
0381
0382 &mux {
0383 mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
0384 <0x34 0x00000038>, /* IPU_CSI1_MUX */
0385 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
0386 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
0387 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
0388 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
0389 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
0390 };
0391
0392 &vpu {
0393 compatible = "fsl,imx6dl-vpu", "cnm,coda960";
0394 };
