0001 // SPDX-License-Identifier: GPL-2.0 or MIT
0002 //
0003 // Device Tree Source for i.MX6DL based congatec QMX6
0004 // System on Module
0005 //
0006 // Copyright 2018-2021 General Electric Company
0007 // Copyright 2018-2021 Collabora
0008 // Copyright 2016 congatec AG
0009
0010 #include "imx6dl.dtsi"
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/sound/fsl-imx-audmux.h>
0013
0014 / {
0015 memory@10000000 {
0016 reg = <0x10000000 0x40000000>;
0017 };
0018
0019 reg_3p3v: 3p3v {
0020 compatible = "regulator-fixed";
0021 regulator-name = "3P3V";
0022 regulator-min-microvolt = <3300000>;
0023 regulator-max-microvolt = <3300000>;
0024 };
0025
0026 i2cmux {
0027 compatible = "i2c-mux-gpio";
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030 mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
0031 i2c-parent = <&i2c2>;
0032
0033 i2c5: i2c@0 {
0034 reg = <0>;
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037 };
0038
0039 i2c6: i2c@1 {
0040 reg = <1>;
0041 #address-cells = <1>;
0042 #size-cells = <0>;
0043 };
0044 };
0045 };
0046
0047 &audmux {
0048 pinctrl-names = "default";
0049 pinctrl-0 = <&pinctrl_audmux>;
0050
0051 audmux_ssi1 {
0052 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
0053 fsl,port-config = <
0054 (IMX_AUDMUX_V2_PTCR_TFSDIR |
0055 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) |
0056 IMX_AUDMUX_V2_PTCR_TCLKDIR |
0057 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) |
0058 IMX_AUDMUX_V2_PTCR_SYN)
0059 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6)
0060 >;
0061 };
0062
0063 audmux_aud6 {
0064 fsl,audmux-port = <MX51_AUDMUX_PORT6>;
0065 fsl,port-config = <
0066 IMX_AUDMUX_V2_PTCR_SYN
0067 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
0068 >;
0069 };
0070 };
0071
0072 &clks {
0073 clocks = <&rtc_sqw>;
0074 clock-names = "ckil";
0075 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
0076 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
0077 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
0078 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
0079 };
0080
0081 &ecspi1 {
0082 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&pinctrl_spi1>;
0085 status = "okay";
0086
0087 flash@0 {
0088 #address-cells = <1>;
0089 #size-cells = <1>;
0090 compatible = "sst,sst25vf032b", "jedec,spi-nor";
0091 spi-max-frequency = <20000000>;
0092 reg = <0>;
0093
0094 partition@0 {
0095 label = "bootloader";
0096 reg = <0x0000000 0x100000>;
0097 };
0098
0099 partition@100000 {
0100 label = "user";
0101 reg = <0x0100000 0x2fc000>;
0102 };
0103
0104 partition@3fc000 {
0105 label = "reserved";
0106 reg = <0x03fc000 0x4000>;
0107 read-only;
0108 };
0109 };
0110 };
0111
0112 &fec {
0113 pinctrl-names = "default";
0114 pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
0115 phy-mode = "rgmii-id";
0116 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
0117 fsl,magic-packet;
0118 phy-handle = <&phy0>;
0119
0120 mdio {
0121 #address-cells = <1>;
0122 #size-cells = <0>;
0123
0124 phy0: ethernet-phy@6 {
0125 reg = <6>;
0126 qca,clk-out-frequency = <125000000>;
0127 };
0128 };
0129 };
0130
0131 &i2c1 {
0132 clock-frequency = <100000>;
0133 pinctrl-names = "default", "gpio";
0134 pinctrl-0 = <&pinctrl_i2c1>;
0135 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0136 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0137 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0138 status = "okay";
0139 };
0140
0141 &i2c2 {
0142 clock-frequency = <100000>;
0143 pinctrl-names = "default", "gpio";
0144 pinctrl-0 = <&pinctrl_i2c2>;
0145 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0146 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0147 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0148 status = "okay";
0149 };
0150
0151 &i2c3 {
0152 clock-frequency = <100000>;
0153 pinctrl-names = "default", "gpio";
0154 pinctrl-0 = <&pinctrl_i2c3>;
0155 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0156 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0157 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0158 status = "okay";
0159
0160 rtc: m41t62@68 {
0161 compatible = "st,m41t62";
0162 reg = <0x68>;
0163
0164 rtc_sqw: clock {
0165 compatible = "fixed-clock";
0166 #clock-cells = <0>;
0167 clock-frequency = <32768>;
0168 };
0169 };
0170 };
0171
0172 &i2c6 {
0173 pmic@8 {
0174 compatible = "fsl,pfuze100";
0175 reg = <0x08>;
0176
0177 regulators {
0178 sw1a_reg: sw1ab {
0179 regulator-min-microvolt = <300000>;
0180 regulator-max-microvolt = <1875000>;
0181 regulator-boot-on;
0182 regulator-always-on;
0183 regulator-ramp-delay = <6250>;
0184 };
0185
0186 sw1c_reg: sw1c {
0187 regulator-min-microvolt = <300000>;
0188 regulator-max-microvolt = <1875000>;
0189 regulator-boot-on;
0190 regulator-always-on;
0191 regulator-ramp-delay = <6250>;
0192 };
0193
0194 sw2_reg: sw2 {
0195 regulator-min-microvolt = <800000>;
0196 regulator-max-microvolt = <3300000>;
0197 regulator-boot-on;
0198 regulator-always-on;
0199 };
0200
0201 sw3a_reg: sw3a {
0202 regulator-min-microvolt = <400000>;
0203 regulator-max-microvolt = <1975000>;
0204 regulator-boot-on;
0205 regulator-always-on;
0206 };
0207
0208 sw3b_reg: sw3b {
0209 regulator-min-microvolt = <400000>;
0210 regulator-max-microvolt = <1975000>;
0211 regulator-boot-on;
0212 regulator-always-on;
0213 };
0214
0215 sw4_reg: sw4 {
0216 regulator-min-microvolt = <675000>;
0217 regulator-max-microvolt = <3300000>;
0218 regulator-boot-on;
0219 regulator-always-on;
0220 };
0221
0222 swbst_reg: swbst {
0223 regulator-min-microvolt = <5000000>;
0224 regulator-max-microvolt = <5150000>;
0225 };
0226
0227 snvs_reg: vsnvs {
0228 regulator-min-microvolt = <1000000>;
0229 regulator-max-microvolt = <3000000>;
0230 regulator-boot-on;
0231 regulator-always-on;
0232 };
0233
0234 vref_reg: vrefddr {
0235 regulator-boot-on;
0236 regulator-always-on;
0237 };
0238
0239 /*
0240 * keep VGEN3, VGEN4 and VGEN5 enabled in order to
0241 * maintain backward compatibility with hw-rev. A.0
0242 */
0243 vgen3_reg: vgen3 {
0244 regulator-min-microvolt = <1800000>;
0245 regulator-max-microvolt = <3300000>;
0246 regulator-always-on;
0247 };
0248
0249 vgen4_reg: vgen4 {
0250 regulator-min-microvolt = <2500000>;
0251 regulator-max-microvolt = <2500000>;
0252 regulator-always-on;
0253 };
0254
0255 vgen5_reg: vgen5 {
0256 regulator-min-microvolt = <1800000>;
0257 regulator-max-microvolt = <3300000>;
0258 regulator-always-on;
0259 };
0260
0261 /* supply voltage for eMMC */
0262 vgen6_reg: vgen6 {
0263 regulator-min-microvolt = <1800000>;
0264 regulator-max-microvolt = <1800000>;
0265 regulator-boot-on;
0266 regulator-always-on;
0267 };
0268 };
0269 };
0270 };
0271
0272 &pcie {
0273 reset-gpio = <&gpio1 20 0>;
0274 };
0275
0276 &pwm4 {
0277 pinctrl-names = "default";
0278 pinctrl-0 = <&pinctrl_pwm4>;
0279 };
0280
0281 ®_arm {
0282 vin-supply = <&sw1a_reg>;
0283 };
0284
0285 ®_pu {
0286 vin-supply = <&sw1c_reg>;
0287 };
0288
0289 ®_soc {
0290 vin-supply = <&sw1c_reg>;
0291 };
0292
0293 &snvs_poweroff {
0294 status = "okay";
0295 };
0296
0297 &uart2 {
0298 pinctrl-names = "default";
0299 pinctrl-0 = <&pinctrl_uart2>;
0300 status = "okay";
0301 };
0302
0303 &uart3 {
0304 pinctrl-names = "default";
0305 pinctrl-0 = <&pinctrl_uart3>;
0306 status = "okay";
0307 };
0308
0309 &usbh1 {
0310 /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */
0311 vbus-supply = <®_5v>;
0312 status = "okay";
0313 };
0314
0315 &usbotg {
0316 pinctrl-names = "default";
0317 pinctrl-0 = <&pinctrl_usbotg>;
0318 };
0319
0320 &usdhc2 {
0321 /* MicroSD card slot */
0322 pinctrl-names = "default";
0323 pinctrl-0 = <&pinctrl_usdhc2>;
0324 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
0325 no-1-8-v;
0326 keep-power-in-suspend;
0327 wakeup-source;
0328 vmmc-supply = <®_3p3v>;
0329 status = "okay";
0330 };
0331
0332 &usdhc3 {
0333 /* eMMC module */
0334 pinctrl-names = "default";
0335 pinctrl-0 = <&pinctrl_usdhc3>;
0336 non-removable;
0337 bus-width = <8>;
0338 no-1-8-v;
0339 keep-power-in-suspend;
0340 wakeup-source;
0341 vmmc-supply = <®_3p3v>;
0342 status = "okay";
0343 };
0344
0345 &wdog1 {
0346 pinctrl-names = "default";
0347 pinctrl-0 = <&pinctrl_wdog>;
0348 fsl,ext-reset-output;
0349 };
0350
0351 &iomuxc {
0352 pinctrl-names = "default";
0353 pinctrl-0 = <&pinctrl_hog>;
0354
0355 qmx6mux: imx6qdl-qmx6 {
0356 pinctrl_audmux: audmuxgrp {
0357 fsl,pins = <
0358 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */
0359 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */
0360 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */
0361 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */
0362 >;
0363 };
0364
0365 /* PHY is on System on Module, Q7[3-15] have Ethernet lines */
0366 pinctrl_enet: enet {
0367 fsl,pins = <
0368 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0369 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0370 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
0371 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
0372 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
0373 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
0374 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
0375 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
0376 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0377 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
0378 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
0379 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
0380 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
0381 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
0382 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
0383 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
0384 >;
0385 };
0386
0387 pinctrl_hog: hoggrp {
0388 fsl,pins = <
0389 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */
0390 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */
0391 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */
0392 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */
0393 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */
0394 >;
0395 };
0396
0397 pinctrl_i2c1: i2c1 {
0398 fsl,pins = <
0399 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */
0400 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */
0401 >;
0402 };
0403
0404 pinctrl_i2c1_gpio: i2c1-gpio {
0405 fsl,pins = <
0406 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */
0407 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */
0408 >;
0409 };
0410
0411 pinctrl_i2c2: i2c2 {
0412 fsl,pins = <
0413 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */
0414 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */
0415 >;
0416 };
0417
0418 pinctrl_i2c2_gpio: i2c2-gpio {
0419 fsl,pins = <
0420 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */
0421 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */
0422 >;
0423 };
0424
0425 pinctrl_i2c3: i2c3 {
0426 fsl,pins = <
0427 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */
0428 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */
0429 >;
0430 };
0431
0432 pinctrl_i2c3_gpio: i2c3-gpio {
0433 fsl,pins = <
0434 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */
0435 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */
0436 >;
0437 };
0438
0439 pinctrl_phy_reset: phy-reset {
0440 fsl,pins = <
0441 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */
0442 >;
0443 };
0444
0445 pinctrl_pwm4: pwm4 {
0446 fsl,pins = <
0447 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
0448 >;
0449 };
0450
0451 pinctrl_q7_backlight_enable: q7-backlight-enable {
0452 fsl,pins = <
0453 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */
0454 >;
0455 };
0456
0457 pinctrl_q7_gpio0: q7-gpio0 {
0458 fsl,pins = <
0459 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */
0460 >;
0461 };
0462
0463 pinctrl_q7_gpio1: q7-gpio1 {
0464 fsl,pins = <
0465 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */
0466 >;
0467 };
0468
0469 pinctrl_q7_gpio2: q7-gpio2 {
0470 fsl,pins = <
0471 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */
0472 >;
0473 };
0474
0475 pinctrl_q7_gpio3: q7-gpio3 {
0476 fsl,pins = <
0477 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */
0478 >;
0479 };
0480
0481 pinctrl_q7_gpio4: q7-gpio4 {
0482 fsl,pins = <
0483 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */
0484 >;
0485 };
0486
0487 pinctrl_q7_gpio5: q7-gpio5 {
0488 fsl,pins = <
0489 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */
0490 >;
0491 };
0492
0493 pinctrl_q7_gpio6: q7-gpio6 {
0494 fsl,pins = <
0495 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */
0496 >;
0497 };
0498
0499 pinctrl_q7_gpio7: q7-gpio7 {
0500 fsl,pins = <
0501 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */
0502 >;
0503 };
0504
0505 pinctrl_q7_hda_reset: q7-hda-reset {
0506 fsl,pins = <
0507 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */
0508 >;
0509 };
0510
0511 pinctrl_q7_lcd_power: lcd-power {
0512 fsl,pins = <
0513 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */
0514 >;
0515 };
0516
0517 pinctrl_q7_sdio_power: q7-sdio-power {
0518 fsl,pins = <
0519 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */
0520 >;
0521 };
0522
0523 pinctrl_q7_sleep_button: q7-sleep-button {
0524 fsl,pins = <
0525 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */
0526 >;
0527 };
0528
0529 pinctrl_q7_spi_cs1: spi-cs1 {
0530 fsl,pins = <
0531 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */
0532 >;
0533 };
0534
0535 /* SPI1 bus does not leave System on Module */
0536 pinctrl_spi1: spi1 {
0537 fsl,pins = <
0538 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
0539 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0540 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
0541 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
0542 >;
0543 };
0544
0545 /* Debug connector on Q7 module */
0546 pinctrl_uart2: uart2 {
0547 fsl,pins = <
0548 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
0549 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
0550 >;
0551 };
0552
0553 pinctrl_uart3: uart3 {
0554 fsl,pins = <
0555 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */
0556 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */
0557 >;
0558 };
0559
0560 pinctrl_usbotg: usbotg {
0561 fsl,pins = <
0562 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */
0563 >;
0564 };
0565
0566 /* µSD card slot on Q7 module */
0567 pinctrl_usdhc2: usdhc2 {
0568 fsl,pins = <
0569 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
0570 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
0571 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
0572 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
0573 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
0574 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
0575 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */
0576 >;
0577 };
0578
0579 /* eMMC module on Q7 module */
0580 pinctrl_usdhc3: usdhc3 {
0581 fsl,pins = <
0582 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0583 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
0584 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0585 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0586 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0587 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0588 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
0589 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
0590 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
0591 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
0592 >;
0593 };
0594
0595 pinctrl_usdhc4: usdhc4 {
0596 fsl,pins = <
0597 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */
0598 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */
0599 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */
0600 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */
0601 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */
0602 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */
0603 >;
0604 };
0605
0606 pinctrl_wdog: wdog {
0607 fsl,pins = <
0608 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */
0609 >;
0610 };
0611 };
0612 };
