0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright (c) 2016 Protonic Holland
0004 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
0005 */
0006
0007 /dts-v1/;
0008 #include <dt-bindings/display/sdtv-standards.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/input/input.h>
0011 #include <dt-bindings/leds/common.h>
0012 #include <dt-bindings/media/tvp5150.h>
0013 #include <dt-bindings/sound/fsl-imx-audmux.h>
0014 #include "imx6dl.dtsi"
0015
0016 / {
0017 model = "Protonic MVT board";
0018 compatible = "prt,prtmvt", "fsl,imx6dl";
0019
0020 chosen {
0021 stdout-path = &uart4;
0022 };
0023
0024 backlight: backlight {
0025 compatible = "pwm-backlight";
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pinctrl_backlight>;
0028 pwms = <&pwm1 0 5000000 0>;
0029 brightness-levels = <0 16 64 255>;
0030 num-interpolated-steps = <16>;
0031 default-brightness-level = <1>;
0032 power-supply = <®_3v3>;
0033 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
0034 };
0035
0036 connector {
0037 compatible = "composite-video-connector";
0038 label = "Composite0";
0039 sdtv-standards = <SDTV_STD_PAL_B>;
0040
0041 port {
0042 comp0_out: endpoint {
0043 remote-endpoint = <&tvp5150_comp0_in>;
0044 };
0045 };
0046 };
0047
0048 gpio-keys {
0049 compatible = "gpio-keys";
0050 pinctrl-names = "default";
0051 pinctrl-0 = <&pinctrl_gpiokeys>;
0052 autorepeat;
0053
0054 power {
0055 label = "Power Button";
0056 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
0057 linux,code = <KEY_POWER>;
0058 wakeup-source;
0059 };
0060
0061 f1 {
0062 label = "GPIO Key F1";
0063 linux,code = <KEY_F1>;
0064 gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>;
0065 };
0066
0067 f2 {
0068 label = "GPIO Key F2";
0069 linux,code = <KEY_F2>;
0070 gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>;
0071 };
0072
0073 f3 {
0074 label = "GPIO Key F3";
0075 linux,code = <KEY_F3>;
0076 gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>;
0077 };
0078
0079 f4 {
0080 label = "GPIO Key F4";
0081 linux,code = <KEY_F4>;
0082 gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>;
0083 };
0084
0085 f5 {
0086 label = "GPIO Key F5";
0087 linux,code = <KEY_F5>;
0088 gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>;
0089 };
0090
0091 cycle {
0092 label = "GPIO Key CYCLE";
0093 linux,code = <KEY_CYCLEWINDOWS>;
0094 gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>;
0095 };
0096
0097 esc {
0098 label = "GPIO Key ESC";
0099 linux,code = <KEY_ESC>;
0100 gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>;
0101 };
0102
0103 up {
0104 label = "GPIO Key UP";
0105 linux,code = <KEY_UP>;
0106 gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>;
0107 };
0108
0109 down {
0110 label = "GPIO Key DOWN";
0111 linux,code = <KEY_DOWN>;
0112 gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>;
0113 };
0114
0115 ok {
0116 label = "GPIO Key OK";
0117 linux,code = <KEY_OK>;
0118 gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>;
0119 };
0120
0121 f6 {
0122 label = "GPIO Key F6";
0123 linux,code = <KEY_F6>;
0124 gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>;
0125 };
0126
0127 f7 {
0128 label = "GPIO Key F7";
0129 linux,code = <KEY_F7>;
0130 gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>;
0131 };
0132
0133 f8 {
0134 label = "GPIO Key F8";
0135 linux,code = <KEY_F8>;
0136 gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>;
0137 };
0138
0139 f9 {
0140 label = "GPIO Key F9";
0141 linux,code = <KEY_F9>;
0142 gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>;
0143 };
0144
0145 f10 {
0146 label = "GPIO Key F10";
0147 linux,code = <KEY_F10>;
0148 gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>;
0149 };
0150
0151 };
0152
0153 leds {
0154 compatible = "gpio-leds";
0155 pinctrl-names = "default";
0156 pinctrl-0 = <&pinctrl_leds>;
0157
0158 led-0 {
0159 label = "debug0";
0160 function = LED_FUNCTION_HEARTBEAT;
0161 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
0162 linux,default-trigger = "heartbeat";
0163 };
0164
0165 led-1 {
0166 label = "debug1";
0167 function = LED_FUNCTION_DISK;
0168 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0169 linux,default-trigger = "disk-activity";
0170 };
0171
0172 led-2 {
0173 label = "power_led";
0174 function = LED_FUNCTION_POWER;
0175 gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
0176 default-state = "on";
0177 };
0178 };
0179
0180 panel {
0181 compatible = "kyo,tcg070wvlq", "lg,lb070wv8";
0182 backlight = <&backlight>;
0183 power-supply = <®_3v3>;
0184
0185 port {
0186 panel_in: endpoint {
0187 remote-endpoint = <&lvds0_out>;
0188 };
0189 };
0190 };
0191
0192 clk50m_phy: phy-clock {
0193 compatible = "fixed-clock";
0194 #clock-cells = <0>;
0195 clock-frequency = <50000000>;
0196 };
0197
0198 reg_1v8: regulator-1v8 {
0199 compatible = "regulator-fixed";
0200 regulator-name = "1v8";
0201 regulator-min-microvolt = <1800000>;
0202 regulator-max-microvolt = <1800000>;
0203 };
0204
0205 reg_3v3: regulator-3v3 {
0206 compatible = "regulator-fixed";
0207 regulator-name = "3v3";
0208 regulator-min-microvolt = <3300000>;
0209 regulator-max-microvolt = <3300000>;
0210 };
0211
0212 reg_h1_vbus: regulator-h1-vbus {
0213 compatible = "regulator-fixed";
0214 regulator-name = "h1-vbus";
0215 regulator-min-microvolt = <5000000>;
0216 regulator-max-microvolt = <5000000>;
0217 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
0218 enable-active-high;
0219 };
0220
0221 reg_otg_vbus: regulator-otg-vbus {
0222 compatible = "regulator-fixed";
0223 regulator-name = "otg-vbus";
0224 regulator-min-microvolt = <5000000>;
0225 regulator-max-microvolt = <5000000>;
0226 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0227 enable-active-high;
0228 };
0229
0230 sound {
0231 compatible = "simple-audio-card";
0232 simple-audio-card,name = "prti6q-sgtl5000";
0233 simple-audio-card,format = "i2s";
0234 simple-audio-card,widgets =
0235 "Microphone", "Microphone Jack",
0236 "Line", "Line In Jack",
0237 "Headphone", "Headphone Jack",
0238 "Speaker", "External Speaker";
0239 simple-audio-card,routing =
0240 "MIC_IN", "Microphone Jack",
0241 "LINE_IN", "Line In Jack",
0242 "Headphone Jack", "HP_OUT",
0243 "External Speaker", "LINE_OUT";
0244
0245 simple-audio-card,cpu {
0246 sound-dai = <&ssi1>;
0247 system-clock-frequency = <0>;
0248 };
0249
0250 simple-audio-card,codec {
0251 sound-dai = <&codec>;
0252 bitclock-master;
0253 frame-master;
0254 };
0255 };
0256 };
0257
0258 &audmux {
0259 pinctrl-names = "default";
0260 pinctrl-0 = <&pinctrl_audmux>;
0261 status = "okay";
0262
0263 mux-ssi1 {
0264 fsl,audmux-port = <0>;
0265 fsl,port-config = <
0266 IMX_AUDMUX_V2_PTCR_SYN 0
0267 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
0268 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
0269 IMX_AUDMUX_V2_PTCR_TFSDIR 0
0270 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
0271 >;
0272 };
0273
0274 mux-pins3 {
0275 fsl,audmux-port = <2>;
0276 fsl,port-config = <
0277 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
0278 0 IMX_AUDMUX_V2_PDCR_TXRXEN
0279 >;
0280 };
0281 };
0282
0283 &can1 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_can1>;
0286 status = "okay";
0287 };
0288
0289 &can2 {
0290 pinctrl-names = "default";
0291 pinctrl-0 = <&pinctrl_can2>;
0292 status = "okay";
0293 };
0294
0295 &clks {
0296 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
0297 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
0298 };
0299
0300 &ecspi1 {
0301 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
0302 pinctrl-names = "default";
0303 pinctrl-0 = <&pinctrl_ecspi1>;
0304 status = "okay";
0305
0306 flash@0 {
0307 compatible = "jedec,spi-nor";
0308 reg = <0>;
0309 spi-max-frequency = <20000000>;
0310 };
0311 };
0312
0313 &fec {
0314 pinctrl-names = "default";
0315 pinctrl-0 = <&pinctrl_enet>;
0316 phy-mode = "rmii";
0317 clocks = <&clks IMX6QDL_CLK_ENET>,
0318 <&clks IMX6QDL_CLK_ENET>,
0319 <&clk50m_phy>;
0320 clock-names = "ipg", "ahb", "ptp";
0321 phy-handle = <&rmii_phy>;
0322 status = "okay";
0323
0324 mdio {
0325 #address-cells = <1>;
0326 #size-cells = <0>;
0327
0328 /* Microchip KSZ8081RNA PHY */
0329 rmii_phy: ethernet-phy@0 {
0330 reg = <0>;
0331 interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
0332 reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
0333 reset-assert-us = <10000>;
0334 reset-deassert-us = <3000>;
0335 };
0336 };
0337 };
0338
0339 &gpio1 {
0340 gpio-line-names =
0341 "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
0342 "CAM2_MIRROR", "", "", "SMBALERT",
0343 "DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
0344 "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
0345 "SD1_DATA3", "", "",
0346 "", "", "", "", "", "", "", "";
0347 };
0348
0349 &gpio2 {
0350 gpio-line-names =
0351 "", "", "", "", "", "", "", "",
0352 "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
0353 "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
0354 "", "", "", "", "", "", "", "ON_SWITCH",
0355 "POWER_LED", "", "", "", "", "", "", "";
0356 };
0357
0358 &gpio3 {
0359 gpio-line-names =
0360 "", "", "", "", "", "", "", "",
0361 "", "", "", "", "", "", "", "",
0362 "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
0363 "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ",
0364 "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
0365 "YACO_RESET";
0366 };
0367
0368 &gpio4 {
0369 gpio-line-names =
0370 "", "", "", "", "", "", "", "",
0371 "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX",
0372 "", "", "DIP1_FB", "", "", "", "", "",
0373 "CPU_LIGHT_ON", "", "ETH_RESET", "", "BL_EN",
0374 "BL_PWM", "ETH_INTRP", "";
0375 };
0376
0377 &gpio5 {
0378 gpio-line-names =
0379 "", "", "", "", "", "", "", "",
0380 "", "", "", "", "", "", "", "",
0381 "", "", "", "", "", "", "", "",
0382 "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
0383 "YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
0384 };
0385
0386 &i2c1 {
0387 clock-frequency = <100000>;
0388 pinctrl-names = "default";
0389 pinctrl-0 = <&pinctrl_i2c1>;
0390 status = "okay";
0391
0392 codec: audio-codec@a {
0393 compatible = "fsl,sgtl5000";
0394 reg = <0xa>;
0395 #sound-dai-cells = <0>;
0396 clocks = <&clks 201>;
0397 VDDA-supply = <®_3v3>;
0398 VDDIO-supply = <®_3v3>;
0399 VDDD-supply = <®_1v8>;
0400 };
0401
0402 video@5c {
0403 compatible = "ti,tvp5150";
0404 reg = <0x5c>;
0405 #address-cells = <1>;
0406 #size-cells = <0>;
0407
0408 port@0 {
0409 reg = <0>;
0410
0411 tvp5150_comp0_in: endpoint {
0412 remote-endpoint = <&comp0_out>;
0413 };
0414 };
0415
0416 /* Output port 2 is video output pad */
0417 port@2 {
0418 reg = <2>;
0419 tvp5151_to_ipu1_csi0_mux: endpoint {
0420 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
0421 };
0422 };
0423 };
0424
0425 gpio_pca: gpio@74 {
0426 compatible = "nxp,pca9539";
0427 reg = <0x74>;
0428 pinctrl-names = "default";
0429 pinctrl-0 = <&pinctrl_pca9539>;
0430 interrupt-parent = <&gpio4>;
0431 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
0432 gpio-controller;
0433 #gpio-cells = <2>;
0434 };
0435
0436 /* additional i2c devices are added automatically by the boot loader */
0437 };
0438
0439 &i2c3 {
0440 clock-frequency = <100000>;
0441 pinctrl-names = "default";
0442 pinctrl-0 = <&pinctrl_i2c3>;
0443 status = "okay";
0444
0445 adc@49 {
0446 compatible = "ti,ads1015";
0447 reg = <0x49>;
0448 #address-cells = <1>;
0449 #size-cells = <0>;
0450
0451 channel@4 {
0452 reg = <4>;
0453 ti,gain = <3>;
0454 ti,datarate = <3>;
0455 };
0456
0457 channel@5 {
0458 reg = <5>;
0459 ti,gain = <3>;
0460 ti,datarate = <3>;
0461 };
0462
0463 channel@6 {
0464 reg = <6>;
0465 ti,gain = <3>;
0466 ti,datarate = <3>;
0467 };
0468
0469 channel@7 {
0470 reg = <7>;
0471 ti,gain = <3>;
0472 ti,datarate = <3>;
0473 };
0474 };
0475
0476 rtc@51 {
0477 compatible = "nxp,pcf8563";
0478 reg = <0x51>;
0479 };
0480
0481 temperature-sensor@70 {
0482 compatible = "ti,tmp103";
0483 reg = <0x70>;
0484 };
0485 };
0486
0487 &ipu1_csi0 {
0488 pinctrl-names = "default";
0489 pinctrl-0 = <&pinctrl_ipu1_csi0>;
0490 status = "okay";
0491 };
0492
0493 &ipu1_csi0_mux_from_parallel_sensor {
0494 remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
0495 };
0496
0497 &ldb {
0498 status = "okay";
0499
0500 lvds-channel@0 {
0501 status = "okay";
0502
0503 port@4 {
0504 reg = <4>;
0505
0506 lvds0_out: endpoint {
0507 remote-endpoint = <&panel_in>;
0508 };
0509 };
0510 };
0511 };
0512
0513 &pcie {
0514 status = "okay";
0515 };
0516
0517 &pwm1 {
0518 pinctrl-names = "default";
0519 pinctrl-0 = <&pinctrl_pwm1>;
0520 status = "okay";
0521 };
0522
0523 &ssi1 {
0524 #sound-dai-cells = <0>;
0525 fsl,mode = "ac97-slave";
0526 status = "okay";
0527 };
0528
0529 &uart1 {
0530 pinctrl-names = "default";
0531 pinctrl-0 = <&pinctrl_uart1>;
0532 status = "okay";
0533 };
0534
0535 &uart2 {
0536 pinctrl-names = "default";
0537 pinctrl-0 = <&pinctrl_uart2>;
0538 status = "okay";
0539 };
0540
0541 &uart3 {
0542 pinctrl-names = "default";
0543 pinctrl-0 = <&pinctrl_uart3>;
0544 status = "okay";
0545 };
0546
0547 &uart4 {
0548 pinctrl-names = "default";
0549 pinctrl-0 = <&pinctrl_uart4>;
0550 status = "okay";
0551 };
0552
0553 &uart5 {
0554 pinctrl-names = "default";
0555 pinctrl-0 = <&pinctrl_uart5>;
0556 status = "okay";
0557 };
0558
0559 &usbh1 {
0560 vbus-supply = <®_h1_vbus>;
0561 pinctrl-names = "default";
0562 phy_type = "utmi";
0563 dr_mode = "host";
0564 status = "okay";
0565 };
0566
0567 &usbotg {
0568 vbus-supply = <®_otg_vbus>;
0569 pinctrl-names = "default";
0570 pinctrl-0 = <&pinctrl_usbotg>;
0571 phy_type = "utmi";
0572 dr_mode = "host";
0573 disable-over-current;
0574 status = "okay";
0575 };
0576
0577 &usdhc1 {
0578 pinctrl-names = "default";
0579 pinctrl-0 = <&pinctrl_usdhc1>;
0580 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0581 no-1-8-v;
0582 disable-wp;
0583 cap-sd-highspeed;
0584 no-mmc;
0585 no-sdio;
0586 status = "okay";
0587 };
0588
0589 &usdhc3 {
0590 pinctrl-names = "default";
0591 pinctrl-0 = <&pinctrl_usdhc3>;
0592 bus-width = <8>;
0593 no-1-8-v;
0594 non-removable;
0595 no-sd;
0596 no-sdio;
0597 status = "okay";
0598 };
0599
0600 &iomuxc {
0601 pinctrl-names = "default";
0602 pinctrl-0 = <&pinctrl_hog>;
0603
0604 pinctrl_audmux: audmuxgrp {
0605 fsl,pins = <
0606 /* SGTL5000 sys_mclk */
0607 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
0608 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
0609 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
0610 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
0611 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
0612 >;
0613 };
0614
0615 pinctrl_backlight: backlightgrp {
0616 fsl,pins = <
0617 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
0618 >;
0619 };
0620
0621 pinctrl_can1: can1grp {
0622 fsl,pins = <
0623 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
0624 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
0625 /* CAN1_SR */
0626 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
0627 /* CAN1_TERM */
0628 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088
0629 >;
0630 };
0631
0632 pinctrl_can2: can2grp {
0633 fsl,pins = <
0634 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
0635 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
0636 /* CAN2_SR */
0637 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
0638 >;
0639 };
0640
0641 pinctrl_ecspi1: ecspi1grp {
0642 fsl,pins = <
0643 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
0644 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
0645 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
0646 /* CS */
0647 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
0648 >;
0649 };
0650
0651 pinctrl_enet: enetgrp {
0652 fsl,pins = <
0653 /* MX6QDL_ENET_PINGRP4 */
0654 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0655 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0656 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
0657 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
0658 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
0659 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
0660 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
0661 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
0662 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
0663 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
0664 /* Phy reset */
0665 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
0666 /* nINTRP */
0667 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0
0668 >;
0669 };
0670
0671 pinctrl_gpiokeys: gpiokeygrp {
0672 fsl,pins = <
0673 /* nON_SWITCH */
0674 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
0675 >;
0676 };
0677
0678 pinctrl_hog: hoggrp {
0679 fsl,pins = <
0680 /* ITU656_nRESET */
0681 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
0682 /* CAM1_MIRROR */
0683 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0
0684 /* CAM2_MIRROR */
0685 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
0686 /* CAM_nDETECT */
0687 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
0688 /* ISB_IN1 */
0689 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
0690 /* ISB_nIN2 */
0691 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
0692 /* WARN_LIGHT */
0693 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0
0694 /* ON2_FB */
0695 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0
0696 /* YACO_nIRQ */
0697 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
0698 /* YACO_BOOT0 */
0699 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0
0700 /* YACO_nRESET */
0701 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
0702 /* FORCE_ON1 */
0703 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
0704 /* AUDIO_nRESET */
0705 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
0706 /* ITU656_nPDN */
0707 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
0708
0709 /* HW revision detect */
0710 /* REV_ID0 */
0711 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
0712 /* REV_ID1 */
0713 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
0714 /* REV_ID2 */
0715 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
0716 /* REV_ID3 */
0717 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
0718 /* REV_ID4 */
0719 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
0720
0721 /* New in HW revision 1 */
0722 /* ON1_FB */
0723 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
0724 /* DIP1_FB */
0725 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
0726 >;
0727 };
0728
0729 pinctrl_i2c1: i2c1grp {
0730 fsl,pins = <
0731 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
0732 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
0733 >;
0734 };
0735
0736 pinctrl_i2c3: i2c3grp {
0737 fsl,pins = <
0738 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
0739 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
0740 >;
0741 };
0742
0743 pinctrl_ipu1_csi0: ipu1csi0grp {
0744 fsl,pins = <
0745 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
0746 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
0747 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
0748 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
0749 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
0750 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
0751 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
0752 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
0753 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
0754 >;
0755 };
0756
0757 pinctrl_leds: ledsgrp {
0758 fsl,pins = <
0759 /* DEBUG0 */
0760 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0
0761 /* DEBUG1 */
0762 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
0763 /* POWER_LED */
0764 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
0765 >;
0766 };
0767
0768 pinctrl_pca9539: pca9539 {
0769 fsl,pins = <
0770 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
0771 >;
0772 };
0773
0774 pinctrl_pwm1: pwm1grp {
0775 fsl,pins = <
0776 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
0777 >;
0778 };
0779
0780 /* YaCO AUX Uart */
0781 pinctrl_uart1: uart1grp {
0782 fsl,pins = <
0783 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
0784 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
0785 >;
0786 };
0787
0788 pinctrl_uart2: uart2grp {
0789 fsl,pins = <
0790 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
0791 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
0792 >;
0793 };
0794
0795 /* YaCO Touchscreen UART */
0796 pinctrl_uart3: uart3grp {
0797 fsl,pins = <
0798 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
0799 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
0800 >;
0801 };
0802
0803 pinctrl_uart4: uart4grp {
0804 fsl,pins = <
0805 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
0806 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
0807 >;
0808 };
0809
0810 pinctrl_uart5: uart5grp {
0811 fsl,pins = <
0812 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
0813 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
0814 >;
0815 };
0816
0817 pinctrl_usbotg: usbotggrp {
0818 fsl,pins = <
0819 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
0820 /* power enable, high active */
0821 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
0822 >;
0823 };
0824
0825 pinctrl_usdhc1: usdhc1grp {
0826 fsl,pins = <
0827 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
0828 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
0829 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
0830 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
0831 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
0832 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
0833 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
0834 >;
0835 };
0836
0837 pinctrl_usdhc3: usdhc3grp {
0838 fsl,pins = <
0839 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
0840 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
0841 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
0842 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
0843 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
0844 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
0845 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
0846 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
0847 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
0848 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
0849 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
0850 >;
0851 };
0852 };
