OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2011 Freescale Semiconductor, Inc.
0004 // Copyright 2011 Linaro Ltd.
0005
0006 #include "imx53-pinfunc.h"
0007 #include <dt-bindings/clock/imx5-clock.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/input.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 /*
0016 * The decompressor and also some bootloaders rely on a
0017 * pre-existing /chosen node to be available to insert the
0018 * command line and merge other ATAGS info.
0019 */
0020 chosen {};
0021
0022 aliases {
0023 ethernet0 = &fec;
0024 gpio0 = &gpio1;
0025 gpio1 = &gpio2;
0026 gpio2 = &gpio3;
0027 gpio3 = &gpio4;
0028 gpio4 = &gpio5;
0029 gpio5 = &gpio6;
0030 gpio6 = &gpio7;
0031 i2c0 = &i2c1;
0032 i2c1 = &i2c2;
0033 i2c2 = &i2c3;
0034 ipu0 = &ipu;
0035 mmc0 = &esdhc1;
0036 mmc1 = &esdhc2;
0037 mmc2 = &esdhc3;
0038 mmc3 = &esdhc4;
0039 serial0 = &uart1;
0040 serial1 = &uart2;
0041 serial2 = &uart3;
0042 serial3 = &uart4;
0043 serial4 = &uart5;
0044 spi0 = &ecspi1;
0045 spi1 = &ecspi2;
0046 spi2 = &cspi;
0047 };
0048
0049 cpus {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052 cpu0: cpu@0 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a8";
0055 reg = <0x0>;
0056 clocks = <&clks IMX5_CLK_ARM>;
0057 clock-latency = <61036>;
0058 voltage-tolerance = <5>;
0059 operating-points = <
0060 /* kHz */
0061 166666 850000
0062 400000 900000
0063 800000 1050000
0064 1000000 1200000
0065 1200000 1300000
0066 >;
0067 };
0068 };
0069
0070 display-subsystem {
0071 compatible = "fsl,imx-display-subsystem";
0072 ports = <&ipu_di0>, <&ipu_di1>;
0073 };
0074
0075 capture_subsystem {
0076 compatible = "fsl,imx-capture-subsystem";
0077 ports = <&ipu_csi0>, <&ipu_csi1>;
0078 };
0079
0080 tzic: tz-interrupt-controller@fffc000 {
0081 compatible = "fsl,imx53-tzic", "fsl,tzic";
0082 interrupt-controller;
0083 #interrupt-cells = <1>;
0084 reg = <0x0fffc000 0x4000>;
0085 };
0086
0087 clocks {
0088 ckil {
0089 compatible = "fixed-clock";
0090 #clock-cells = <0>;
0091 clock-frequency = <32768>;
0092 };
0093
0094 ckih1 {
0095 compatible = "fixed-clock";
0096 #clock-cells = <0>;
0097 clock-frequency = <22579200>;
0098 };
0099
0100 ckih2 {
0101 compatible = "fixed-clock";
0102 #clock-cells = <0>;
0103 clock-frequency = <0>;
0104 };
0105
0106 osc {
0107 compatible = "fixed-clock";
0108 #clock-cells = <0>;
0109 clock-frequency = <24000000>;
0110 };
0111 };
0112
0113 pmu: pmu {
0114 compatible = "arm,cortex-a8-pmu";
0115 interrupt-parent = <&tzic>;
0116 interrupts = <77>;
0117 };
0118
0119 usbphy0: usbphy-0 {
0120 compatible = "usb-nop-xceiv";
0121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
0122 clock-names = "main_clk";
0123 #phy-cells = <0>;
0124 status = "okay";
0125 };
0126
0127 usbphy1: usbphy-1 {
0128 compatible = "usb-nop-xceiv";
0129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
0130 clock-names = "main_clk";
0131 #phy-cells = <0>;
0132 status = "okay";
0133 };
0134
0135 soc: soc {
0136 #address-cells = <1>;
0137 #size-cells = <1>;
0138 compatible = "simple-bus";
0139 interrupt-parent = <&tzic>;
0140 ranges;
0141
0142 sata: sata@10000000 {
0143 compatible = "fsl,imx53-ahci";
0144 reg = <0x10000000 0x1000>;
0145 interrupts = <28>;
0146 clocks = <&clks IMX5_CLK_SATA_GATE>,
0147 <&clks IMX5_CLK_SATA_REF>,
0148 <&clks IMX5_CLK_AHB>;
0149 clock-names = "sata", "sata_ref", "ahb";
0150 status = "disabled";
0151 };
0152
0153 ipu: ipu@18000000 {
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156 compatible = "fsl,imx53-ipu";
0157 reg = <0x18000000 0x08000000>;
0158 interrupts = <11 10>;
0159 clocks = <&clks IMX5_CLK_IPU_GATE>,
0160 <&clks IMX5_CLK_IPU_DI0_GATE>,
0161 <&clks IMX5_CLK_IPU_DI1_GATE>;
0162 clock-names = "bus", "di0", "di1";
0163 resets = <&src 2>;
0164
0165 ipu_csi0: port@0 {
0166 reg = <0>;
0167
0168 ipu_csi0_from_parallel_sensor: endpoint {
0169 };
0170 };
0171
0172 ipu_csi1: port@1 {
0173 reg = <1>;
0174
0175 ipu_csi1_from_parallel_sensor: endpoint {
0176 };
0177 };
0178
0179 ipu_di0: port@2 {
0180 #address-cells = <1>;
0181 #size-cells = <0>;
0182 reg = <2>;
0183
0184 ipu_di0_disp0: endpoint@0 {
0185 reg = <0>;
0186 };
0187
0188 ipu_di0_lvds0: endpoint@1 {
0189 reg = <1>;
0190 remote-endpoint = <&lvds0_in>;
0191 };
0192 };
0193
0194 ipu_di1: port@3 {
0195 #address-cells = <1>;
0196 #size-cells = <0>;
0197 reg = <3>;
0198
0199 ipu_di1_disp1: endpoint@0 {
0200 reg = <0>;
0201 };
0202
0203 ipu_di1_lvds1: endpoint@1 {
0204 reg = <1>;
0205 remote-endpoint = <&lvds1_in>;
0206 };
0207
0208 ipu_di1_tve: endpoint@2 {
0209 reg = <2>;
0210 remote-endpoint = <&tve_in>;
0211 };
0212 };
0213 };
0214
0215 gpu: gpu@30000000 {
0216 compatible = "amd,imageon-200.0", "amd,imageon";
0217 reg = <0x30000000 0x20000>;
0218 reg-names = "kgsl_3d0_reg_memory";
0219 interrupts = <12>;
0220 interrupt-names = "kgsl_3d0_irq";
0221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
0222 clock-names = "core_clk", "mem_iface_clk";
0223 };
0224
0225 aips1: bus@50000000 { /* AIPS1 */
0226 compatible = "fsl,aips-bus", "simple-bus";
0227 #address-cells = <1>;
0228 #size-cells = <1>;
0229 reg = <0x50000000 0x10000000>;
0230 ranges;
0231
0232 spba-bus@50000000 {
0233 compatible = "fsl,spba-bus", "simple-bus";
0234 #address-cells = <1>;
0235 #size-cells = <1>;
0236 reg = <0x50000000 0x40000>;
0237 ranges;
0238
0239 esdhc1: mmc@50004000 {
0240 compatible = "fsl,imx53-esdhc";
0241 reg = <0x50004000 0x4000>;
0242 interrupts = <1>;
0243 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
0244 <&clks IMX5_CLK_DUMMY>,
0245 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
0246 clock-names = "ipg", "ahb", "per";
0247 bus-width = <4>;
0248 status = "disabled";
0249 };
0250
0251 esdhc2: mmc@50008000 {
0252 compatible = "fsl,imx53-esdhc";
0253 reg = <0x50008000 0x4000>;
0254 interrupts = <2>;
0255 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
0256 <&clks IMX5_CLK_DUMMY>,
0257 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
0258 clock-names = "ipg", "ahb", "per";
0259 bus-width = <4>;
0260 status = "disabled";
0261 };
0262
0263 uart3: serial@5000c000 {
0264 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
0265 reg = <0x5000c000 0x4000>;
0266 interrupts = <33>;
0267 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
0268 <&clks IMX5_CLK_UART3_PER_GATE>;
0269 clock-names = "ipg", "per";
0270 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
0271 dma-names = "rx", "tx";
0272 status = "disabled";
0273 };
0274
0275 ecspi1: spi@50010000 {
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
0279 reg = <0x50010000 0x4000>;
0280 interrupts = <36>;
0281 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
0282 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
0283 clock-names = "ipg", "per";
0284 status = "disabled";
0285 };
0286
0287 ssi2: ssi@50014000 {
0288 #sound-dai-cells = <0>;
0289 compatible = "fsl,imx53-ssi",
0290 "fsl,imx51-ssi",
0291 "fsl,imx21-ssi";
0292 reg = <0x50014000 0x4000>;
0293 interrupts = <30>;
0294 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
0295 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
0296 clock-names = "ipg", "baud";
0297 dmas = <&sdma 24 1 0>,
0298 <&sdma 25 1 0>;
0299 dma-names = "rx", "tx";
0300 fsl,fifo-depth = <15>;
0301 status = "disabled";
0302 };
0303
0304 esdhc3: mmc@50020000 {
0305 compatible = "fsl,imx53-esdhc";
0306 reg = <0x50020000 0x4000>;
0307 interrupts = <3>;
0308 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
0309 <&clks IMX5_CLK_DUMMY>,
0310 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
0311 clock-names = "ipg", "ahb", "per";
0312 bus-width = <4>;
0313 status = "disabled";
0314 };
0315
0316 esdhc4: mmc@50024000 {
0317 compatible = "fsl,imx53-esdhc";
0318 reg = <0x50024000 0x4000>;
0319 interrupts = <4>;
0320 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
0321 <&clks IMX5_CLK_DUMMY>,
0322 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
0323 clock-names = "ipg", "ahb", "per";
0324 bus-width = <4>;
0325 status = "disabled";
0326 };
0327 };
0328
0329 aipstz1: bridge@53f00000 {
0330 compatible = "fsl,imx53-aipstz";
0331 reg = <0x53f00000 0x60>;
0332 };
0333
0334 usbotg: usb@53f80000 {
0335 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
0336 reg = <0x53f80000 0x0200>;
0337 interrupts = <18>;
0338 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0339 fsl,usbmisc = <&usbmisc 0>;
0340 fsl,usbphy = <&usbphy0>;
0341 status = "disabled";
0342 };
0343
0344 usbh1: usb@53f80200 {
0345 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
0346 reg = <0x53f80200 0x0200>;
0347 interrupts = <14>;
0348 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0349 fsl,usbmisc = <&usbmisc 1>;
0350 fsl,usbphy = <&usbphy1>;
0351 dr_mode = "host";
0352 status = "disabled";
0353 };
0354
0355 usbh2: usb@53f80400 {
0356 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
0357 reg = <0x53f80400 0x0200>;
0358 interrupts = <16>;
0359 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0360 fsl,usbmisc = <&usbmisc 2>;
0361 dr_mode = "host";
0362 status = "disabled";
0363 };
0364
0365 usbh3: usb@53f80600 {
0366 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
0367 reg = <0x53f80600 0x0200>;
0368 interrupts = <17>;
0369 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0370 fsl,usbmisc = <&usbmisc 3>;
0371 dr_mode = "host";
0372 status = "disabled";
0373 };
0374
0375 usbmisc: usbmisc@53f80800 {
0376 #index-cells = <1>;
0377 compatible = "fsl,imx53-usbmisc";
0378 reg = <0x53f80800 0x200>;
0379 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0380 };
0381
0382 gpio1: gpio@53f84000 {
0383 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
0384 reg = <0x53f84000 0x4000>;
0385 interrupts = <50 51>;
0386 gpio-controller;
0387 #gpio-cells = <2>;
0388 interrupt-controller;
0389 #interrupt-cells = <2>;
0390 };
0391
0392 gpio2: gpio@53f88000 {
0393 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
0394 reg = <0x53f88000 0x4000>;
0395 interrupts = <52 53>;
0396 gpio-controller;
0397 #gpio-cells = <2>;
0398 interrupt-controller;
0399 #interrupt-cells = <2>;
0400 };
0401
0402 gpio3: gpio@53f8c000 {
0403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
0404 reg = <0x53f8c000 0x4000>;
0405 interrupts = <54 55>;
0406 gpio-controller;
0407 #gpio-cells = <2>;
0408 interrupt-controller;
0409 #interrupt-cells = <2>;
0410 };
0411
0412 gpio4: gpio@53f90000 {
0413 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
0414 reg = <0x53f90000 0x4000>;
0415 interrupts = <56 57>;
0416 gpio-controller;
0417 #gpio-cells = <2>;
0418 interrupt-controller;
0419 #interrupt-cells = <2>;
0420 };
0421
0422 kpp: kpp@53f94000 {
0423 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
0424 reg = <0x53f94000 0x4000>;
0425 interrupts = <60>;
0426 clocks = <&clks IMX5_CLK_DUMMY>;
0427 status = "disabled";
0428 };
0429
0430 wdog1: watchdog@53f98000 {
0431 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
0432 reg = <0x53f98000 0x4000>;
0433 interrupts = <58>;
0434 clocks = <&clks IMX5_CLK_DUMMY>;
0435 };
0436
0437 wdog2: watchdog@53f9c000 {
0438 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
0439 reg = <0x53f9c000 0x4000>;
0440 interrupts = <59>;
0441 clocks = <&clks IMX5_CLK_DUMMY>;
0442 status = "disabled";
0443 };
0444
0445 gpt: timer@53fa0000 {
0446 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
0447 reg = <0x53fa0000 0x4000>;
0448 interrupts = <39>;
0449 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
0450 <&clks IMX5_CLK_GPT_HF_GATE>;
0451 clock-names = "ipg", "per";
0452 };
0453
0454 srtc: rtc@53fa4000 {
0455 compatible = "fsl,imx53-rtc";
0456 reg = <0x53fa4000 0x4000>;
0457 interrupts = <24>;
0458 clocks = <&clks IMX5_CLK_SRTC_GATE>;
0459 };
0460
0461 iomuxc: iomuxc@53fa8000 {
0462 compatible = "fsl,imx53-iomuxc";
0463 reg = <0x53fa8000 0x4000>;
0464 };
0465
0466 gpr: iomuxc-gpr@53fa8000 {
0467 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
0468 reg = <0x53fa8000 0xc>;
0469 };
0470
0471 ldb: ldb@53fa8008 {
0472 #address-cells = <1>;
0473 #size-cells = <0>;
0474 compatible = "fsl,imx53-ldb";
0475 reg = <0x53fa8008 0x4>;
0476 gpr = <&gpr>;
0477 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
0478 <&clks IMX5_CLK_LDB_DI1_SEL>,
0479 <&clks IMX5_CLK_IPU_DI0_SEL>,
0480 <&clks IMX5_CLK_IPU_DI1_SEL>,
0481 <&clks IMX5_CLK_LDB_DI0_GATE>,
0482 <&clks IMX5_CLK_LDB_DI1_GATE>;
0483 clock-names = "di0_pll", "di1_pll",
0484 "di0_sel", "di1_sel",
0485 "di0", "di1";
0486 status = "disabled";
0487
0488 lvds-channel@0 {
0489 #address-cells = <1>;
0490 #size-cells = <0>;
0491 reg = <0>;
0492 status = "disabled";
0493
0494 port@0 {
0495 reg = <0>;
0496
0497 lvds0_in: endpoint {
0498 remote-endpoint = <&ipu_di0_lvds0>;
0499 };
0500 };
0501
0502 port@2 {
0503 reg = <2>;
0504 };
0505 };
0506
0507 lvds-channel@1 {
0508 #address-cells = <1>;
0509 #size-cells = <0>;
0510 reg = <1>;
0511 status = "disabled";
0512
0513 port@1 {
0514 reg = <1>;
0515
0516 lvds1_in: endpoint {
0517 remote-endpoint = <&ipu_di1_lvds1>;
0518 };
0519 };
0520
0521 port@2 {
0522 reg = <2>;
0523 };
0524 };
0525 };
0526
0527 pwm1: pwm@53fb4000 {
0528 #pwm-cells = <3>;
0529 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
0530 reg = <0x53fb4000 0x4000>;
0531 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
0532 <&clks IMX5_CLK_PWM1_HF_GATE>;
0533 clock-names = "ipg", "per";
0534 interrupts = <61>;
0535 };
0536
0537 pwm2: pwm@53fb8000 {
0538 #pwm-cells = <3>;
0539 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
0540 reg = <0x53fb8000 0x4000>;
0541 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
0542 <&clks IMX5_CLK_PWM2_HF_GATE>;
0543 clock-names = "ipg", "per";
0544 interrupts = <94>;
0545 };
0546
0547 uart1: serial@53fbc000 {
0548 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
0549 reg = <0x53fbc000 0x4000>;
0550 interrupts = <31>;
0551 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
0552 <&clks IMX5_CLK_UART1_PER_GATE>;
0553 clock-names = "ipg", "per";
0554 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
0555 dma-names = "rx", "tx";
0556 status = "disabled";
0557 };
0558
0559 uart2: serial@53fc0000 {
0560 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
0561 reg = <0x53fc0000 0x4000>;
0562 interrupts = <32>;
0563 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
0564 <&clks IMX5_CLK_UART2_PER_GATE>;
0565 clock-names = "ipg", "per";
0566 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
0567 dma-names = "rx", "tx";
0568 status = "disabled";
0569 };
0570
0571 can1: can@53fc8000 {
0572 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
0573 reg = <0x53fc8000 0x4000>;
0574 interrupts = <82>;
0575 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
0576 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
0577 clock-names = "ipg", "per";
0578 status = "disabled";
0579 };
0580
0581 can2: can@53fcc000 {
0582 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
0583 reg = <0x53fcc000 0x4000>;
0584 interrupts = <83>;
0585 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
0586 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
0587 clock-names = "ipg", "per";
0588 status = "disabled";
0589 };
0590
0591 src: reset-controller@53fd0000 {
0592 compatible = "fsl,imx53-src", "fsl,imx51-src";
0593 reg = <0x53fd0000 0x4000>;
0594 interrupts = <75>;
0595 #reset-cells = <1>;
0596 };
0597
0598 clks: ccm@53fd4000{
0599 compatible = "fsl,imx53-ccm";
0600 reg = <0x53fd4000 0x4000>;
0601 interrupts = <0 71 0x04 0 72 0x04>;
0602 #clock-cells = <1>;
0603 };
0604
0605 gpio5: gpio@53fdc000 {
0606 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
0607 reg = <0x53fdc000 0x4000>;
0608 interrupts = <103 104>;
0609 gpio-controller;
0610 #gpio-cells = <2>;
0611 interrupt-controller;
0612 #interrupt-cells = <2>;
0613 };
0614
0615 gpio6: gpio@53fe0000 {
0616 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
0617 reg = <0x53fe0000 0x4000>;
0618 interrupts = <105 106>;
0619 gpio-controller;
0620 #gpio-cells = <2>;
0621 interrupt-controller;
0622 #interrupt-cells = <2>;
0623 };
0624
0625 gpio7: gpio@53fe4000 {
0626 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
0627 reg = <0x53fe4000 0x4000>;
0628 interrupts = <107 108>;
0629 gpio-controller;
0630 #gpio-cells = <2>;
0631 interrupt-controller;
0632 #interrupt-cells = <2>;
0633 };
0634
0635 i2c3: i2c@53fec000 {
0636 #address-cells = <1>;
0637 #size-cells = <0>;
0638 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
0639 reg = <0x53fec000 0x4000>;
0640 interrupts = <64>;
0641 clocks = <&clks IMX5_CLK_I2C3_GATE>;
0642 status = "disabled";
0643 };
0644
0645 uart4: serial@53ff0000 {
0646 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
0647 reg = <0x53ff0000 0x4000>;
0648 interrupts = <13>;
0649 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
0650 <&clks IMX5_CLK_UART4_PER_GATE>;
0651 clock-names = "ipg", "per";
0652 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
0653 dma-names = "rx", "tx";
0654 status = "disabled";
0655 };
0656 };
0657
0658 aips2: bus@60000000 { /* AIPS2 */
0659 compatible = "fsl,aips-bus", "simple-bus";
0660 #address-cells = <1>;
0661 #size-cells = <1>;
0662 reg = <0x60000000 0x10000000>;
0663 ranges;
0664
0665 aipstz2: bridge@63f00000 {
0666 compatible = "fsl,imx53-aipstz";
0667 reg = <0x63f00000 0x60>;
0668 };
0669
0670 iim: efuse@63f98000 {
0671 compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon";
0672 reg = <0x63f98000 0x4000>;
0673 interrupts = <69>;
0674 clocks = <&clks IMX5_CLK_IIM_GATE>;
0675 };
0676
0677 uart5: serial@63f90000 {
0678 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
0679 reg = <0x63f90000 0x4000>;
0680 interrupts = <86>;
0681 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
0682 <&clks IMX5_CLK_UART5_PER_GATE>;
0683 clock-names = "ipg", "per";
0684 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
0685 dma-names = "rx", "tx";
0686 status = "disabled";
0687 };
0688
0689 tigerp: tigerp@63fa0000 {
0690 compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
0691 reg = <0x63fa0000 0x28>;
0692 };
0693
0694 owire: owire@63fa4000 {
0695 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
0696 reg = <0x63fa4000 0x4000>;
0697 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
0698 status = "disabled";
0699 };
0700
0701 ecspi2: spi@63fac000 {
0702 #address-cells = <1>;
0703 #size-cells = <0>;
0704 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
0705 reg = <0x63fac000 0x4000>;
0706 interrupts = <37>;
0707 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
0708 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
0709 clock-names = "ipg", "per";
0710 status = "disabled";
0711 };
0712
0713 sdma: sdma@63fb0000 {
0714 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
0715 reg = <0x63fb0000 0x4000>;
0716 interrupts = <6>;
0717 clocks = <&clks IMX5_CLK_SDMA_GATE>,
0718 <&clks IMX5_CLK_AHB>;
0719 clock-names = "ipg", "ahb";
0720 #dma-cells = <3>;
0721 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
0722 };
0723
0724 cspi: spi@63fc0000 {
0725 #address-cells = <1>;
0726 #size-cells = <0>;
0727 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
0728 reg = <0x63fc0000 0x4000>;
0729 interrupts = <38>;
0730 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
0731 <&clks IMX5_CLK_CSPI_IPG_GATE>;
0732 clock-names = "ipg", "per";
0733 status = "disabled";
0734 };
0735
0736 i2c2: i2c@63fc4000 {
0737 #address-cells = <1>;
0738 #size-cells = <0>;
0739 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
0740 reg = <0x63fc4000 0x4000>;
0741 interrupts = <63>;
0742 clocks = <&clks IMX5_CLK_I2C2_GATE>;
0743 status = "disabled";
0744 };
0745
0746 i2c1: i2c@63fc8000 {
0747 #address-cells = <1>;
0748 #size-cells = <0>;
0749 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
0750 reg = <0x63fc8000 0x4000>;
0751 interrupts = <62>;
0752 clocks = <&clks IMX5_CLK_I2C1_GATE>;
0753 status = "disabled";
0754 };
0755
0756 ssi1: ssi@63fcc000 {
0757 #sound-dai-cells = <0>;
0758 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
0759 "fsl,imx21-ssi";
0760 reg = <0x63fcc000 0x4000>;
0761 interrupts = <29>;
0762 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
0763 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
0764 clock-names = "ipg", "baud";
0765 dmas = <&sdma 28 0 0>,
0766 <&sdma 29 0 0>;
0767 dma-names = "rx", "tx";
0768 fsl,fifo-depth = <15>;
0769 status = "disabled";
0770 };
0771
0772 audmux: audmux@63fd0000 {
0773 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
0774 reg = <0x63fd0000 0x4000>;
0775 status = "disabled";
0776 };
0777
0778 nfc: nand@63fdb000 {
0779 compatible = "fsl,imx53-nand";
0780 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
0781 interrupts = <8>;
0782 clocks = <&clks IMX5_CLK_NFC_GATE>;
0783 status = "disabled";
0784 };
0785
0786 ssi3: ssi@63fe8000 {
0787 #sound-dai-cells = <0>;
0788 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
0789 "fsl,imx21-ssi";
0790 reg = <0x63fe8000 0x4000>;
0791 interrupts = <96>;
0792 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
0793 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
0794 clock-names = "ipg", "baud";
0795 dmas = <&sdma 46 0 0>,
0796 <&sdma 47 0 0>;
0797 dma-names = "rx", "tx";
0798 fsl,fifo-depth = <15>;
0799 status = "disabled";
0800 };
0801
0802 fec: ethernet@63fec000 {
0803 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
0804 reg = <0x63fec000 0x4000>;
0805 interrupts = <87>;
0806 clocks = <&clks IMX5_CLK_FEC_GATE>,
0807 <&clks IMX5_CLK_FEC_GATE>,
0808 <&clks IMX5_CLK_FEC_GATE>;
0809 clock-names = "ipg", "ahb", "ptp";
0810 status = "disabled";
0811 };
0812
0813 tve: tve@63ff0000 {
0814 compatible = "fsl,imx53-tve";
0815 reg = <0x63ff0000 0x1000>;
0816 interrupts = <92>;
0817 clocks = <&clks IMX5_CLK_TVE_GATE>,
0818 <&clks IMX5_CLK_IPU_DI1_SEL>;
0819 clock-names = "tve", "di_sel";
0820 status = "disabled";
0821
0822 port {
0823 tve_in: endpoint {
0824 remote-endpoint = <&ipu_di1_tve>;
0825 };
0826 };
0827 };
0828
0829 vpu: vpu@63ff4000 {
0830 compatible = "fsl,imx53-vpu", "cnm,coda7541";
0831 reg = <0x63ff4000 0x1000>;
0832 interrupts = <9>;
0833 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
0834 <&clks IMX5_CLK_VPU_GATE>;
0835 clock-names = "per", "ahb";
0836 resets = <&src 1>;
0837 iram = <&ocram>;
0838 };
0839
0840 sahara: crypto@63ff8000 {
0841 compatible = "fsl,imx53-sahara";
0842 reg = <0x63ff8000 0x4000>;
0843 interrupts = <19 20>;
0844 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
0845 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
0846 clock-names = "ipg", "ahb";
0847 };
0848 };
0849
0850 ocram: sram@f8000000 {
0851 compatible = "mmio-sram";
0852 reg = <0xf8000000 0x20000>;
0853 clocks = <&clks IMX5_CLK_OCRAM>;
0854 };
0855 };
0856 };
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