0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2011 Freescale Semiconductor, Inc.
0004 // Copyright 2011 Linaro Ltd.
0005
0006 #include "imx51-pinfunc.h"
0007 #include <dt-bindings/clock/imx5-clock.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/input.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 /*
0016 * The decompressor and also some bootloaders rely on a
0017 * pre-existing /chosen node to be available to insert the
0018 * command line and merge other ATAGS info.
0019 */
0020 chosen {};
0021
0022 aliases {
0023 ethernet0 = &fec;
0024 gpio0 = &gpio1;
0025 gpio1 = &gpio2;
0026 gpio2 = &gpio3;
0027 gpio3 = &gpio4;
0028 i2c0 = &i2c1;
0029 i2c1 = &i2c2;
0030 mmc0 = &esdhc1;
0031 mmc1 = &esdhc2;
0032 mmc2 = &esdhc3;
0033 mmc3 = &esdhc4;
0034 serial0 = &uart1;
0035 serial1 = &uart2;
0036 serial2 = &uart3;
0037 spi0 = &ecspi1;
0038 spi1 = &ecspi2;
0039 spi2 = &cspi;
0040 };
0041
0042 tzic: tz-interrupt-controller@e0000000 {
0043 compatible = "fsl,imx51-tzic", "fsl,tzic";
0044 interrupt-controller;
0045 #interrupt-cells = <1>;
0046 reg = <0xe0000000 0x4000>;
0047 };
0048
0049 clocks {
0050 ckil {
0051 compatible = "fixed-clock";
0052 #clock-cells = <0>;
0053 clock-frequency = <32768>;
0054 };
0055
0056 ckih1 {
0057 compatible = "fixed-clock";
0058 #clock-cells = <0>;
0059 clock-frequency = <0>;
0060 };
0061
0062 ckih2 {
0063 compatible = "fixed-clock";
0064 #clock-cells = <0>;
0065 clock-frequency = <0>;
0066 };
0067
0068 osc {
0069 compatible = "fixed-clock";
0070 #clock-cells = <0>;
0071 clock-frequency = <24000000>;
0072 };
0073 };
0074
0075 cpus {
0076 #address-cells = <1>;
0077 #size-cells = <0>;
0078 cpu: cpu@0 {
0079 device_type = "cpu";
0080 compatible = "arm,cortex-a8";
0081 reg = <0>;
0082 clock-latency = <62500>;
0083 clocks = <&clks IMX5_CLK_CPU_PODF>;
0084 clock-names = "cpu";
0085 operating-points = <
0086 166000 1000000
0087 600000 1050000
0088 800000 1100000
0089 >;
0090 voltage-tolerance = <5>;
0091 };
0092 };
0093
0094 pmu: pmu {
0095 compatible = "arm,cortex-a8-pmu";
0096 interrupt-parent = <&tzic>;
0097 interrupts = <77>;
0098 };
0099
0100 usbphy0: usbphy0 {
0101 compatible = "usb-nop-xceiv";
0102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
0103 clock-names = "main_clk";
0104 #phy-cells = <0>;
0105 };
0106
0107 capture-subsystem {
0108 compatible = "fsl,imx-capture-subsystem";
0109 ports = <&ipu_csi0>, <&ipu_csi1>;
0110 };
0111
0112 display-subsystem {
0113 compatible = "fsl,imx-display-subsystem";
0114 ports = <&ipu_di0>, <&ipu_di1>;
0115 };
0116
0117 soc: soc {
0118 #address-cells = <1>;
0119 #size-cells = <1>;
0120 compatible = "simple-bus";
0121 interrupt-parent = <&tzic>;
0122 ranges;
0123
0124 iram: sram@1ffe0000 {
0125 compatible = "mmio-sram";
0126 reg = <0x1ffe0000 0x20000>;
0127 };
0128
0129 gpu: gpu@30000000 {
0130 compatible = "amd,imageon-200.1", "amd,imageon";
0131 reg = <0x30000000 0x20000>;
0132 reg-names = "kgsl_3d0_reg_memory";
0133 interrupts = <12>;
0134 interrupt-names = "kgsl_3d0_irq";
0135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
0136 clock-names = "core_clk", "mem_iface_clk";
0137 };
0138
0139 ipu: ipu@40000000 {
0140 #address-cells = <1>;
0141 #size-cells = <0>;
0142 compatible = "fsl,imx51-ipu";
0143 reg = <0x40000000 0x20000000>;
0144 interrupts = <11 10>;
0145 clocks = <&clks IMX5_CLK_IPU_GATE>,
0146 <&clks IMX5_CLK_IPU_DI0_GATE>,
0147 <&clks IMX5_CLK_IPU_DI1_GATE>;
0148 clock-names = "bus", "di0", "di1";
0149 resets = <&src 2>;
0150
0151 ipu_csi0: port@0 {
0152 reg = <0>;
0153 };
0154
0155 ipu_csi1: port@1 {
0156 reg = <1>;
0157 };
0158
0159 ipu_di0: port@2 {
0160 reg = <2>;
0161
0162 ipu_di0_disp1: endpoint {
0163 };
0164 };
0165
0166 ipu_di1: port@3 {
0167 reg = <3>;
0168
0169 ipu_di1_disp2: endpoint {
0170 };
0171 };
0172 };
0173
0174 aips1: bus@70000000 { /* AIPS1 */
0175 compatible = "fsl,aips-bus", "simple-bus";
0176 #address-cells = <1>;
0177 #size-cells = <1>;
0178 reg = <0x70000000 0x10000000>;
0179 ranges;
0180
0181 spba-bus@70000000 {
0182 compatible = "fsl,spba-bus", "simple-bus";
0183 #address-cells = <1>;
0184 #size-cells = <1>;
0185 reg = <0x70000000 0x40000>;
0186 ranges;
0187
0188 esdhc1: mmc@70004000 {
0189 compatible = "fsl,imx51-esdhc";
0190 reg = <0x70004000 0x4000>;
0191 interrupts = <1>;
0192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
0193 <&clks IMX5_CLK_DUMMY>,
0194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
0195 clock-names = "ipg", "ahb", "per";
0196 status = "disabled";
0197 };
0198
0199 esdhc2: mmc@70008000 {
0200 compatible = "fsl,imx51-esdhc";
0201 reg = <0x70008000 0x4000>;
0202 interrupts = <2>;
0203 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
0204 <&clks IMX5_CLK_DUMMY>,
0205 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
0206 clock-names = "ipg", "ahb", "per";
0207 bus-width = <4>;
0208 status = "disabled";
0209 };
0210
0211 uart3: serial@7000c000 {
0212 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
0213 reg = <0x7000c000 0x4000>;
0214 interrupts = <33>;
0215 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
0216 <&clks IMX5_CLK_UART3_PER_GATE>;
0217 clock-names = "ipg", "per";
0218 dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
0219 dma-names = "rx", "tx";
0220 status = "disabled";
0221 };
0222
0223 ecspi1: spi@70010000 {
0224 #address-cells = <1>;
0225 #size-cells = <0>;
0226 compatible = "fsl,imx51-ecspi";
0227 reg = <0x70010000 0x4000>;
0228 interrupts = <36>;
0229 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
0230 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
0231 clock-names = "ipg", "per";
0232 status = "disabled";
0233 };
0234
0235 ssi2: ssi@70014000 {
0236 #sound-dai-cells = <0>;
0237 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
0238 reg = <0x70014000 0x4000>;
0239 interrupts = <30>;
0240 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
0241 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
0242 clock-names = "ipg", "baud";
0243 dmas = <&sdma 24 1 0>,
0244 <&sdma 25 1 0>;
0245 dma-names = "rx", "tx";
0246 fsl,fifo-depth = <15>;
0247 status = "disabled";
0248 };
0249
0250 esdhc3: mmc@70020000 {
0251 compatible = "fsl,imx51-esdhc";
0252 reg = <0x70020000 0x4000>;
0253 interrupts = <3>;
0254 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
0255 <&clks IMX5_CLK_DUMMY>,
0256 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
0257 clock-names = "ipg", "ahb", "per";
0258 bus-width = <4>;
0259 status = "disabled";
0260 };
0261
0262 esdhc4: mmc@70024000 {
0263 compatible = "fsl,imx51-esdhc";
0264 reg = <0x70024000 0x4000>;
0265 interrupts = <4>;
0266 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
0267 <&clks IMX5_CLK_DUMMY>,
0268 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
0269 clock-names = "ipg", "ahb", "per";
0270 bus-width = <4>;
0271 status = "disabled";
0272 };
0273 };
0274
0275 aipstz1: bridge@73f00000 {
0276 compatible = "fsl,imx51-aipstz";
0277 reg = <0x73f00000 0x60>;
0278 };
0279
0280 usbotg: usb@73f80000 {
0281 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
0282 reg = <0x73f80000 0x0200>;
0283 interrupts = <18>;
0284 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0285 fsl,usbmisc = <&usbmisc 0>;
0286 fsl,usbphy = <&usbphy0>;
0287 status = "disabled";
0288 };
0289
0290 usbh1: usb@73f80200 {
0291 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
0292 reg = <0x73f80200 0x0200>;
0293 interrupts = <14>;
0294 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0295 fsl,usbmisc = <&usbmisc 1>;
0296 dr_mode = "host";
0297 status = "disabled";
0298 };
0299
0300 usbh2: usb@73f80400 {
0301 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
0302 reg = <0x73f80400 0x0200>;
0303 interrupts = <16>;
0304 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0305 fsl,usbmisc = <&usbmisc 2>;
0306 dr_mode = "host";
0307 status = "disabled";
0308 };
0309
0310 usbh3: usb@73f80600 {
0311 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
0312 reg = <0x73f80600 0x0200>;
0313 interrupts = <17>;
0314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0315 fsl,usbmisc = <&usbmisc 3>;
0316 dr_mode = "host";
0317 status = "disabled";
0318 };
0319
0320 usbmisc: usbmisc@73f80800 {
0321 #index-cells = <1>;
0322 compatible = "fsl,imx51-usbmisc";
0323 reg = <0x73f80800 0x200>;
0324 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0325 };
0326
0327 gpio1: gpio@73f84000 {
0328 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
0329 reg = <0x73f84000 0x4000>;
0330 interrupts = <50 51>;
0331 gpio-controller;
0332 #gpio-cells = <2>;
0333 interrupt-controller;
0334 #interrupt-cells = <2>;
0335 };
0336
0337 gpio2: gpio@73f88000 {
0338 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
0339 reg = <0x73f88000 0x4000>;
0340 interrupts = <52 53>;
0341 gpio-controller;
0342 #gpio-cells = <2>;
0343 interrupt-controller;
0344 #interrupt-cells = <2>;
0345 };
0346
0347 gpio3: gpio@73f8c000 {
0348 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
0349 reg = <0x73f8c000 0x4000>;
0350 interrupts = <54 55>;
0351 gpio-controller;
0352 #gpio-cells = <2>;
0353 interrupt-controller;
0354 #interrupt-cells = <2>;
0355 };
0356
0357 gpio4: gpio@73f90000 {
0358 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
0359 reg = <0x73f90000 0x4000>;
0360 interrupts = <56 57>;
0361 gpio-controller;
0362 #gpio-cells = <2>;
0363 interrupt-controller;
0364 #interrupt-cells = <2>;
0365 };
0366
0367 kpp: kpp@73f94000 {
0368 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
0369 reg = <0x73f94000 0x4000>;
0370 interrupts = <60>;
0371 clocks = <&clks IMX5_CLK_DUMMY>;
0372 status = "disabled";
0373 };
0374
0375 wdog1: watchdog@73f98000 {
0376 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
0377 reg = <0x73f98000 0x4000>;
0378 interrupts = <58>;
0379 clocks = <&clks IMX5_CLK_DUMMY>;
0380 };
0381
0382 wdog2: watchdog@73f9c000 {
0383 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
0384 reg = <0x73f9c000 0x4000>;
0385 interrupts = <59>;
0386 clocks = <&clks IMX5_CLK_DUMMY>;
0387 status = "disabled";
0388 };
0389
0390 gpt: timer@73fa0000 {
0391 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
0392 reg = <0x73fa0000 0x4000>;
0393 interrupts = <39>;
0394 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
0395 <&clks IMX5_CLK_GPT_HF_GATE>;
0396 clock-names = "ipg", "per";
0397 };
0398
0399 iomuxc: iomuxc@73fa8000 {
0400 compatible = "fsl,imx51-iomuxc";
0401 reg = <0x73fa8000 0x4000>;
0402 };
0403
0404 pwm1: pwm@73fb4000 {
0405 #pwm-cells = <3>;
0406 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
0407 reg = <0x73fb4000 0x4000>;
0408 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
0409 <&clks IMX5_CLK_PWM1_HF_GATE>;
0410 clock-names = "ipg", "per";
0411 interrupts = <61>;
0412 };
0413
0414 pwm2: pwm@73fb8000 {
0415 #pwm-cells = <3>;
0416 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
0417 reg = <0x73fb8000 0x4000>;
0418 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
0419 <&clks IMX5_CLK_PWM2_HF_GATE>;
0420 clock-names = "ipg", "per";
0421 interrupts = <94>;
0422 };
0423
0424 uart1: serial@73fbc000 {
0425 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
0426 reg = <0x73fbc000 0x4000>;
0427 interrupts = <31>;
0428 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
0429 <&clks IMX5_CLK_UART1_PER_GATE>;
0430 clock-names = "ipg", "per";
0431 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
0432 dma-names = "rx", "tx";
0433 status = "disabled";
0434 };
0435
0436 uart2: serial@73fc0000 {
0437 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
0438 reg = <0x73fc0000 0x4000>;
0439 interrupts = <32>;
0440 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
0441 <&clks IMX5_CLK_UART2_PER_GATE>;
0442 clock-names = "ipg", "per";
0443 dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
0444 dma-names = "rx", "tx";
0445 status = "disabled";
0446 };
0447
0448 src: reset-controller@73fd0000 {
0449 compatible = "fsl,imx51-src";
0450 reg = <0x73fd0000 0x4000>;
0451 interrupts = <75>;
0452 #reset-cells = <1>;
0453 };
0454
0455 clks: ccm@73fd4000{
0456 compatible = "fsl,imx51-ccm";
0457 reg = <0x73fd4000 0x4000>;
0458 interrupts = <0 71 0x04 0 72 0x04>;
0459 #clock-cells = <1>;
0460 };
0461 };
0462
0463 aips2: bus@80000000 { /* AIPS2 */
0464 compatible = "fsl,aips-bus", "simple-bus";
0465 #address-cells = <1>;
0466 #size-cells = <1>;
0467 reg = <0x80000000 0x10000000>;
0468 ranges;
0469
0470 aipstz2: bridge@83f00000 {
0471 compatible = "fsl,imx51-aipstz";
0472 reg = <0x83f00000 0x60>;
0473 };
0474
0475 iim: efuse@83f98000 {
0476 compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon";
0477 reg = <0x83f98000 0x4000>;
0478 interrupts = <69>;
0479 clocks = <&clks IMX5_CLK_IIM_GATE>;
0480 };
0481
0482 tigerp: tigerp@83fa0000 {
0483 compatible = "fsl,imx51-tigerp";
0484 reg = <0x83fa0000 0x28>;
0485 };
0486
0487 owire: owire@83fa4000 {
0488 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
0489 reg = <0x83fa4000 0x4000>;
0490 interrupts = <88>;
0491 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
0492 status = "disabled";
0493 };
0494
0495 ecspi2: spi@83fac000 {
0496 #address-cells = <1>;
0497 #size-cells = <0>;
0498 compatible = "fsl,imx51-ecspi";
0499 reg = <0x83fac000 0x4000>;
0500 interrupts = <37>;
0501 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
0502 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
0503 clock-names = "ipg", "per";
0504 status = "disabled";
0505 };
0506
0507 sdma: sdma@83fb0000 {
0508 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
0509 reg = <0x83fb0000 0x4000>;
0510 interrupts = <6>;
0511 clocks = <&clks IMX5_CLK_SDMA_GATE>,
0512 <&clks IMX5_CLK_AHB>;
0513 clock-names = "ipg", "ahb";
0514 #dma-cells = <3>;
0515 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
0516 };
0517
0518 cspi: spi@83fc0000 {
0519 #address-cells = <1>;
0520 #size-cells = <0>;
0521 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
0522 reg = <0x83fc0000 0x4000>;
0523 interrupts = <38>;
0524 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
0525 <&clks IMX5_CLK_CSPI_IPG_GATE>;
0526 clock-names = "ipg", "per";
0527 status = "disabled";
0528 };
0529
0530 i2c2: i2c@83fc4000 {
0531 #address-cells = <1>;
0532 #size-cells = <0>;
0533 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
0534 reg = <0x83fc4000 0x4000>;
0535 interrupts = <63>;
0536 clocks = <&clks IMX5_CLK_I2C2_GATE>;
0537 status = "disabled";
0538 };
0539
0540 i2c1: i2c@83fc8000 {
0541 #address-cells = <1>;
0542 #size-cells = <0>;
0543 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
0544 reg = <0x83fc8000 0x4000>;
0545 interrupts = <62>;
0546 clocks = <&clks IMX5_CLK_I2C1_GATE>;
0547 status = "disabled";
0548 };
0549
0550 ssi1: ssi@83fcc000 {
0551 #sound-dai-cells = <0>;
0552 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
0553 reg = <0x83fcc000 0x4000>;
0554 interrupts = <29>;
0555 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
0556 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
0557 clock-names = "ipg", "baud";
0558 dmas = <&sdma 28 0 0>,
0559 <&sdma 29 0 0>;
0560 dma-names = "rx", "tx";
0561 fsl,fifo-depth = <15>;
0562 status = "disabled";
0563 };
0564
0565 audmux: audmux@83fd0000 {
0566 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
0567 reg = <0x83fd0000 0x4000>;
0568 clocks = <&clks IMX5_CLK_DUMMY>;
0569 clock-names = "audmux";
0570 status = "disabled";
0571 };
0572
0573 m4if: m4if@83fd8000 {
0574 compatible = "fsl,imx51-m4if";
0575 reg = <0x83fd8000 0x1000>;
0576 };
0577
0578 weim: weim@83fda000 {
0579 #address-cells = <2>;
0580 #size-cells = <1>;
0581 compatible = "fsl,imx51-weim";
0582 reg = <0x83fda000 0x1000>;
0583 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
0584 ranges = <
0585 0 0 0xb0000000 0x08000000
0586 1 0 0xb8000000 0x08000000
0587 2 0 0xc0000000 0x08000000
0588 3 0 0xc8000000 0x04000000
0589 4 0 0xcc000000 0x02000000
0590 5 0 0xce000000 0x02000000
0591 >;
0592 status = "disabled";
0593 };
0594
0595 nfc: nand@83fdb000 {
0596 #address-cells = <1>;
0597 #size-cells = <1>;
0598 compatible = "fsl,imx51-nand";
0599 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
0600 interrupts = <8>;
0601 clocks = <&clks IMX5_CLK_NFC_GATE>;
0602 status = "disabled";
0603 };
0604
0605 pata: pata@83fe0000 {
0606 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
0607 reg = <0x83fe0000 0x4000>;
0608 interrupts = <70>;
0609 clocks = <&clks IMX5_CLK_PATA_GATE>;
0610 status = "disabled";
0611 };
0612
0613 ssi3: ssi@83fe8000 {
0614 #sound-dai-cells = <0>;
0615 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
0616 reg = <0x83fe8000 0x4000>;
0617 interrupts = <96>;
0618 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
0619 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
0620 clock-names = "ipg", "baud";
0621 dmas = <&sdma 46 0 0>,
0622 <&sdma 47 0 0>;
0623 dma-names = "rx", "tx";
0624 fsl,fifo-depth = <15>;
0625 status = "disabled";
0626 };
0627
0628 fec: ethernet@83fec000 {
0629 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
0630 reg = <0x83fec000 0x4000>;
0631 interrupts = <87>;
0632 clocks = <&clks IMX5_CLK_FEC_GATE>,
0633 <&clks IMX5_CLK_FEC_GATE>,
0634 <&clks IMX5_CLK_FEC_GATE>;
0635 clock-names = "ipg", "ahb", "ptp";
0636 status = "disabled";
0637 };
0638
0639 vpu: vpu@83ff4000 {
0640 compatible = "fsl,imx51-vpu", "cnm,codahx4";
0641 reg = <0x83ff4000 0x1000>;
0642 interrupts = <9>;
0643 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
0644 <&clks IMX5_CLK_VPU_GATE>;
0645 clock-names = "per", "ahb";
0646 resets = <&src 1>;
0647 iram = <&iram>;
0648 };
0649
0650 sahara: crypto@83ff8000 {
0651 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
0652 reg = <0x83ff8000 0x4000>;
0653 interrupts = <19 20>;
0654 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
0655 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
0656 clock-names = "ipg", "ahb";
0657 };
0658 };
0659 };
0660 };
