0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2017 Zodiac Inflight Innovations
0004 */
0005
0006 /dts-v1/;
0007 #include "imx51.dtsi"
0008 #include <dt-bindings/sound/fsl-imx-audmux.h>
0009
0010 / {
0011 model = "ZII RDU1 Board";
0012 compatible = "zii,imx51-rdu1", "fsl,imx51";
0013
0014 chosen {
0015 stdout-path = &uart1;
0016 };
0017
0018 /* Will be filled by the bootloader */
0019 memory@90000000 {
0020 device_type = "memory";
0021 reg = <0x90000000 0>;
0022 };
0023
0024 aliases {
0025 mdio-gpio0 = &mdio_gpio;
0026 rtc0 = &ds1341;
0027 };
0028
0029 clk_26M_osc: 26M_osc {
0030 compatible = "fixed-clock";
0031 #clock-cells = <0>;
0032 clock-frequency = <26000000>;
0033 };
0034
0035 clk_26M_osc_gate: 26M_gate {
0036 compatible = "gpio-gate-clock";
0037 pinctrl-names = "default";
0038 pinctrl-0 = <&pinctrl_clk26mhz>;
0039 clocks = <&clk_26M_osc>;
0040 #clock-cells = <0>;
0041 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
0042 };
0043
0044 clk_26M_usb: usbhost_gate {
0045 compatible = "gpio-gate-clock";
0046 pinctrl-names = "default";
0047 pinctrl-0 = <&pinctrl_usbgate26mhz>;
0048 clocks = <&clk_26M_osc_gate>;
0049 #clock-cells = <0>;
0050 enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0051 };
0052
0053 clk_26M_snd: snd_gate {
0054 compatible = "gpio-gate-clock";
0055 pinctrl-names = "default";
0056 pinctrl-0 = <&pinctrl_sndgate26mhz>;
0057 clocks = <&clk_26M_osc_gate>;
0058 #clock-cells = <0>;
0059 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
0060 };
0061
0062 reg_5p0v_main: regulator-5p0v-main {
0063 compatible = "regulator-fixed";
0064 regulator-name = "5V_MAIN";
0065 regulator-min-microvolt = <5000000>;
0066 regulator-max-microvolt = <5000000>;
0067 regulator-always-on;
0068 };
0069
0070 reg_3p3v: regulator-3p3v {
0071 compatible = "regulator-fixed";
0072 regulator-name = "3.3V";
0073 regulator-min-microvolt = <3300000>;
0074 regulator-max-microvolt = <3300000>;
0075 regulator-always-on;
0076 };
0077
0078 disp0 {
0079 compatible = "fsl,imx-parallel-display";
0080 pinctrl-names = "default";
0081 pinctrl-0 = <&pinctrl_ipu_disp1>;
0082
0083 #address-cells = <1>;
0084 #size-cells = <0>;
0085
0086 port@0 {
0087 reg = <0>;
0088
0089 display_in: endpoint {
0090 remote-endpoint = <&ipu_di0_disp1>;
0091 };
0092 };
0093
0094 port@1 {
0095 reg = <1>;
0096
0097 display_out: endpoint {
0098 remote-endpoint = <&panel_in>;
0099 };
0100 };
0101 };
0102
0103 panel {
0104 /* no compatible here, bootloader will patch in correct one */
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_panel>;
0107 power-supply = <®_3p3v>;
0108 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
0109 status = "disabled";
0110
0111 port {
0112 panel_in: endpoint {
0113 remote-endpoint = <&display_out>;
0114 };
0115 };
0116 };
0117
0118 i2c_gpio: i2c-gpio {
0119 compatible = "i2c-gpio";
0120 pinctrl-names = "default";
0121 pinctrl-0 = <&pinctrl_swi2c>;
0122 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
0123 <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
0124 i2c-gpio,delay-us = <50>;
0125 status = "okay";
0126
0127 #address-cells = <1>;
0128 #size-cells = <0>;
0129
0130 sgtl5000: codec@a {
0131 compatible = "fsl,sgtl5000";
0132 reg = <0x0a>;
0133 clocks = <&clk_26M_snd>;
0134 VDDA-supply = <&vdig_reg>;
0135 VDDIO-supply = <&vvideo_reg>;
0136 #sound-dai-cells = <0>;
0137 };
0138 };
0139
0140 spi_gpio: spi-gpio {
0141 compatible = "spi-gpio";
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&pinctrl_gpiospi0>;
0146 status = "okay";
0147
0148 gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>;
0149 gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>;
0150 gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>;
0151 num-chipselects = <1>;
0152 cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
0153
0154 eeprom@0 {
0155 compatible = "eeprom-93xx46";
0156 reg = <0>;
0157 spi-max-frequency = <1000000>;
0158 spi-cs-high;
0159 data-size = <8>;
0160 };
0161 };
0162
0163 mdio_gpio: mdio-gpio {
0164 compatible = "virtual,mdio-gpio";
0165 pinctrl-names = "default";
0166 pinctrl-0 = <&pinctrl_swmdio>;
0167 gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */
0168 <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */
0169
0170 #address-cells = <1>;
0171 #size-cells = <0>;
0172
0173 switch@0 {
0174 compatible = "marvell,mv88e6085";
0175 reg = <0>;
0176 dsa,member = <0 0>;
0177
0178 ports {
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181
0182 port@0 {
0183 reg = <0>;
0184 label = "cpu";
0185 ethernet = <&fec>;
0186
0187 fixed-link {
0188 speed = <100>;
0189 full-duplex;
0190 };
0191 };
0192
0193 port@1 {
0194 reg = <1>;
0195 label = "netaux";
0196 };
0197
0198 port@3 {
0199 reg = <3>;
0200 label = "netright";
0201 };
0202
0203 port@4 {
0204 reg = <4>;
0205 label = "netleft";
0206 };
0207 };
0208 };
0209 };
0210
0211 sound {
0212 compatible = "simple-audio-card";
0213 simple-audio-card,name = "Front";
0214 simple-audio-card,format = "i2s";
0215 simple-audio-card,bitclock-master = <&sound_codec>;
0216 simple-audio-card,frame-master = <&sound_codec>;
0217 simple-audio-card,widgets =
0218 "Headphone", "Headphone Jack";
0219 simple-audio-card,routing =
0220 "Headphone Jack", "TPA6130A2 HPLEFT",
0221 "Headphone Jack", "TPA6130A2 HPRIGHT";
0222 simple-audio-card,aux-devs = <&hpa1>;
0223
0224 sound_cpu: simple-audio-card,cpu {
0225 sound-dai = <&ssi2>;
0226 };
0227
0228 sound_codec: simple-audio-card,codec {
0229 sound-dai = <&sgtl5000>;
0230 clocks = <&clk_26M_snd>;
0231 };
0232 };
0233
0234 usbh1phy: usbphy1 {
0235 compatible = "usb-nop-xceiv";
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_usbh1phy>;
0238 clocks = <&clk_26M_usb>;
0239 clock-names = "main_clk";
0240 reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
0241 vcc-supply = <&vusb_reg>;
0242 #phy-cells = <0>;
0243 };
0244
0245 usbh2phy: usbphy2 {
0246 compatible = "usb-nop-xceiv";
0247 pinctrl-names = "default";
0248 pinctrl-0 = <&pinctrl_usbh2phy>;
0249 clocks = <&clk_26M_usb>;
0250 clock-names = "main_clk";
0251 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
0252 vcc-supply = <&vusb_reg>;
0253 #phy-cells = <0>;
0254 };
0255 };
0256
0257 &audmux {
0258 pinctrl-names = "default";
0259 pinctrl-0 = <&pinctrl_audmux>;
0260 status = "okay";
0261
0262 ssi2 {
0263 fsl,audmux-port = <1>;
0264 fsl,port-config = <
0265 (IMX_AUDMUX_V2_PTCR_SYN |
0266 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
0267 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
0268 IMX_AUDMUX_V2_PTCR_TFSDIR |
0269 IMX_AUDMUX_V2_PTCR_TCLKDIR)
0270 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
0271 >;
0272 };
0273
0274 aud3 {
0275 fsl,audmux-port = <2>;
0276 fsl,port-config = <
0277 IMX_AUDMUX_V2_PTCR_SYN
0278 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
0279 >;
0280 };
0281 };
0282
0283 &cpu {
0284 cpu-supply = <&sw1_reg>;
0285 };
0286
0287 &ecspi1 {
0288 pinctrl-names = "default";
0289 pinctrl-0 = <&pinctrl_ecspi1>;
0290 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
0291 <&gpio4 25 GPIO_ACTIVE_LOW>;
0292 status = "okay";
0293
0294 pmic@0 {
0295 compatible = "fsl,mc13892";
0296 pinctrl-names = "default";
0297 pinctrl-0 = <&pinctrl_pmic>;
0298 spi-max-frequency = <6000000>;
0299 spi-cs-high;
0300 reg = <0>;
0301 interrupt-parent = <&gpio1>;
0302 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
0303 fsl,mc13xxx-uses-adc;
0304
0305 regulators {
0306 sw1_reg: sw1 {
0307 regulator-min-microvolt = <600000>;
0308 regulator-max-microvolt = <1375000>;
0309 regulator-boot-on;
0310 regulator-always-on;
0311 };
0312
0313 sw2_reg: sw2 {
0314 regulator-min-microvolt = <900000>;
0315 regulator-max-microvolt = <1850000>;
0316 regulator-boot-on;
0317 regulator-always-on;
0318 };
0319
0320 sw3_reg: sw3 {
0321 regulator-min-microvolt = <1100000>;
0322 regulator-max-microvolt = <1850000>;
0323 regulator-boot-on;
0324 regulator-always-on;
0325 };
0326
0327 sw4_reg: sw4 {
0328 regulator-min-microvolt = <1100000>;
0329 regulator-max-microvolt = <1850000>;
0330 regulator-boot-on;
0331 regulator-always-on;
0332 };
0333
0334 vpll_reg: vpll {
0335 regulator-min-microvolt = <1050000>;
0336 regulator-max-microvolt = <1800000>;
0337 regulator-boot-on;
0338 regulator-always-on;
0339 };
0340
0341 vdig_reg: vdig {
0342 regulator-min-microvolt = <1650000>;
0343 regulator-max-microvolt = <1650000>;
0344 regulator-boot-on;
0345 };
0346
0347 vsd_reg: vsd {
0348 regulator-min-microvolt = <1800000>;
0349 regulator-max-microvolt = <3150000>;
0350 };
0351
0352 vusb_reg: vusb {
0353 regulator-always-on;
0354 };
0355
0356 vusb2_reg: vusb2 {
0357 regulator-min-microvolt = <2400000>;
0358 regulator-max-microvolt = <2775000>;
0359 regulator-boot-on;
0360 regulator-always-on;
0361 };
0362
0363 vvideo_reg: vvideo {
0364 regulator-min-microvolt = <2775000>;
0365 regulator-max-microvolt = <2775000>;
0366 };
0367
0368 vaudio_reg: vaudio {
0369 regulator-min-microvolt = <2300000>;
0370 regulator-max-microvolt = <3000000>;
0371 };
0372
0373 vcam_reg: vcam {
0374 regulator-min-microvolt = <2500000>;
0375 regulator-max-microvolt = <3000000>;
0376 };
0377
0378 vgen1_reg: vgen1 {
0379 regulator-min-microvolt = <1200000>;
0380 regulator-max-microvolt = <1200000>;
0381 };
0382
0383 vgen2_reg: vgen2 {
0384 regulator-min-microvolt = <1200000>;
0385 regulator-max-microvolt = <3150000>;
0386 regulator-always-on;
0387 };
0388
0389 vgen3_reg: vgen3 {
0390 regulator-min-microvolt = <1800000>;
0391 regulator-max-microvolt = <2900000>;
0392 regulator-always-on;
0393 };
0394 };
0395
0396 leds {
0397 #address-cells = <1>;
0398 #size-cells = <0>;
0399 led-control = <0x0 0x0 0x3f83f8 0x0>;
0400
0401 sysled0@3 {
0402 reg = <3>;
0403 label = "system:green:status";
0404 linux,default-trigger = "default-on";
0405 };
0406
0407 sysled1@4 {
0408 reg = <4>;
0409 label = "system:green:act";
0410 linux,default-trigger = "heartbeat";
0411 };
0412 };
0413 };
0414
0415 flash@1 {
0416 #address-cells = <1>;
0417 #size-cells = <1>;
0418 compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
0419 spi-max-frequency = <25000000>;
0420 reg = <1>;
0421 };
0422 };
0423
0424 &esdhc1 {
0425 pinctrl-names = "default";
0426 pinctrl-0 = <&pinctrl_esdhc1>;
0427 bus-width = <4>;
0428 no-1-8-v;
0429 non-removable;
0430 no-sdio;
0431 no-sd;
0432 status = "okay";
0433 };
0434
0435 &fec {
0436 pinctrl-names = "default";
0437 pinctrl-0 = <&pinctrl_fec>;
0438 phy-mode = "mii";
0439 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
0440 phy-supply = <&vgen3_reg>;
0441 status = "okay";
0442 };
0443
0444 &gpio1 {
0445 gpio-line-names = "", "", "", "",
0446 "", "", "", "",
0447 "", "hp-amp-shutdown-b", "", "",
0448 "", "", "", "",
0449 "", "", "", "",
0450 "", "", "", "",
0451 "", "", "", "",
0452 "", "", "", "";
0453
0454 unused-sd3-wp-hog {
0455 /*
0456 * See pinctrl_esdhc1 below for more details on this
0457 */
0458 gpio-hog;
0459 gpios = <1 GPIO_ACTIVE_HIGH>;
0460 output-high;
0461 };
0462 };
0463
0464 &i2c2 {
0465 pinctrl-names = "default";
0466 pinctrl-0 = <&pinctrl_i2c2>;
0467 status = "okay";
0468
0469 hpa1: amp@60 {
0470 compatible = "ti,tpa6130a2";
0471 reg = <0x60>;
0472 Vdd-supply = <®_3p3v>;
0473 sound-name-prefix = "TPA6130A2";
0474 };
0475
0476 ds1341: rtc@68 {
0477 compatible = "dallas,ds1341";
0478 reg = <0x68>;
0479 };
0480
0481 /* touch nodes default disabled, bootloader will enable the right one */
0482
0483 touchscreen@4b {
0484 compatible = "atmel,maxtouch";
0485 reg = <0x4b>;
0486 pinctrl-names = "default";
0487 pinctrl-0 = <&pinctrl_ts>;
0488 interrupt-parent = <&gpio3>;
0489 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
0490 status = "disabled";
0491 };
0492
0493 touchscreen@4c {
0494 compatible = "atmel,maxtouch";
0495 reg = <0x4c>;
0496 pinctrl-names = "default";
0497 pinctrl-0 = <&pinctrl_ts>;
0498 interrupt-parent = <&gpio3>;
0499 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
0500 status = "disabled";
0501 };
0502
0503 touchscreen@20 {
0504 compatible = "syna,rmi4-i2c";
0505 reg = <0x20>;
0506 pinctrl-names = "default";
0507 pinctrl-0 = <&pinctrl_ts>;
0508 interrupt-parent = <&gpio3>;
0509 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
0510 status = "disabled";
0511
0512 #address-cells = <1>;
0513 #size-cells = <0>;
0514
0515 rmi4-f01@1 {
0516 reg = <0x1>;
0517 syna,nosleep-mode = <2>;
0518 };
0519
0520 rmi4-f11@11 {
0521 reg = <0x11>;
0522 touchscreen-inverted-x;
0523 touchscreen-swapped-x-y;
0524 syna,sensor-type = <1>;
0525 };
0526 };
0527
0528 };
0529
0530 &ipu_di0_disp1 {
0531 remote-endpoint = <&display_in>;
0532 };
0533
0534 &pmu {
0535 secure-reg-access;
0536 };
0537
0538 &ssi2 {
0539 status = "okay";
0540 };
0541
0542 &uart1 {
0543 pinctrl-names = "default";
0544 pinctrl-0 = <&pinctrl_uart1>;
0545 status = "okay";
0546 };
0547
0548 &uart2 {
0549 pinctrl-names = "default";
0550 pinctrl-0 = <&pinctrl_uart2>;
0551 status = "okay";
0552 };
0553
0554 &uart3 {
0555 pinctrl-names = "default";
0556 pinctrl-0 = <&pinctrl_uart3>;
0557 status = "okay";
0558
0559 rave-sp {
0560 compatible = "zii,rave-sp-rdu1";
0561 current-speed = <38400>;
0562 #address-cells = <1>;
0563 #size-cells = <1>;
0564
0565 watchdog {
0566 compatible = "zii,rave-sp-watchdog";
0567 };
0568
0569 backlight {
0570 compatible = "zii,rave-sp-backlight";
0571 };
0572
0573 pwrbutton {
0574 compatible = "zii,rave-sp-pwrbutton";
0575 };
0576
0577 eeprom@a3 {
0578 compatible = "zii,rave-sp-eeprom";
0579 reg = <0xa3 0x2000>;
0580 #address-cells = <1>;
0581 #size-cells = <1>;
0582 zii,eeprom-name = "dds-eeprom";
0583 };
0584
0585 eeprom@a4 {
0586 compatible = "zii,rave-sp-eeprom";
0587 reg = <0xa4 0x4000>;
0588 #address-cells = <1>;
0589 #size-cells = <1>;
0590 zii,eeprom-name = "main-eeprom";
0591 };
0592
0593 eeprom@ae {
0594 compatible = "zii,rave-sp-eeprom";
0595 reg = <0xae 0x200>;
0596 zii,eeprom-name = "switch-eeprom";
0597 /*
0598 * Not all RDU1s have this functionality, so we
0599 * rely on the bootloader to enable this
0600 */
0601 status = "disabled";
0602 };
0603 };
0604 };
0605
0606 &usbh1 {
0607 pinctrl-names = "default";
0608 pinctrl-0 = <&pinctrl_usbh1>;
0609 dr_mode = "host";
0610 phy_type = "ulpi";
0611 fsl,usbphy = <&usbh1phy>;
0612 disable-over-current;
0613 maximum-speed = "full-speed";
0614 vbus-supply = <®_5p0v_main>;
0615 status = "okay";
0616 };
0617
0618 &usbh2 {
0619 pinctrl-names = "default";
0620 pinctrl-0 = <&pinctrl_usbh2>;
0621 dr_mode = "host";
0622 phy_type = "ulpi";
0623 fsl,usbphy = <&usbh2phy>;
0624 disable-over-current;
0625 vbus-supply = <®_5p0v_main>;
0626 status = "okay";
0627 };
0628
0629 &usbphy0 {
0630 vcc-supply = <&vusb_reg>;
0631 };
0632
0633 &usbotg {
0634 dr_mode = "host";
0635 disable-over-current;
0636 phy_type = "utmi_wide";
0637 vbus-supply = <®_5p0v_main>;
0638 status = "okay";
0639 };
0640
0641 &wdog1 {
0642 status = "disabled";
0643 };
0644
0645 &iomuxc {
0646 pinctrl-names = "default";
0647 pinctrl-0 = <&pinctrl_hog>;
0648
0649 pinctrl_hog: hoggrp {
0650 fsl,pins = <
0651 MX51_PAD_GPIO1_9__GPIO1_9 0x5e
0652 >;
0653 };
0654
0655 pinctrl_audmux: audmuxgrp {
0656 fsl,pins = <
0657 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5
0658 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85
0659 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5
0660 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85
0661 >;
0662 };
0663
0664 pinctrl_clk26mhz: clk26mhzgrp {
0665 fsl,pins = <
0666 MX51_PAD_DI1_PIN12__GPIO3_1 0x85
0667 >;
0668 };
0669
0670 pinctrl_ecspi1: ecspi1grp {
0671 fsl,pins = <
0672 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
0673 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
0674 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
0675 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
0676 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
0677 >;
0678 };
0679
0680 pinctrl_esdhc1: esdhc1grp {
0681 fsl,pins = <
0682 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
0683 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
0684 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
0685 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
0686 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
0687 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
0688 /*
0689 * GPIO1_1 is not directly used by eSDHC1 in
0690 * any capacity, but earlier versions of RDU1
0691 * used that pin as WP GPIO for eSDHC3 and
0692 * because of that that pad has an external
0693 * pull-up resistor. This is problematic
0694 * because out of reset the pad is configured
0695 * as ALT0 which serves as SD1_WP, which, when
0696 * pulled high by and external pull-up, will
0697 * inhibit execution of any write request to
0698 * attached eMMC device.
0699 *
0700 * To avoid this problem we configure the pad
0701 * to ALT1/GPIO and avoid driving SD1_WP
0702 * signal high.
0703 */
0704 MX51_PAD_GPIO1_1__GPIO1_1 0x0000
0705 >;
0706 };
0707
0708 pinctrl_fec: fecgrp {
0709 fsl,pins = <
0710 MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5
0711 MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180
0712 MX51_PAD_EIM_EB3__FEC_RDATA1 0x180
0713 MX51_PAD_EIM_CS2__FEC_RDATA2 0x180
0714 MX51_PAD_EIM_CS3__FEC_RDATA3 0x180
0715 MX51_PAD_EIM_CS4__FEC_RX_ER 0x180
0716 MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084
0717 MX51_PAD_EIM_CS5__FEC_CRS 0x180
0718 MX51_PAD_NANDF_RB2__FEC_COL 0x2180
0719 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180
0720 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004
0721 MX51_PAD_NANDF_CS3__FEC_MDC 0x2004
0722 MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180
0723 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004
0724 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004
0725 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004
0726 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
0727 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
0728 MX51_PAD_EIM_A20__GPIO2_14 0x85
0729 >;
0730 };
0731
0732 pinctrl_gpiospi0: gpiospi0grp {
0733 fsl,pins = <
0734 MX51_PAD_CSI2_D18__GPIO4_11 0x85
0735 MX51_PAD_CSI2_D19__GPIO4_12 0x85
0736 MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85
0737 MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85
0738 >;
0739 };
0740
0741 pinctrl_i2c2: i2c2grp {
0742 fsl,pins = <
0743 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
0744 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
0745 >;
0746 };
0747
0748 pinctrl_ipu_disp1: ipudisp1grp {
0749 fsl,pins = <
0750 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
0751 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
0752 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
0753 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
0754 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
0755 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
0756 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
0757 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
0758 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
0759 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
0760 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
0761 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
0762 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
0763 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
0764 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
0765 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
0766 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
0767 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
0768 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
0769 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
0770 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
0771 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
0772 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
0773 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
0774 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
0775 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
0776 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
0777 >;
0778 };
0779
0780 pinctrl_panel: panelgrp {
0781 fsl,pins = <
0782 MX51_PAD_DI1_D0_CS__GPIO3_3 0x85
0783 >;
0784 };
0785
0786 pinctrl_pmic: pmicgrp {
0787 fsl,pins = <
0788 MX51_PAD_GPIO1_4__GPIO1_4 0x1e0
0789 MX51_PAD_GPIO1_8__GPIO1_8 0x21e2
0790 >;
0791 };
0792
0793 pinctrl_sndgate26mhz: sndgate26mhzgrp {
0794 fsl,pins = <
0795 MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
0796 >;
0797 };
0798
0799 pinctrl_swi2c: swi2cgrp {
0800 fsl,pins = <
0801 MX51_PAD_GPIO1_2__GPIO1_2 0xc5
0802 MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5
0803 >;
0804 };
0805
0806 pinctrl_swmdio: swmdiogrp {
0807 fsl,pins = <
0808 MX51_PAD_NANDF_D14__GPIO3_26 0x21e6
0809 MX51_PAD_NANDF_D15__GPIO3_25 0x21e6
0810 >;
0811 };
0812
0813 pinctrl_ts: tsgrp {
0814 fsl,pins = <
0815 MX51_PAD_CSI1_D8__GPIO3_12 0x04
0816 MX51_PAD_CSI1_D9__GPIO3_13 0x85
0817 >;
0818 };
0819
0820 pinctrl_uart1: uart1grp {
0821 fsl,pins = <
0822 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
0823 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
0824 MX51_PAD_UART1_RTS__UART1_RTS 0x1c4
0825 MX51_PAD_UART1_CTS__UART1_CTS 0x1c4
0826 >;
0827 };
0828
0829 pinctrl_uart2: uart2grp {
0830 fsl,pins = <
0831 MX51_PAD_UART2_RXD__UART2_RXD 0xc5
0832 MX51_PAD_UART2_TXD__UART2_TXD 0xc5
0833 >;
0834 };
0835
0836 pinctrl_uart3: uart3grp {
0837 fsl,pins = <
0838 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
0839 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
0840 >;
0841 };
0842
0843 pinctrl_usbgate26mhz: usbgate26mhzgrp {
0844 fsl,pins = <
0845 MX51_PAD_DISP2_DAT6__GPIO1_19 0x85
0846 >;
0847 };
0848
0849 pinctrl_usbh1: usbh1grp {
0850 fsl,pins = <
0851 MX51_PAD_USBH1_STP__USBH1_STP 0x0
0852 MX51_PAD_USBH1_CLK__USBH1_CLK 0x0
0853 MX51_PAD_USBH1_DIR__USBH1_DIR 0x0
0854 MX51_PAD_USBH1_NXT__USBH1_NXT 0x0
0855 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0
0856 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0
0857 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0
0858 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0
0859 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0
0860 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0
0861 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0
0862 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0
0863 >;
0864 };
0865
0866 pinctrl_usbh1phy: usbh1phygrp {
0867 fsl,pins = <
0868 MX51_PAD_NANDF_D0__GPIO4_8 0x85
0869 >;
0870 };
0871
0872 pinctrl_usbh2: usbh2grp {
0873 fsl,pins = <
0874 MX51_PAD_EIM_A26__USBH2_STP 0x0
0875 MX51_PAD_EIM_A24__USBH2_CLK 0x0
0876 MX51_PAD_EIM_A25__USBH2_DIR 0x0
0877 MX51_PAD_EIM_A27__USBH2_NXT 0x0
0878 MX51_PAD_EIM_D16__USBH2_DATA0 0x0
0879 MX51_PAD_EIM_D17__USBH2_DATA1 0x0
0880 MX51_PAD_EIM_D18__USBH2_DATA2 0x0
0881 MX51_PAD_EIM_D19__USBH2_DATA3 0x0
0882 MX51_PAD_EIM_D20__USBH2_DATA4 0x0
0883 MX51_PAD_EIM_D21__USBH2_DATA5 0x0
0884 MX51_PAD_EIM_D22__USBH2_DATA6 0x0
0885 MX51_PAD_EIM_D23__USBH2_DATA7 0x0
0886 >;
0887 };
0888
0889 pinctrl_usbh2phy: usbh2phygrp {
0890 fsl,pins = <
0891 MX51_PAD_NANDF_D1__GPIO4_7 0x85
0892 >;
0893 };
0894 };
