0001 /*
0002 * Copyright 2015 Savoir-faire Linux
0003 *
0004 * This device tree is based on imx51-babbage.dts
0005 *
0006 * Licensed under the X11 license or the GPL v2 (or later)
0007 */
0008
0009 /dts-v1/;
0010 #include "imx51.dtsi"
0011
0012 / {
0013 model = "Technologic Systems TS-4800";
0014 compatible = "technologic,imx51-ts4800", "fsl,imx51";
0015
0016 chosen {
0017 stdout-path = &uart1;
0018 };
0019
0020 memory@90000000 {
0021 device_type = "memory";
0022 reg = <0x90000000 0x10000000>;
0023 };
0024
0025 clocks {
0026 ckih1 {
0027 clock-frequency = <22579200>;
0028 };
0029
0030 ckih2 {
0031 clock-frequency = <24576000>;
0032 };
0033 };
0034
0035 backlight_reg: regulator-backlight {
0036 compatible = "regulator-fixed";
0037 pinctrl-names = "default";
0038 pinctrl-0 = <&pinctrl_enable_lcd>;
0039 regulator-name = "enable_lcd_reg";
0040 regulator-min-microvolt = <3300000>;
0041 regulator-max-microvolt = <3300000>;
0042 gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
0043 enable-active-high;
0044 };
0045
0046 backlight: backlight {
0047 compatible = "pwm-backlight";
0048 pwms = <&pwm1 0 78770>;
0049 brightness-levels = <0 150 200 255>;
0050 default-brightness-level = <1>;
0051 power-supply = <&backlight_reg>;
0052 };
0053
0054 display1: disp1 {
0055 compatible = "fsl,imx-parallel-display";
0056 interface-pix-fmt = "rgb24";
0057 pinctrl-names = "default";
0058 pinctrl-0 = <&pinctrl_lcd>;
0059
0060 display-timings {
0061 800x480p60 {
0062 native-mode;
0063 clock-frequency = <30066000>;
0064 hactive = <800>;
0065 vactive = <480>;
0066 hfront-porch = <50>;
0067 hback-porch = <70>;
0068 hsync-len = <50>;
0069 vback-porch = <0>;
0070 vfront-porch = <0>;
0071 vsync-len = <50>;
0072 };
0073 };
0074
0075 port {
0076 display0_in: endpoint {
0077 remote-endpoint = <&ipu_di0_disp1>;
0078 };
0079 };
0080 };
0081 };
0082
0083 &esdhc1 {
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_esdhc1>;
0086 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
0087 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
0088 status = "okay";
0089 };
0090
0091 &fec {
0092 pinctrl-names = "default";
0093 pinctrl-0 = <&pinctrl_fec>;
0094 phy-mode = "mii";
0095 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
0096 phy-reset-duration = <1>;
0097 status = "okay";
0098 };
0099
0100 &i2c2 {
0101 pinctrl-names = "default";
0102 pinctrl-0 = <&pinctrl_i2c2>;
0103 status = "okay";
0104
0105 rtc: rtc@68 {
0106 compatible = "st,m41t00";
0107 reg = <0x68>;
0108 };
0109 };
0110
0111 &ipu_di0_disp1 {
0112 remote-endpoint = <&display0_in>;
0113 };
0114
0115 &pwm1 {
0116 #pwm-cells = <2>;
0117 pinctrl-names = "default";
0118 pinctrl-0 = <&pinctrl_pwm_backlight>;
0119 status = "okay";
0120 };
0121
0122 &uart1 {
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_uart1>;
0125 status = "okay";
0126 };
0127
0128 &uart2 {
0129 pinctrl-names = "default";
0130 pinctrl-0 = <&pinctrl_uart2>;
0131 status = "okay";
0132 };
0133
0134 &uart3 {
0135 pinctrl-names = "default";
0136 pinctrl-0 = <&pinctrl_uart3>;
0137 status = "okay";
0138 };
0139
0140 &weim {
0141 pinctrl-names = "default";
0142 pinctrl-0 = <&pinctrl_weim>;
0143 status = "okay";
0144
0145 fpga@0 {
0146 compatible = "simple-bus";
0147 fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
0148 0x00000000 0x1c092480 0x00000000>;
0149 reg = <0 0x0000000 0x1d000>;
0150 #address-cells = <1>;
0151 #size-cells = <1>;
0152 ranges = <0 0 0 0x1d000>;
0153
0154 syscon: syscon@10000 {
0155 compatible = "syscon", "simple-mfd";
0156 reg = <0x10000 0x3d>;
0157 reg-io-width = <2>;
0158
0159 wdt {
0160 compatible = "technologic,ts4800-wdt";
0161 syscon = <&syscon 0xe>;
0162 };
0163 };
0164
0165 touchscreen@12000 {
0166 compatible = "technologic,ts4800-ts";
0167 reg = <0x12000 0x1000>;
0168 syscon = <&syscon 0x10 6>;
0169 };
0170
0171 fpga_irqc: fpga-irqc@15000 {
0172 compatible = "technologic,ts4800-irqc";
0173 reg = <0x15000 0x1000>;
0174 pinctrl-names = "default";
0175 pinctrl-0 = <&pinctrl_interrupt_fpga>;
0176 interrupt-parent = <&gpio2>;
0177 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
0178 interrupt-controller;
0179 #interrupt-cells = <1>;
0180 };
0181
0182 can@1a000 {
0183 compatible = "technologic,sja1000";
0184 reg = <0x1a000 0x100>;
0185 interrupt-parent = <&fpga_irqc>;
0186 interrupts = <1>;
0187 reg-io-width = <2>;
0188 nxp,tx-output-config = <0x06>;
0189 nxp,external-clock-frequency = <24000000>;
0190 };
0191 };
0192 };
0193
0194 &iomuxc {
0195 pinctrl_ecspi1: ecspi1grp {
0196 fsl,pins = <
0197 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
0198 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
0199 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
0200 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
0201 >;
0202 };
0203
0204 pinctrl_enable_lcd: enablelcdgrp {
0205 fsl,pins = <
0206 MX51_PAD_CSI2_D12__GPIO4_9 0x1c5
0207 >;
0208 };
0209
0210 pinctrl_esdhc1: esdhc1grp {
0211 fsl,pins = <
0212 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
0213 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
0214 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
0215 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
0216 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
0217 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
0218 MX51_PAD_GPIO1_0__GPIO1_0 0x100
0219 MX51_PAD_GPIO1_1__GPIO1_1 0x100
0220 >;
0221 };
0222
0223 pinctrl_fec: fecgrp {
0224 fsl,pins = <
0225 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
0226 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
0227 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
0228 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
0229 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
0230 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
0231 MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180
0232 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180
0233 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180
0234 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004
0235 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
0236 MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004
0237 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004
0238 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004
0239 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004
0240 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004
0241 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180
0242 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4
0243 MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
0244 >;
0245 };
0246
0247 pinctrl_i2c2: i2c2grp {
0248 fsl,pins = <
0249 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
0250 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
0251 >;
0252 };
0253
0254 pinctrl_interrupt_fpga: fpgaicgrp {
0255 fsl,pins = <
0256 MX51_PAD_EIM_D27__GPIO2_9 0xe5
0257 >;
0258 };
0259
0260 pinctrl_lcd: lcdgrp {
0261 fsl,pins = <
0262 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
0263 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
0264 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
0265 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
0266 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
0267 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
0268 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
0269 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
0270 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
0271 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
0272 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
0273 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
0274 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
0275 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
0276 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
0277 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
0278 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
0279 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
0280 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
0281 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
0282 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
0283 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
0284 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
0285 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
0286 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
0287 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
0288 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
0289 MX51_PAD_DI_GP4__DI2_PIN15 0x5
0290 >;
0291 };
0292
0293 pinctrl_pwm_backlight: backlightgrp {
0294 fsl,pins = <
0295 MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000
0296 >;
0297 };
0298
0299 pinctrl_uart1: uart1grp {
0300 fsl,pins = <
0301 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
0302 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
0303 >;
0304 };
0305
0306 pinctrl_uart2: uart2grp {
0307 fsl,pins = <
0308 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
0309 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
0310 >;
0311 };
0312
0313 pinctrl_uart3: uart3grp {
0314 fsl,pins = <
0315 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
0316 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
0317 >;
0318 };
0319
0320 pinctrl_weim: weimgrp {
0321 fsl,pins = <
0322 MX51_PAD_EIM_DTACK__EIM_DTACK 0x85
0323 MX51_PAD_EIM_CS0__EIM_CS0 0x0
0324 MX51_PAD_EIM_CS1__EIM_CS1 0x0
0325 MX51_PAD_EIM_EB0__EIM_EB0 0x85
0326 MX51_PAD_EIM_EB1__EIM_EB1 0x85
0327 MX51_PAD_EIM_OE__EIM_OE 0x85
0328 MX51_PAD_EIM_LBA__EIM_LBA 0x85
0329 >;
0330 };
0331 };
