0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0004 */
0005
0006 /dts-v1/;
0007 #include "imx51.dtsi"
0008
0009 / {
0010 model = "Digi ConnectCore CC(W)-MX51";
0011 compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
0012
0013 memory@90000000 {
0014 device_type = "memory";
0015 reg = <0x90000000 0x08000000>;
0016 };
0017 };
0018
0019 &ecspi1 {
0020 pinctrl-names = "default";
0021 pinctrl-0 = <&pinctrl_ecspi1>;
0022 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
0023 status = "okay";
0024
0025 pmic: mc13892@0 {
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pinctrl_mc13892>;
0028 compatible = "fsl,mc13892";
0029 spi-max-frequency = <16000000>;
0030 spi-cs-high;
0031 reg = <0>;
0032 interrupt-parent = <&gpio1>;
0033 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
0034
0035 regulators {
0036 sw1_reg: sw1 {
0037 regulator-min-microvolt = <1050000>;
0038 regulator-max-microvolt = <1100000>;
0039 regulator-boot-on;
0040 regulator-always-on;
0041 };
0042
0043 sw2_reg: sw2 {
0044 regulator-min-microvolt = <1175000>;
0045 regulator-max-microvolt = <1275000>;
0046 regulator-boot-on;
0047 regulator-always-on;
0048 };
0049
0050 sw3_reg: sw3 {
0051 regulator-min-microvolt = <1150000>;
0052 regulator-max-microvolt = <1350000>;
0053 regulator-boot-on;
0054 regulator-always-on;
0055 };
0056
0057 swbst_reg: swbst { };
0058
0059 viohi_reg: viohi {
0060 regulator-always-on;
0061 };
0062
0063 vpll_reg: vpll {
0064 regulator-min-microvolt = <1800000>;
0065 regulator-max-microvolt = <1800000>;
0066 regulator-always-on;
0067 };
0068
0069 vdig_reg: vdig {
0070 regulator-min-microvolt = <1250000>;
0071 regulator-max-microvolt = <1250000>;
0072 regulator-always-on;
0073 };
0074
0075 vsd_reg: vsd {
0076 regulator-min-microvolt = <3150000>;
0077 regulator-max-microvolt = <3150000>;
0078 regulator-always-on;
0079 };
0080
0081 vusb2_reg: vusb2 {
0082 regulator-min-microvolt = <2600000>;
0083 regulator-max-microvolt = <2600000>;
0084 regulator-always-on;
0085 };
0086
0087 vvideo_reg: vvideo {
0088 regulator-min-microvolt = <2775000>;
0089 regulator-max-microvolt = <2775000>;
0090 regulator-always-on;
0091 };
0092
0093 vaudio_reg: vaudio {
0094 regulator-min-microvolt = <3000000>;
0095 regulator-max-microvolt = <3000000>;
0096 regulator-always-on;
0097 };
0098
0099 vcam_reg: vcam {
0100 regulator-min-microvolt = <2750000>;
0101 regulator-max-microvolt = <2750000>;
0102 regulator-always-on;
0103 };
0104
0105 vgen3_reg: vgen3 {
0106 regulator-min-microvolt = <1800000>;
0107 regulator-max-microvolt = <1800000>;
0108 regulator-always-on;
0109 };
0110
0111 vusb_reg: vusb {
0112 regulator-always-on;
0113 };
0114
0115 gpo2_reg: gpo2 { };
0116
0117 gpo3_reg: gpo3 { };
0118
0119 gpo4_reg: gpo4 { };
0120
0121 pwgt2spi_reg: pwgt2spi {
0122 regulator-always-on;
0123 };
0124 };
0125 };
0126 };
0127
0128 &esdhc1 {
0129 pinctrl-names = "default";
0130 pinctrl-0 = <&pinctrl_esdhc1>;
0131 max-frequency = <50000000>;
0132 bus-width = <1>;
0133 };
0134
0135 &esdhc2 {
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&pinctrl_esdhc2>;
0138 cap-sdio-irq;
0139 wakeup-source;
0140 keep-power-in-suspend;
0141 max-frequency = <50000000>;
0142 no-1-8-v;
0143 non-removable;
0144 vmmc-supply = <&gpo4_reg>;
0145 status = "okay";
0146 };
0147
0148 &fec {
0149 pinctrl-names = "default";
0150 pinctrl-0 = <&pinctrl_fec>;
0151 phy-mode = "mii";
0152 phy-supply = <&gpo3_reg>;
0153 /* Pins shared with LCD2, keep status disabled */
0154 };
0155
0156 &i2c2 {
0157 pinctrl-names = "default", "gpio";
0158 pinctrl-0 = <&pinctrl_i2c2>;
0159 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0160 clock-frequency = <400000>;
0161 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
0162 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
0163 status = "okay";
0164
0165 mma7455l@1d {
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&pinctrl_mma7455l>;
0168 compatible = "fsl,mma7455l";
0169 reg = <0x1d>;
0170 interrupt-parent = <&gpio1>;
0171 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
0172 };
0173 };
0174
0175 &nfc {
0176 pinctrl-names = "default";
0177 pinctrl-0 = <&pinctrl_nfc>;
0178 nand-bus-width = <8>;
0179 nand-ecc-mode = "hw";
0180 nand-on-flash-bbt;
0181 status = "okay";
0182 };
0183
0184 &usbotg {
0185 phy_type = "utmi_wide";
0186 disable-over-current;
0187 vbus-supply = <&swbst_reg>;
0188 /* Device role is not known, keep status disabled */
0189 };
0190
0191 &weim {
0192 pinctrl-names = "default";
0193 pinctrl-0 = <&pinctrl_weim>;
0194 status = "okay";
0195
0196 lan9221: ethernet@5,0 {
0197 pinctrl-names = "default";
0198 pinctrl-0 = <&pinctrl_lan9221>;
0199 compatible = "smsc,lan9221", "smsc,lan9115";
0200 reg = <5 0x00000000 0x1000>;
0201 fsl,weim-cs-timing = <
0202 0x00420081 0x00000000
0203 0x32260000 0x00000000
0204 0x72080f00 0x00000000
0205 >;
0206 clocks = <&clks IMX5_CLK_DUMMY>;
0207 interrupt-parent = <&gpio1>;
0208 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
0209 phy-mode = "mii";
0210 reg-io-width = <2>;
0211 smsc,irq-push-pull;
0212 vdd33a-supply = <&gpo2_reg>;
0213 vddvario-supply = <&gpo2_reg>;
0214 };
0215 };
0216
0217 &iomuxc {
0218 imx51-digi-connectcore-som {
0219 pinctrl_ecspi1: ecspi1grp {
0220 fsl,pins = <
0221 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
0222 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
0223 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
0224 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
0225 >;
0226 };
0227
0228 pinctrl_esdhc1: esdhc1grp {
0229 fsl,pins = <
0230 MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5
0231 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
0232 MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5
0233 >;
0234 };
0235
0236 pinctrl_esdhc2: esdhc2grp {
0237 fsl,pins = <
0238 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
0239 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
0240 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
0241 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
0242 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
0243 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
0244 >;
0245 };
0246
0247 pinctrl_fec: fecgrp {
0248 fsl,pins = <
0249 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
0250 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
0251 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
0252 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
0253 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
0254 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
0255 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
0256 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
0257 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
0258 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
0259 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
0260 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
0261 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
0262 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
0263 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
0264 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
0265 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
0266 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
0267 >;
0268 };
0269
0270 pinctrl_i2c2: i2c2grp {
0271 fsl,pins = <
0272 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
0273 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
0274 >;
0275 };
0276
0277 pinctrl_i2c2_gpio: i2c2gpiogrp {
0278 fsl,pins = <
0279 MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed
0280 MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed
0281 >;
0282 };
0283
0284 pinctrl_nfc: nfcgrp {
0285 fsl,pins = <
0286 MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
0287 MX51_PAD_NANDF_D1__NANDF_D1 0x80000000
0288 MX51_PAD_NANDF_D2__NANDF_D2 0x80000000
0289 MX51_PAD_NANDF_D3__NANDF_D3 0x80000000
0290 MX51_PAD_NANDF_D4__NANDF_D4 0x80000000
0291 MX51_PAD_NANDF_D5__NANDF_D5 0x80000000
0292 MX51_PAD_NANDF_D6__NANDF_D6 0x80000000
0293 MX51_PAD_NANDF_D7__NANDF_D7 0x80000000
0294 MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000
0295 MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000
0296 MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000
0297 MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000
0298 MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000
0299 MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000
0300 MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000
0301 >;
0302 };
0303
0304 pinctrl_lan9221: lan9221grp {
0305 fsl,pins = <
0306 MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */
0307 >;
0308 };
0309
0310 pinctrl_mc13892: mc13892grp {
0311 fsl,pins = <
0312 MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
0313 >;
0314 };
0315
0316 pinctrl_mma7455l: mma7455lgrp {
0317 fsl,pins = <
0318 MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */
0319 MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */
0320 >;
0321 };
0322
0323 pinctrl_weim: weimgrp {
0324 fsl,pins = <
0325 MX51_PAD_EIM_DA0__EIM_DA0 0x80000000
0326 MX51_PAD_EIM_DA1__EIM_DA1 0x80000000
0327 MX51_PAD_EIM_DA2__EIM_DA2 0x80000000
0328 MX51_PAD_EIM_DA3__EIM_DA3 0x80000000
0329 MX51_PAD_EIM_DA4__EIM_DA4 0x80000000
0330 MX51_PAD_EIM_DA5__EIM_DA5 0x80000000
0331 MX51_PAD_EIM_DA6__EIM_DA6 0x80000000
0332 MX51_PAD_EIM_DA7__EIM_DA7 0x80000000
0333 MX51_PAD_EIM_DA8__EIM_DA8 0x80000000
0334 MX51_PAD_EIM_DA9__EIM_DA9 0x80000000
0335 MX51_PAD_EIM_DA10__EIM_DA10 0x80000000
0336 MX51_PAD_EIM_DA11__EIM_DA11 0x80000000
0337 MX51_PAD_EIM_DA12__EIM_DA12 0x80000000
0338 MX51_PAD_EIM_DA13__EIM_DA13 0x80000000
0339 MX51_PAD_EIM_DA14__EIM_DA14 0x80000000
0340 MX51_PAD_EIM_DA15__EIM_DA15 0x80000000
0341 MX51_PAD_EIM_A16__EIM_A16 0x80000000
0342 MX51_PAD_EIM_A17__EIM_A17 0x80000000
0343 MX51_PAD_EIM_A18__EIM_A18 0x80000000
0344 MX51_PAD_EIM_A19__EIM_A19 0x80000000
0345 MX51_PAD_EIM_A20__EIM_A20 0x80000000
0346 MX51_PAD_EIM_A21__EIM_A21 0x80000000
0347 MX51_PAD_EIM_A22__EIM_A22 0x80000000
0348 MX51_PAD_EIM_A23__EIM_A23 0x80000000
0349 MX51_PAD_EIM_A24__EIM_A24 0x80000000
0350 MX51_PAD_EIM_A25__EIM_A25 0x80000000
0351 MX51_PAD_EIM_A26__EIM_A26 0x80000000
0352 MX51_PAD_EIM_A27__EIM_A27 0x80000000
0353 MX51_PAD_EIM_D16__EIM_D16 0x80000000
0354 MX51_PAD_EIM_D17__EIM_D17 0x80000000
0355 MX51_PAD_EIM_D18__EIM_D18 0x80000000
0356 MX51_PAD_EIM_D19__EIM_D19 0x80000000
0357 MX51_PAD_EIM_D20__EIM_D20 0x80000000
0358 MX51_PAD_EIM_D21__EIM_D21 0x80000000
0359 MX51_PAD_EIM_D22__EIM_D22 0x80000000
0360 MX51_PAD_EIM_D23__EIM_D23 0x80000000
0361 MX51_PAD_EIM_D24__EIM_D24 0x80000000
0362 MX51_PAD_EIM_D25__EIM_D25 0x80000000
0363 MX51_PAD_EIM_D26__EIM_D26 0x80000000
0364 MX51_PAD_EIM_D27__EIM_D27 0x80000000
0365 MX51_PAD_EIM_D28__EIM_D28 0x80000000
0366 MX51_PAD_EIM_D29__EIM_D29 0x80000000
0367 MX51_PAD_EIM_D30__EIM_D30 0x80000000
0368 MX51_PAD_EIM_D31__EIM_D31 0x80000000
0369 MX51_PAD_EIM_OE__EIM_OE 0x80000000
0370 MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000
0371 MX51_PAD_EIM_LBA__EIM_LBA 0x80000000
0372 MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */
0373 >;
0374 };
0375 };
0376 };
