0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2013 Greg Ungerer <gerg@uclinux.org>
0004 // Copyright 2011 Freescale Semiconductor, Inc.
0005 // Copyright 2011 Linaro Ltd.
0006
0007 #include "imx50-pinfunc.h"
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/clock/imx5-clock.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 /*
0015 * The decompressor and also some bootloaders rely on a
0016 * pre-existing /chosen node to be available to insert the
0017 * command line and merge other ATAGS info.
0018 */
0019 chosen {};
0020
0021 aliases {
0022 ethernet0 = &fec;
0023 gpio0 = &gpio1;
0024 gpio1 = &gpio2;
0025 gpio2 = &gpio3;
0026 gpio3 = &gpio4;
0027 gpio4 = &gpio5;
0028 gpio5 = &gpio6;
0029 i2c0 = &i2c1;
0030 i2c1 = &i2c2;
0031 i2c2 = &i2c3;
0032 mmc0 = &esdhc1;
0033 mmc1 = &esdhc2;
0034 mmc2 = &esdhc3;
0035 mmc3 = &esdhc4;
0036 serial0 = &uart1;
0037 serial1 = &uart2;
0038 serial2 = &uart3;
0039 serial3 = &uart4;
0040 serial4 = &uart5;
0041 spi0 = &ecspi1;
0042 spi1 = &ecspi2;
0043 spi2 = &cspi;
0044 };
0045
0046 cpus {
0047 #address-cells = <1>;
0048 #size-cells = <0>;
0049 cpu@0 {
0050 device_type = "cpu";
0051 compatible = "arm,cortex-a8";
0052 reg = <0x0>;
0053 };
0054 };
0055
0056 tzic: tz-interrupt-controller@fffc000 {
0057 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
0058 interrupt-controller;
0059 #interrupt-cells = <1>;
0060 reg = <0x0fffc000 0x4000>;
0061 };
0062
0063 clocks {
0064 ckil {
0065 compatible = "fixed-clock";
0066 #clock-cells = <0>;
0067 clock-frequency = <32768>;
0068 };
0069
0070 ckih1 {
0071 compatible = "fixed-clock";
0072 #clock-cells = <0>;
0073 clock-frequency = <22579200>;
0074 };
0075
0076 ckih2 {
0077 compatible = "fixed-clock";
0078 #clock-cells = <0>;
0079 clock-frequency = <0>;
0080 };
0081
0082 osc {
0083 compatible = "fixed-clock";
0084 #clock-cells = <0>;
0085 clock-frequency = <24000000>;
0086 };
0087 };
0088
0089 usbphy0: usbphy-0 {
0090 compatible = "usb-nop-xceiv";
0091 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
0092 clock-names = "main_clk";
0093 #phy-cells = <0>;
0094 status = "okay";
0095 };
0096
0097 soc: soc {
0098 #address-cells = <1>;
0099 #size-cells = <1>;
0100 compatible = "simple-bus";
0101 interrupt-parent = <&tzic>;
0102 ranges;
0103
0104 aips1: bus@50000000 { /* AIPS1 */
0105 compatible = "fsl,aips-bus", "simple-bus";
0106 #address-cells = <1>;
0107 #size-cells = <1>;
0108 reg = <0x50000000 0x10000000>;
0109 ranges;
0110
0111 spba-bus@50000000 {
0112 compatible = "fsl,spba-bus", "simple-bus";
0113 #address-cells = <1>;
0114 #size-cells = <1>;
0115 reg = <0x50000000 0x40000>;
0116 ranges;
0117
0118 esdhc1: mmc@50004000 {
0119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
0120 reg = <0x50004000 0x4000>;
0121 interrupts = <1>;
0122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
0123 <&clks IMX5_CLK_DUMMY>,
0124 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
0125 clock-names = "ipg", "ahb", "per";
0126 bus-width = <4>;
0127 status = "disabled";
0128 };
0129
0130 esdhc2: mmc@50008000 {
0131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
0132 reg = <0x50008000 0x4000>;
0133 interrupts = <2>;
0134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
0135 <&clks IMX5_CLK_DUMMY>,
0136 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
0137 clock-names = "ipg", "ahb", "per";
0138 bus-width = <4>;
0139 status = "disabled";
0140 };
0141
0142 uart3: serial@5000c000 {
0143 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
0144 reg = <0x5000c000 0x4000>;
0145 interrupts = <33>;
0146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
0147 <&clks IMX5_CLK_UART3_PER_GATE>;
0148 clock-names = "ipg", "per";
0149 status = "disabled";
0150 };
0151
0152 ecspi1: spi@50010000 {
0153 #address-cells = <1>;
0154 #size-cells = <0>;
0155 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
0156 reg = <0x50010000 0x4000>;
0157 interrupts = <36>;
0158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
0159 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
0160 clock-names = "ipg", "per";
0161 status = "disabled";
0162 };
0163
0164 ssi2: ssi@50014000 {
0165 #sound-dai-cells = <0>;
0166 compatible = "fsl,imx50-ssi",
0167 "fsl,imx51-ssi",
0168 "fsl,imx21-ssi";
0169 reg = <0x50014000 0x4000>;
0170 interrupts = <30>;
0171 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
0172 dmas = <&sdma 24 1 0>,
0173 <&sdma 25 1 0>;
0174 dma-names = "rx", "tx";
0175 fsl,fifo-depth = <15>;
0176 status = "disabled";
0177 };
0178
0179 esdhc3: mmc@50020000 {
0180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
0181 reg = <0x50020000 0x4000>;
0182 interrupts = <3>;
0183 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
0184 <&clks IMX5_CLK_DUMMY>,
0185 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
0186 clock-names = "ipg", "ahb", "per";
0187 bus-width = <4>;
0188 status = "disabled";
0189 };
0190
0191 esdhc4: mmc@50024000 {
0192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
0193 reg = <0x50024000 0x4000>;
0194 interrupts = <4>;
0195 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
0196 <&clks IMX5_CLK_DUMMY>,
0197 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
0198 clock-names = "ipg", "ahb", "per";
0199 bus-width = <4>;
0200 status = "disabled";
0201 };
0202 };
0203
0204 usbotg: usb@53f80000 {
0205 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
0206 reg = <0x53f80000 0x0200>;
0207 interrupts = <18>;
0208 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
0209 fsl,usbphy = <&usbphy0>;
0210 status = "disabled";
0211 };
0212
0213 usbh1: usb@53f80200 {
0214 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
0215 reg = <0x53f80200 0x0200>;
0216 interrupts = <14>;
0217 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
0218 dr_mode = "host";
0219 status = "disabled";
0220 };
0221
0222 gpio1: gpio@53f84000 {
0223 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
0224 reg = <0x53f84000 0x4000>;
0225 interrupts = <50 51>;
0226 gpio-controller;
0227 #gpio-cells = <2>;
0228 interrupt-controller;
0229 #interrupt-cells = <2>;
0230 gpio-ranges = <&iomuxc 0 151 28>;
0231 };
0232
0233 gpio2: gpio@53f88000 {
0234 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
0235 reg = <0x53f88000 0x4000>;
0236 interrupts = <52 53>;
0237 gpio-controller;
0238 #gpio-cells = <2>;
0239 interrupt-controller;
0240 #interrupt-cells = <2>;
0241 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
0242 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
0243 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
0244 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
0245 };
0246
0247 gpio3: gpio@53f8c000 {
0248 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
0249 reg = <0x53f8c000 0x4000>;
0250 interrupts = <54 55>;
0251 gpio-controller;
0252 #gpio-cells = <2>;
0253 interrupt-controller;
0254 #interrupt-cells = <2>;
0255 gpio-ranges = <&iomuxc 0 108 32>;
0256 };
0257
0258 gpio4: gpio@53f90000 {
0259 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
0260 reg = <0x53f90000 0x4000>;
0261 interrupts = <56 57>;
0262 gpio-controller;
0263 #gpio-cells = <2>;
0264 interrupt-controller;
0265 #interrupt-cells = <2>;
0266 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
0267 <&iomuxc 20 140 11>;
0268 };
0269
0270 wdog1: watchdog@53f98000 {
0271 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
0272 reg = <0x53f98000 0x4000>;
0273 interrupts = <58>;
0274 clocks = <&clks IMX5_CLK_DUMMY>;
0275 };
0276
0277 gpt: timer@53fa0000 {
0278 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
0279 reg = <0x53fa0000 0x4000>;
0280 interrupts = <39>;
0281 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
0282 <&clks IMX5_CLK_GPT_HF_GATE>;
0283 clock-names = "ipg", "per";
0284 };
0285
0286 iomuxc: iomuxc@53fa8000 {
0287 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
0288 reg = <0x53fa8000 0x4000>;
0289 };
0290
0291 pwm1: pwm@53fb4000 {
0292 #pwm-cells = <3>;
0293 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
0294 reg = <0x53fb4000 0x4000>;
0295 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
0296 <&clks IMX5_CLK_PWM1_HF_GATE>;
0297 clock-names = "ipg", "per";
0298 interrupts = <61>;
0299 };
0300
0301 pwm2: pwm@53fb8000 {
0302 #pwm-cells = <3>;
0303 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
0304 reg = <0x53fb8000 0x4000>;
0305 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
0306 <&clks IMX5_CLK_PWM2_HF_GATE>;
0307 clock-names = "ipg", "per";
0308 interrupts = <94>;
0309 };
0310
0311 uart1: serial@53fbc000 {
0312 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
0313 reg = <0x53fbc000 0x4000>;
0314 interrupts = <31>;
0315 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
0316 <&clks IMX5_CLK_UART1_PER_GATE>;
0317 clock-names = "ipg", "per";
0318 status = "disabled";
0319 };
0320
0321 uart2: serial@53fc0000 {
0322 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
0323 reg = <0x53fc0000 0x4000>;
0324 interrupts = <32>;
0325 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
0326 <&clks IMX5_CLK_UART2_PER_GATE>;
0327 clock-names = "ipg", "per";
0328 status = "disabled";
0329 };
0330
0331 src: reset-controller@53fd0000 {
0332 compatible = "fsl,imx50-src", "fsl,imx51-src";
0333 reg = <0x53fd0000 0x4000>;
0334 interrupts = <75>;
0335 #reset-cells = <1>;
0336 };
0337
0338 clks: ccm@53fd4000{
0339 compatible = "fsl,imx50-ccm";
0340 reg = <0x53fd4000 0x4000>;
0341 interrupts = <0 71 0x04 0 72 0x04>;
0342 #clock-cells = <1>;
0343 };
0344
0345 gpio5: gpio@53fdc000 {
0346 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
0347 reg = <0x53fdc000 0x4000>;
0348 interrupts = <103 104>;
0349 gpio-controller;
0350 #gpio-cells = <2>;
0351 interrupt-controller;
0352 #interrupt-cells = <2>;
0353 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
0354 };
0355
0356 gpio6: gpio@53fe0000 {
0357 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
0358 reg = <0x53fe0000 0x4000>;
0359 interrupts = <105 106>;
0360 gpio-controller;
0361 #gpio-cells = <2>;
0362 interrupt-controller;
0363 #interrupt-cells = <2>;
0364 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
0365 };
0366
0367 i2c3: i2c@53fec000 {
0368 #address-cells = <1>;
0369 #size-cells = <0>;
0370 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
0371 reg = <0x53fec000 0x4000>;
0372 interrupts = <64>;
0373 clocks = <&clks IMX5_CLK_I2C3_GATE>;
0374 status = "disabled";
0375 };
0376
0377 uart4: serial@53ff0000 {
0378 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
0379 reg = <0x53ff0000 0x4000>;
0380 interrupts = <13>;
0381 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
0382 <&clks IMX5_CLK_UART4_PER_GATE>;
0383 clock-names = "ipg", "per";
0384 status = "disabled";
0385 };
0386 };
0387
0388 aips2: bus@60000000 { /* AIPS2 */
0389 compatible = "fsl,aips-bus", "simple-bus";
0390 #address-cells = <1>;
0391 #size-cells = <1>;
0392 reg = <0x60000000 0x10000000>;
0393 ranges;
0394
0395 uart5: serial@63f90000 {
0396 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
0397 reg = <0x63f90000 0x4000>;
0398 interrupts = <86>;
0399 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
0400 <&clks IMX5_CLK_UART5_PER_GATE>;
0401 clock-names = "ipg", "per";
0402 status = "disabled";
0403 };
0404
0405 owire: owire@63fa4000 {
0406 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
0407 reg = <0x63fa4000 0x4000>;
0408 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
0409 status = "disabled";
0410 };
0411
0412 ecspi2: spi@63fac000 {
0413 #address-cells = <1>;
0414 #size-cells = <0>;
0415 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
0416 reg = <0x63fac000 0x4000>;
0417 interrupts = <37>;
0418 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
0419 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
0420 clock-names = "ipg", "per";
0421 status = "disabled";
0422 };
0423
0424 sdma: sdma@63fb0000 {
0425 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
0426 reg = <0x63fb0000 0x4000>;
0427 interrupts = <6>;
0428 clocks = <&clks IMX5_CLK_SDMA_GATE>,
0429 <&clks IMX5_CLK_AHB>;
0430 clock-names = "ipg", "ahb";
0431 #dma-cells = <3>;
0432 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
0433 };
0434
0435 cspi: spi@63fc0000 {
0436 #address-cells = <1>;
0437 #size-cells = <0>;
0438 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
0439 reg = <0x63fc0000 0x4000>;
0440 interrupts = <38>;
0441 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
0442 <&clks IMX5_CLK_CSPI_IPG_GATE>;
0443 clock-names = "ipg", "per";
0444 status = "disabled";
0445 };
0446
0447 i2c2: i2c@63fc4000 {
0448 #address-cells = <1>;
0449 #size-cells = <0>;
0450 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
0451 reg = <0x63fc4000 0x4000>;
0452 interrupts = <63>;
0453 clocks = <&clks IMX5_CLK_I2C2_GATE>;
0454 status = "disabled";
0455 };
0456
0457 i2c1: i2c@63fc8000 {
0458 #address-cells = <1>;
0459 #size-cells = <0>;
0460 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
0461 reg = <0x63fc8000 0x4000>;
0462 interrupts = <62>;
0463 clocks = <&clks IMX5_CLK_I2C1_GATE>;
0464 status = "disabled";
0465 };
0466
0467 ssi1: ssi@63fcc000 {
0468 #sound-dai-cells = <0>;
0469 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
0470 "fsl,imx21-ssi";
0471 reg = <0x63fcc000 0x4000>;
0472 interrupts = <29>;
0473 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
0474 dmas = <&sdma 28 0 0>,
0475 <&sdma 29 0 0>;
0476 dma-names = "rx", "tx";
0477 fsl,fifo-depth = <15>;
0478 status = "disabled";
0479 };
0480
0481 audmux: audmux@63fd0000 {
0482 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
0483 reg = <0x63fd0000 0x4000>;
0484 status = "disabled";
0485 };
0486
0487 fec: ethernet@63fec000 {
0488 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
0489 reg = <0x63fec000 0x4000>;
0490 interrupts = <87>;
0491 clocks = <&clks IMX5_CLK_FEC_GATE>,
0492 <&clks IMX5_CLK_FEC_GATE>,
0493 <&clks IMX5_CLK_FEC_GATE>;
0494 clock-names = "ipg", "ahb", "ptp";
0495 status = "disabled";
0496 };
0497 };
0498 };
0499 };
