0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2013 Greg Ungerer <gerg@uclinux.org>
0004 // Copyright 2011 Freescale Semiconductor, Inc.
0005 // Copyright 2011 Linaro Ltd.
0006
0007 /dts-v1/;
0008 #include "imx50.dtsi"
0009
0010 / {
0011 model = "Freescale i.MX50 Evaluation Kit";
0012 compatible = "fsl,imx50-evk", "fsl,imx50";
0013
0014 memory@70000000 {
0015 device_type = "memory";
0016 reg = <0x70000000 0x80000000>;
0017 };
0018 };
0019
0020 &cspi {
0021 pinctrl-names = "default";
0022 pinctrl-0 = <&pinctrl_cspi>;
0023 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>;
0024 status = "okay";
0025
0026 flash: m25p32@1 {
0027 #address-cells = <1>;
0028 #size-cells = <1>;
0029 compatible = "m25p32", "jedec,spi-nor";
0030 spi-max-frequency = <25000000>;
0031 reg = <1>;
0032
0033 partition@0 {
0034 label = "bootloader";
0035 reg = <0x0 0x100000>;
0036 read-only;
0037 };
0038
0039 partition@100000 {
0040 label = "kernel";
0041 reg = <0x100000 0x300000>;
0042 };
0043 };
0044 };
0045
0046 &fec {
0047 pinctrl-names = "default";
0048 pinctrl-0 = <&pinctrl_fec>;
0049 phy-mode = "rmii";
0050 phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
0051 status = "okay";
0052 };
0053
0054 &iomuxc {
0055 imx50-evk {
0056 pinctrl_cspi: cspigrp {
0057 fsl,pins = <
0058 MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
0059 MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
0060 MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
0061 MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
0062 MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84
0063 >;
0064 };
0065
0066 pinctrl_fec: fecgrp {
0067 fsl,pins = <
0068 MX50_PAD_SSI_RXFS__FEC_MDC 0x80
0069 MX50_PAD_SSI_RXC__FEC_MDIO 0x80
0070 MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
0071 MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
0072 MX50_PAD_DISP_D2__FEC_RX_DV 0x80
0073 MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
0074 MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
0075 MX50_PAD_DISP_D5__FEC_TX_EN 0x80
0076 MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
0077 MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
0078 >;
0079 };
0080
0081 pinctrl_uart1: uart1grp {
0082 fsl,pins = <
0083 MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
0084 MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
0085 MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
0086 MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
0087 >;
0088 };
0089 };
0090 };
0091
0092 &uart1 {
0093 pinctrl-names = "default";
0094 pinctrl-0 = <&pinctrl_uart1>;
0095 status = "okay";
0096 };
0097
0098 &usbh1 {
0099 status = "okay";
0100 };
0101
0102 &usbotg {
0103 status = "okay";
0104 };
