0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2012 Sascha Hauer, Pengutronix
0004
0005 #include "imx27-pinfunc.h"
0006
0007 #include <dt-bindings/clock/imx27-clock.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/input.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 /*
0016 * The decompressor and also some bootloaders rely on a
0017 * pre-existing /chosen node to be available to insert the
0018 * command line and merge other ATAGS info.
0019 */
0020 chosen {};
0021
0022 aliases {
0023 ethernet0 = &fec;
0024 gpio0 = &gpio1;
0025 gpio1 = &gpio2;
0026 gpio2 = &gpio3;
0027 gpio3 = &gpio4;
0028 gpio4 = &gpio5;
0029 gpio5 = &gpio6;
0030 i2c0 = &i2c1;
0031 i2c1 = &i2c2;
0032 serial0 = &uart1;
0033 serial1 = &uart2;
0034 serial2 = &uart3;
0035 serial3 = &uart4;
0036 serial4 = &uart5;
0037 serial5 = &uart6;
0038 spi0 = &cspi1;
0039 spi1 = &cspi2;
0040 spi2 = &cspi3;
0041 };
0042
0043 aitc: aitc-interrupt-controller@10040000 {
0044 compatible = "fsl,imx27-aitc", "fsl,avic";
0045 interrupt-controller;
0046 #interrupt-cells = <1>;
0047 reg = <0x10040000 0x1000>;
0048 };
0049
0050 clocks {
0051 clk_osc26m: osc26m {
0052 compatible = "fsl,imx-osc26m", "fixed-clock";
0053 #clock-cells = <0>;
0054 clock-frequency = <26000000>;
0055 };
0056 };
0057
0058 cpus {
0059 #size-cells = <0>;
0060 #address-cells = <1>;
0061
0062 cpu: cpu@0 {
0063 device_type = "cpu";
0064 reg = <0>;
0065 compatible = "arm,arm926ej-s";
0066 operating-points = <
0067 /* kHz uV */
0068 266000 1300000
0069 399000 1450000
0070 >;
0071 clock-latency = <62500>;
0072 clocks = <&clks IMX27_CLK_CPU_DIV>;
0073 voltage-tolerance = <5>;
0074 };
0075 };
0076
0077 soc: soc {
0078 #address-cells = <1>;
0079 #size-cells = <1>;
0080 compatible = "simple-bus";
0081 interrupt-parent = <&aitc>;
0082 ranges;
0083
0084 aipi1: aipi@10000000 { /* AIPI1 */
0085 compatible = "fsl,aipi-bus", "simple-bus";
0086 #address-cells = <1>;
0087 #size-cells = <1>;
0088 reg = <0x10000000 0x20000>;
0089 ranges;
0090
0091 dma: dma@10001000 {
0092 compatible = "fsl,imx27-dma";
0093 reg = <0x10001000 0x1000>;
0094 interrupts = <32>;
0095 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
0096 <&clks IMX27_CLK_DMA_AHB_GATE>;
0097 clock-names = "ipg", "ahb";
0098 #dma-cells = <1>;
0099 dma-channels = <16>;
0100 };
0101
0102 wdog: watchdog@10002000 {
0103 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
0104 reg = <0x10002000 0x1000>;
0105 interrupts = <27>;
0106 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
0107 };
0108
0109 gpt1: timer@10003000 {
0110 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
0111 reg = <0x10003000 0x1000>;
0112 interrupts = <26>;
0113 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
0114 <&clks IMX27_CLK_PER1_GATE>;
0115 clock-names = "ipg", "per";
0116 };
0117
0118 gpt2: timer@10004000 {
0119 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
0120 reg = <0x10004000 0x1000>;
0121 interrupts = <25>;
0122 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
0123 <&clks IMX27_CLK_PER1_GATE>;
0124 clock-names = "ipg", "per";
0125 };
0126
0127 gpt3: timer@10005000 {
0128 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
0129 reg = <0x10005000 0x1000>;
0130 interrupts = <24>;
0131 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
0132 <&clks IMX27_CLK_PER1_GATE>;
0133 clock-names = "ipg", "per";
0134 };
0135
0136 pwm: pwm@10006000 {
0137 #pwm-cells = <3>;
0138 compatible = "fsl,imx27-pwm";
0139 reg = <0x10006000 0x1000>;
0140 interrupts = <23>;
0141 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
0142 <&clks IMX27_CLK_PER1_GATE>;
0143 clock-names = "ipg", "per";
0144 };
0145
0146 rtc: rtc@10007000 {
0147 compatible = "fsl,imx21-rtc";
0148 reg = <0x10007000 0x1000>;
0149 interrupts = <22>;
0150 clocks = <&clks IMX27_CLK_CKIL>,
0151 <&clks IMX27_CLK_RTC_IPG_GATE>;
0152 clock-names = "ref", "ipg";
0153 };
0154
0155 kpp: kpp@10008000 {
0156 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
0157 reg = <0x10008000 0x1000>;
0158 interrupts = <21>;
0159 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
0160 status = "disabled";
0161 };
0162
0163 owire: owire@10009000 {
0164 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
0165 reg = <0x10009000 0x1000>;
0166 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
0167 status = "disabled";
0168 };
0169
0170 uart1: serial@1000a000 {
0171 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
0172 reg = <0x1000a000 0x1000>;
0173 interrupts = <20>;
0174 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
0175 <&clks IMX27_CLK_PER1_GATE>;
0176 clock-names = "ipg", "per";
0177 status = "disabled";
0178 };
0179
0180 uart2: serial@1000b000 {
0181 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
0182 reg = <0x1000b000 0x1000>;
0183 interrupts = <19>;
0184 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
0185 <&clks IMX27_CLK_PER1_GATE>;
0186 clock-names = "ipg", "per";
0187 status = "disabled";
0188 };
0189
0190 uart3: serial@1000c000 {
0191 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
0192 reg = <0x1000c000 0x1000>;
0193 interrupts = <18>;
0194 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
0195 <&clks IMX27_CLK_PER1_GATE>;
0196 clock-names = "ipg", "per";
0197 status = "disabled";
0198 };
0199
0200 uart4: serial@1000d000 {
0201 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
0202 reg = <0x1000d000 0x1000>;
0203 interrupts = <17>;
0204 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
0205 <&clks IMX27_CLK_PER1_GATE>;
0206 clock-names = "ipg", "per";
0207 status = "disabled";
0208 };
0209
0210 cspi1: spi@1000e000 {
0211 #address-cells = <1>;
0212 #size-cells = <0>;
0213 compatible = "fsl,imx27-cspi";
0214 reg = <0x1000e000 0x1000>;
0215 interrupts = <16>;
0216 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
0217 <&clks IMX27_CLK_PER2_GATE>;
0218 clock-names = "ipg", "per";
0219 status = "disabled";
0220 };
0221
0222 cspi2: spi@1000f000 {
0223 #address-cells = <1>;
0224 #size-cells = <0>;
0225 compatible = "fsl,imx27-cspi";
0226 reg = <0x1000f000 0x1000>;
0227 interrupts = <15>;
0228 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
0229 <&clks IMX27_CLK_PER2_GATE>;
0230 clock-names = "ipg", "per";
0231 status = "disabled";
0232 };
0233
0234 ssi1: ssi@10010000 {
0235 #sound-dai-cells = <0>;
0236 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
0237 reg = <0x10010000 0x1000>;
0238 interrupts = <14>;
0239 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
0240 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
0241 dma-names = "rx0", "tx0", "rx1", "tx1";
0242 fsl,fifo-depth = <8>;
0243 status = "disabled";
0244 };
0245
0246 ssi2: ssi@10011000 {
0247 #sound-dai-cells = <0>;
0248 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
0249 reg = <0x10011000 0x1000>;
0250 interrupts = <13>;
0251 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
0252 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
0253 dma-names = "rx0", "tx0", "rx1", "tx1";
0254 fsl,fifo-depth = <8>;
0255 status = "disabled";
0256 };
0257
0258 i2c1: i2c@10012000 {
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
0262 reg = <0x10012000 0x1000>;
0263 interrupts = <12>;
0264 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
0265 status = "disabled";
0266 };
0267
0268 sdhci1: mmc@10013000 {
0269 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
0270 reg = <0x10013000 0x1000>;
0271 interrupts = <11>;
0272 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
0273 <&clks IMX27_CLK_PER2_GATE>;
0274 clock-names = "ipg", "per";
0275 dmas = <&dma 7>;
0276 dma-names = "rx-tx";
0277 status = "disabled";
0278 };
0279
0280 sdhci2: mmc@10014000 {
0281 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
0282 reg = <0x10014000 0x1000>;
0283 interrupts = <10>;
0284 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
0285 <&clks IMX27_CLK_PER2_GATE>;
0286 clock-names = "ipg", "per";
0287 dmas = <&dma 6>;
0288 dma-names = "rx-tx";
0289 status = "disabled";
0290 };
0291
0292 iomuxc: iomuxc@10015000 {
0293 compatible = "fsl,imx27-iomuxc";
0294 reg = <0x10015000 0x600>;
0295 #address-cells = <1>;
0296 #size-cells = <1>;
0297 ranges;
0298
0299 gpio1: gpio@10015000 {
0300 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
0301 reg = <0x10015000 0x100>;
0302 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
0303 interrupts = <8>;
0304 gpio-controller;
0305 #gpio-cells = <2>;
0306 interrupt-controller;
0307 #interrupt-cells = <2>;
0308 };
0309
0310 gpio2: gpio@10015100 {
0311 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
0312 reg = <0x10015100 0x100>;
0313 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
0314 interrupts = <8>;
0315 gpio-controller;
0316 #gpio-cells = <2>;
0317 interrupt-controller;
0318 #interrupt-cells = <2>;
0319 };
0320
0321 gpio3: gpio@10015200 {
0322 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
0323 reg = <0x10015200 0x100>;
0324 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
0325 interrupts = <8>;
0326 gpio-controller;
0327 #gpio-cells = <2>;
0328 interrupt-controller;
0329 #interrupt-cells = <2>;
0330 };
0331
0332 gpio4: gpio@10015300 {
0333 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
0334 reg = <0x10015300 0x100>;
0335 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
0336 interrupts = <8>;
0337 gpio-controller;
0338 #gpio-cells = <2>;
0339 interrupt-controller;
0340 #interrupt-cells = <2>;
0341 };
0342
0343 gpio5: gpio@10015400 {
0344 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
0345 reg = <0x10015400 0x100>;
0346 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
0347 interrupts = <8>;
0348 gpio-controller;
0349 #gpio-cells = <2>;
0350 interrupt-controller;
0351 #interrupt-cells = <2>;
0352 };
0353
0354 gpio6: gpio@10015500 {
0355 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
0356 reg = <0x10015500 0x100>;
0357 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
0358 interrupts = <8>;
0359 gpio-controller;
0360 #gpio-cells = <2>;
0361 interrupt-controller;
0362 #interrupt-cells = <2>;
0363 };
0364 };
0365
0366 audmux: audmux@10016000 {
0367 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
0368 reg = <0x10016000 0x1000>;
0369 clocks = <&clks IMX27_CLK_DUMMY>;
0370 clock-names = "audmux";
0371 status = "disabled";
0372 };
0373
0374 cspi3: spi@10017000 {
0375 #address-cells = <1>;
0376 #size-cells = <0>;
0377 compatible = "fsl,imx27-cspi";
0378 reg = <0x10017000 0x1000>;
0379 interrupts = <6>;
0380 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
0381 <&clks IMX27_CLK_PER2_GATE>;
0382 clock-names = "ipg", "per";
0383 status = "disabled";
0384 };
0385
0386 gpt4: timer@10019000 {
0387 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
0388 reg = <0x10019000 0x1000>;
0389 interrupts = <4>;
0390 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
0391 <&clks IMX27_CLK_PER1_GATE>;
0392 clock-names = "ipg", "per";
0393 };
0394
0395 gpt5: timer@1001a000 {
0396 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
0397 reg = <0x1001a000 0x1000>;
0398 interrupts = <3>;
0399 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
0400 <&clks IMX27_CLK_PER1_GATE>;
0401 clock-names = "ipg", "per";
0402 };
0403
0404 uart5: serial@1001b000 {
0405 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
0406 reg = <0x1001b000 0x1000>;
0407 interrupts = <49>;
0408 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
0409 <&clks IMX27_CLK_PER1_GATE>;
0410 clock-names = "ipg", "per";
0411 status = "disabled";
0412 };
0413
0414 uart6: serial@1001c000 {
0415 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
0416 reg = <0x1001c000 0x1000>;
0417 interrupts = <48>;
0418 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
0419 <&clks IMX27_CLK_PER1_GATE>;
0420 clock-names = "ipg", "per";
0421 status = "disabled";
0422 };
0423
0424 i2c2: i2c@1001d000 {
0425 #address-cells = <1>;
0426 #size-cells = <0>;
0427 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
0428 reg = <0x1001d000 0x1000>;
0429 interrupts = <1>;
0430 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
0431 status = "disabled";
0432 };
0433
0434 sdhci3: mmc@1001e000 {
0435 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
0436 reg = <0x1001e000 0x1000>;
0437 interrupts = <9>;
0438 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
0439 <&clks IMX27_CLK_PER2_GATE>;
0440 clock-names = "ipg", "per";
0441 dmas = <&dma 36>;
0442 dma-names = "rx-tx";
0443 status = "disabled";
0444 };
0445
0446 gpt6: timer@1001f000 {
0447 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
0448 reg = <0x1001f000 0x1000>;
0449 interrupts = <2>;
0450 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
0451 <&clks IMX27_CLK_PER1_GATE>;
0452 clock-names = "ipg", "per";
0453 };
0454 };
0455
0456 aipi2: aipi@10020000 { /* AIPI2 */
0457 compatible = "fsl,aipi-bus", "simple-bus";
0458 #address-cells = <1>;
0459 #size-cells = <1>;
0460 reg = <0x10020000 0x20000>;
0461 ranges;
0462
0463 fb: fb@10021000 {
0464 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
0465 interrupts = <61>;
0466 reg = <0x10021000 0x1000>;
0467 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
0468 <&clks IMX27_CLK_LCDC_AHB_GATE>,
0469 <&clks IMX27_CLK_PER3_GATE>;
0470 clock-names = "ipg", "ahb", "per";
0471 status = "disabled";
0472 };
0473
0474 coda: coda@10023000 {
0475 compatible = "fsl,imx27-vpu", "cnm,codadx6";
0476 reg = <0x10023000 0x0200>;
0477 interrupts = <53>;
0478 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
0479 <&clks IMX27_CLK_VPU_AHB_GATE>;
0480 clock-names = "per", "ahb";
0481 iram = <&iram>;
0482 };
0483
0484 usbotg: usb@10024000 {
0485 compatible = "fsl,imx27-usb";
0486 reg = <0x10024000 0x200>;
0487 interrupts = <56>;
0488 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
0489 <&clks IMX27_CLK_USB_AHB_GATE>,
0490 <&clks IMX27_CLK_USB_DIV>;
0491 clock-names = "ipg", "ahb", "per";
0492 fsl,usbmisc = <&usbmisc 0>;
0493 status = "disabled";
0494 };
0495
0496 usbh1: usb@10024200 {
0497 compatible = "fsl,imx27-usb";
0498 reg = <0x10024200 0x200>;
0499 interrupts = <54>;
0500 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
0501 <&clks IMX27_CLK_USB_AHB_GATE>,
0502 <&clks IMX27_CLK_USB_DIV>;
0503 clock-names = "ipg", "ahb", "per";
0504 fsl,usbmisc = <&usbmisc 1>;
0505 dr_mode = "host";
0506 status = "disabled";
0507 };
0508
0509 usbh2: usb@10024400 {
0510 compatible = "fsl,imx27-usb";
0511 reg = <0x10024400 0x200>;
0512 interrupts = <55>;
0513 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
0514 <&clks IMX27_CLK_USB_AHB_GATE>,
0515 <&clks IMX27_CLK_USB_DIV>;
0516 clock-names = "ipg", "ahb", "per";
0517 fsl,usbmisc = <&usbmisc 2>;
0518 dr_mode = "host";
0519 status = "disabled";
0520 };
0521
0522 usbmisc: usbmisc@10024600 {
0523 #index-cells = <1>;
0524 compatible = "fsl,imx27-usbmisc";
0525 reg = <0x10024600 0x200>;
0526 };
0527
0528 sahara2: crypto@10025000 {
0529 compatible = "fsl,imx27-sahara";
0530 reg = <0x10025000 0x1000>;
0531 interrupts = <59>;
0532 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
0533 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
0534 clock-names = "ipg", "ahb";
0535 };
0536
0537 clks: ccm@10027000{
0538 compatible = "fsl,imx27-ccm";
0539 reg = <0x10027000 0x1000>;
0540 #clock-cells = <1>;
0541 };
0542
0543 iim: efuse@10028000 {
0544 compatible = "fsl,imx27-iim";
0545 reg = <0x10028000 0x1000>;
0546 interrupts = <62>;
0547 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
0548 };
0549
0550 fec: ethernet@1002b000 {
0551 compatible = "fsl,imx27-fec";
0552 reg = <0x1002b000 0x1000>;
0553 interrupts = <50>;
0554 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
0555 <&clks IMX27_CLK_FEC_AHB_GATE>;
0556 clock-names = "ipg", "ahb";
0557 status = "disabled";
0558 };
0559 };
0560
0561 nfc: nand-controller@d8000000 {
0562 #address-cells = <1>;
0563 #size-cells = <1>;
0564 compatible = "fsl,imx27-nand";
0565 reg = <0xd8000000 0x1000>;
0566 interrupts = <29>;
0567 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
0568 status = "disabled";
0569 };
0570
0571 weim: weim@d8002000 {
0572 #address-cells = <2>;
0573 #size-cells = <1>;
0574 compatible = "fsl,imx27-weim";
0575 reg = <0xd8002000 0x1000>;
0576 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
0577 ranges = <
0578 0 0 0xc0000000 0x08000000
0579 1 0 0xc8000000 0x08000000
0580 2 0 0xd0000000 0x02000000
0581 3 0 0xd2000000 0x02000000
0582 4 0 0xd4000000 0x02000000
0583 5 0 0xd6000000 0x02000000
0584 >;
0585 status = "disabled";
0586 };
0587
0588 iram: sram@ffff4c00 {
0589 compatible = "mmio-sram";
0590 reg = <0xffff4c00 0xb400>;
0591 };
0592 };
0593 };
