OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0004
0005 #include "imx1-pinfunc.h"
0006
0007 #include <dt-bindings/clock/imx1-clock.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 /*
0015 * The decompressor and also some bootloaders rely on a
0016 * pre-existing /chosen node to be available to insert the
0017 * command line and merge other ATAGS info.
0018 */
0019 chosen {};
0020
0021 aliases {
0022 gpio0 = &gpio1;
0023 gpio1 = &gpio2;
0024 gpio2 = &gpio3;
0025 gpio3 = &gpio4;
0026 i2c0 = &i2c;
0027 serial0 = &uart1;
0028 serial1 = &uart2;
0029 serial2 = &uart3;
0030 spi0 = &cspi1;
0031 spi1 = &cspi2;
0032 };
0033
0034 aitc: aitc-interrupt-controller@223000 {
0035 compatible = "fsl,imx1-aitc", "fsl,avic";
0036 interrupt-controller;
0037 #interrupt-cells = <1>;
0038 reg = <0x00223000 0x1000>;
0039 };
0040
0041 cpus {
0042 #size-cells = <0>;
0043 #address-cells = <1>;
0044
0045 cpu@0 {
0046 device_type = "cpu";
0047 reg = <0>;
0048 compatible = "arm,arm920t";
0049 operating-points = <200000 1900000>;
0050 clock-latency = <62500>;
0051 clocks = <&clks IMX1_CLK_MCU>;
0052 voltage-tolerance = <5>;
0053 };
0054 };
0055
0056 clocks {
0057 clk32 {
0058 compatible = "fixed-clock";
0059 #clock-cells = <0>;
0060 clock-frequency = <32000>;
0061 };
0062 };
0063
0064 soc {
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067 compatible = "simple-bus";
0068 interrupt-parent = <&aitc>;
0069 ranges;
0070
0071 aipi@200000 {
0072 compatible = "fsl,aipi-bus", "simple-bus";
0073 #address-cells = <1>;
0074 #size-cells = <1>;
0075 reg = <0x00200000 0x10000>;
0076 ranges;
0077
0078 gpt1: timer@202000 {
0079 compatible = "fsl,imx1-gpt";
0080 reg = <0x00202000 0x1000>;
0081 interrupts = <59>;
0082 clocks = <&clks IMX1_CLK_HCLK>,
0083 <&clks IMX1_CLK_PER1>;
0084 clock-names = "ipg", "per";
0085 };
0086
0087 gpt2: timer@203000 {
0088 compatible = "fsl,imx1-gpt";
0089 reg = <0x00203000 0x1000>;
0090 interrupts = <58>;
0091 clocks = <&clks IMX1_CLK_HCLK>,
0092 <&clks IMX1_CLK_PER1>;
0093 clock-names = "ipg", "per";
0094 };
0095
0096 fb: fb@205000 {
0097 compatible = "fsl,imx1-fb";
0098 reg = <0x00205000 0x1000>;
0099 interrupts = <14>;
0100 clocks = <&clks IMX1_CLK_DUMMY>,
0101 <&clks IMX1_CLK_DUMMY>,
0102 <&clks IMX1_CLK_PER2>;
0103 clock-names = "ipg", "ahb", "per";
0104 status = "disabled";
0105 };
0106
0107 uart1: serial@206000 {
0108 compatible = "fsl,imx1-uart";
0109 reg = <0x00206000 0x1000>;
0110 interrupts = <30 29 26>;
0111 clocks = <&clks IMX1_CLK_HCLK>,
0112 <&clks IMX1_CLK_PER1>;
0113 clock-names = "ipg", "per";
0114 status = "disabled";
0115 };
0116
0117 uart2: serial@207000 {
0118 compatible = "fsl,imx1-uart";
0119 reg = <0x00207000 0x1000>;
0120 interrupts = <24 23 20>;
0121 clocks = <&clks IMX1_CLK_HCLK>,
0122 <&clks IMX1_CLK_PER1>;
0123 clock-names = "ipg", "per";
0124 status = "disabled";
0125 };
0126
0127 pwm: pwm@208000 {
0128 #pwm-cells = <3>;
0129 compatible = "fsl,imx1-pwm";
0130 reg = <0x00208000 0x1000>;
0131 interrupts = <34>;
0132 clocks = <&clks IMX1_CLK_DUMMY>,
0133 <&clks IMX1_CLK_PER1>;
0134 clock-names = "ipg", "per";
0135 };
0136
0137 dma: dma@209000 {
0138 compatible = "fsl,imx1-dma";
0139 reg = <0x00209000 0x1000>;
0140 interrupts = <61 60>;
0141 clocks = <&clks IMX1_CLK_HCLK>,
0142 <&clks IMX1_CLK_DMA_GATE>;
0143 clock-names = "ipg", "ahb";
0144 #dma-cells = <1>;
0145 };
0146
0147 uart3: serial@20a000 {
0148 compatible = "fsl,imx1-uart";
0149 reg = <0x0020a000 0x1000>;
0150 interrupts = <54 4 1>;
0151 clocks = <&clks IMX1_CLK_UART3_GATE>,
0152 <&clks IMX1_CLK_PER1>;
0153 clock-names = "ipg", "per";
0154 status = "disabled";
0155 };
0156 };
0157
0158 aipi@210000 {
0159 compatible = "fsl,aipi-bus", "simple-bus";
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162 reg = <0x00210000 0x10000>;
0163 ranges;
0164
0165 cspi1: spi@213000 {
0166 #address-cells = <1>;
0167 #size-cells = <0>;
0168 compatible = "fsl,imx1-cspi";
0169 reg = <0x00213000 0x1000>;
0170 interrupts = <41>;
0171 clocks = <&clks IMX1_CLK_DUMMY>,
0172 <&clks IMX1_CLK_PER1>;
0173 clock-names = "ipg", "per";
0174 status = "disabled";
0175 };
0176
0177 i2c: i2c@217000 {
0178 #address-cells = <1>;
0179 #size-cells = <0>;
0180 compatible = "fsl,imx1-i2c";
0181 reg = <0x00217000 0x1000>;
0182 interrupts = <39>;
0183 clocks = <&clks IMX1_CLK_HCLK>;
0184 status = "disabled";
0185 };
0186
0187 cspi2: spi@219000 {
0188 #address-cells = <1>;
0189 #size-cells = <0>;
0190 compatible = "fsl,imx1-cspi";
0191 reg = <0x00219000 0x1000>;
0192 interrupts = <40>;
0193 clocks = <&clks IMX1_CLK_DUMMY>,
0194 <&clks IMX1_CLK_PER1>;
0195 clock-names = "ipg", "per";
0196 status = "disabled";
0197 };
0198
0199 clks: ccm@21b000 {
0200 compatible = "fsl,imx1-ccm";
0201 reg = <0x0021b000 0x1000>;
0202 #clock-cells = <1>;
0203 };
0204
0205 iomuxc: iomuxc@21c000 {
0206 compatible = "fsl,imx1-iomuxc";
0207 reg = <0x0021c000 0x1000>;
0208 #address-cells = <1>;
0209 #size-cells = <1>;
0210 ranges;
0211
0212 gpio1: gpio@21c000 {
0213 compatible = "fsl,imx1-gpio";
0214 reg = <0x0021c000 0x100>;
0215 interrupts = <11>;
0216 gpio-controller;
0217 #gpio-cells = <2>;
0218 interrupt-controller;
0219 #interrupt-cells = <2>;
0220 };
0221
0222 gpio2: gpio@21c100 {
0223 compatible = "fsl,imx1-gpio";
0224 reg = <0x0021c100 0x100>;
0225 interrupts = <12>;
0226 gpio-controller;
0227 #gpio-cells = <2>;
0228 interrupt-controller;
0229 #interrupt-cells = <2>;
0230 };
0231
0232 gpio3: gpio@21c200 {
0233 compatible = "fsl,imx1-gpio";
0234 reg = <0x0021c200 0x100>;
0235 interrupts = <13>;
0236 gpio-controller;
0237 #gpio-cells = <2>;
0238 interrupt-controller;
0239 #interrupt-cells = <2>;
0240 };
0241
0242 gpio4: gpio@21c300 {
0243 compatible = "fsl,imx1-gpio";
0244 reg = <0x0021c300 0x100>;
0245 interrupts = <62>;
0246 gpio-controller;
0247 #gpio-cells = <2>;
0248 interrupt-controller;
0249 #interrupt-cells = <2>;
0250 };
0251 };
0252 };
0253
0254 weim: weim@220000 {
0255 #address-cells = <2>;
0256 #size-cells = <1>;
0257 compatible = "fsl,imx1-weim";
0258 reg = <0x00220000 0x1000>;
0259 clocks = <&clks IMX1_CLK_DUMMY>;
0260 ranges = <
0261 0 0 0x10000000 0x02000000
0262 1 0 0x12000000 0x01000000
0263 2 0 0x13000000 0x01000000
0264 3 0 0x14000000 0x01000000
0265 4 0 0x15000000 0x01000000
0266 5 0 0x16000000 0x01000000
0267 >;
0268 status = "disabled";
0269 };
0270
0271 esram: esram@300000 {
0272 compatible = "mmio-sram";
0273 reg = <0x00300000 0x20000>;
0274 };
0275 };
0276 };
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