0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0004 */
0005
0006 /dts-v1/;
0007 #include "imx1.dtsi"
0008
0009 / {
0010 model = "Armadeus APF9328";
0011 compatible = "armadeus,imx1-apf9328", "fsl,imx1";
0012
0013 chosen {
0014 stdout-path = &uart1;
0015 };
0016
0017 memory@8000000 {
0018 device_type = "memory";
0019 reg = <0x08000000 0x00800000>;
0020 };
0021 };
0022
0023 &i2c {
0024 pinctrl-names = "default";
0025 pinctrl-0 = <&pinctrl_i2c>;
0026 status = "okay";
0027 };
0028
0029 &uart1 {
0030 pinctrl-names = "default";
0031 pinctrl-0 = <&pinctrl_uart1>;
0032 uart-has-rtscts;
0033 status = "okay";
0034 };
0035
0036 &uart2 {
0037 pinctrl-names = "default";
0038 pinctrl-0 = <&pinctrl_uart2>;
0039 uart-has-rtscts;
0040 status = "okay";
0041 };
0042
0043 &weim {
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&pinctrl_weim>;
0046 status = "okay";
0047
0048 nor: nor@0,0 {
0049 compatible = "cfi-flash";
0050 reg = <0 0x00000000 0x02000000>;
0051 bank-width = <2>;
0052 fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055 };
0056
0057 eth: eth@4,c00000 {
0058 pinctrl-names = "default";
0059 pinctrl-0 = <&pinctrl_eth>;
0060 compatible = "davicom,dm9000";
0061 reg = <
0062 4 0x00c00000 0x2
0063 4 0x00c00002 0x2
0064 >;
0065 interrupt-parent = <&gpio2>;
0066 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
0067 fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
0068 };
0069 };
0070
0071 &iomuxc {
0072 imx1-apf9328 {
0073 pinctrl_eth: ethgrp {
0074 fsl,pins = <
0075 MX1_PAD_SIM_SVEN__GPIO2_14 0x0
0076 >;
0077 };
0078
0079 pinctrl_i2c: i2cgrp {
0080 fsl,pins = <
0081 MX1_PAD_I2C_SCL__I2C_SCL 0x0
0082 MX1_PAD_I2C_SDA__I2C_SDA 0x0
0083 >;
0084 };
0085
0086 pinctrl_uart1: uart1grp {
0087 fsl,pins = <
0088 MX1_PAD_UART1_TXD__UART1_TXD 0x0
0089 MX1_PAD_UART1_RXD__UART1_RXD 0x0
0090 MX1_PAD_UART1_CTS__UART1_CTS 0x0
0091 MX1_PAD_UART1_RTS__UART1_RTS 0x0
0092 >;
0093 };
0094
0095 pinctrl_uart2: uart2grp {
0096 fsl,pins = <
0097 MX1_PAD_UART2_TXD__UART2_TXD 0x0
0098 MX1_PAD_UART2_RXD__UART2_RXD 0x0
0099 MX1_PAD_UART2_CTS__UART2_CTS 0x0
0100 MX1_PAD_UART2_RTS__UART2_RTS 0x0
0101 >;
0102 };
0103
0104 pinctrl_weim: weimgrp {
0105 fsl,pins = <
0106 MX1_PAD_A0__A0 0x0
0107 MX1_PAD_A16__A16 0x0
0108 MX1_PAD_A17__A17 0x0
0109 MX1_PAD_A18__A18 0x0
0110 MX1_PAD_A19__A19 0x0
0111 MX1_PAD_A20__A20 0x0
0112 MX1_PAD_A21__A21 0x0
0113 MX1_PAD_A22__A22 0x0
0114 MX1_PAD_A23__A23 0x0
0115 MX1_PAD_A24__A24 0x0
0116 MX1_PAD_BCLK__BCLK 0x0
0117 MX1_PAD_CS4__CS4 0x0
0118 MX1_PAD_DTACK__DTACK 0x0
0119 MX1_PAD_ECB__ECB 0x0
0120 MX1_PAD_LBA__LBA 0x0
0121 >;
0122 };
0123 };
0124 };
