0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0004 */
0005
0006 /dts-v1/;
0007 #include "imx1.dtsi"
0008
0009 / {
0010 model = "Freescale MX1 ADS";
0011 compatible = "fsl,imx1ads", "fsl,imx1";
0012
0013 chosen {
0014 stdout-path = &uart1;
0015 };
0016
0017 memory@8000000 {
0018 device_type = "memory";
0019 reg = <0x08000000 0x04000000>;
0020 };
0021 };
0022
0023 &cspi1 {
0024 pinctrl-0 = <&pinctrl_cspi1>;
0025 cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
0026 status = "okay";
0027 };
0028
0029 &i2c {
0030 pinctrl-names = "default";
0031 pinctrl-0 = <&pinctrl_i2c>;
0032 status = "okay";
0033
0034 extgpio0: pcf8575@22 {
0035 compatible = "nxp,pcf8575";
0036 reg = <0x22>;
0037 gpio-controller;
0038 #gpio-cells = <2>;
0039 };
0040
0041 extgpio1: pcf8575@24 {
0042 compatible = "nxp,pcf8575";
0043 reg = <0x24>;
0044 gpio-controller;
0045 #gpio-cells = <2>;
0046 };
0047 };
0048
0049 &uart1 {
0050 pinctrl-names = "default";
0051 pinctrl-0 = <&pinctrl_uart1>;
0052 uart-has-rtscts;
0053 status = "okay";
0054 };
0055
0056 &uart2 {
0057 pinctrl-names = "default";
0058 pinctrl-0 = <&pinctrl_uart2>;
0059 uart-has-rtscts;
0060 status = "okay";
0061 };
0062
0063 &weim {
0064 pinctrl-names = "default";
0065 pinctrl-0 = <&pinctrl_weim>;
0066 status = "okay";
0067
0068 nor: nor@0,0 {
0069 compatible = "cfi-flash";
0070 reg = <0 0x00000000 0x02000000>;
0071 bank-width = <4>;
0072 fsl,weim-cs-timing = <0x00003e00 0x00000801>;
0073 #address-cells = <1>;
0074 #size-cells = <1>;
0075 };
0076 };
0077
0078 &iomuxc {
0079 imx1-ads {
0080 pinctrl_cspi1: cspi1grp {
0081 fsl,pins = <
0082 MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
0083 MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
0084 MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
0085 MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
0086 MX1_PAD_SPI1_SS__GPIO3_15 0x0
0087 >;
0088 };
0089
0090 pinctrl_i2c: i2cgrp {
0091 fsl,pins = <
0092 MX1_PAD_I2C_SCL__I2C_SCL 0x0
0093 MX1_PAD_I2C_SDA__I2C_SDA 0x0
0094 >;
0095 };
0096
0097 pinctrl_uart1: uart1grp {
0098 fsl,pins = <
0099 MX1_PAD_UART1_TXD__UART1_TXD 0x0
0100 MX1_PAD_UART1_RXD__UART1_RXD 0x0
0101 MX1_PAD_UART1_CTS__UART1_CTS 0x0
0102 MX1_PAD_UART1_RTS__UART1_RTS 0x0
0103 >;
0104 };
0105
0106 pinctrl_uart2: uart2grp {
0107 fsl,pins = <
0108 MX1_PAD_UART2_TXD__UART2_TXD 0x0
0109 MX1_PAD_UART2_RXD__UART2_RXD 0x0
0110 MX1_PAD_UART2_CTS__UART2_CTS 0x0
0111 MX1_PAD_UART2_RTS__UART2_RTS 0x0
0112 >;
0113 };
0114
0115 pinctrl_weim: weimgrp {
0116 fsl,pins = <
0117 MX1_PAD_A0__A0 0x0
0118 MX1_PAD_A16__A16 0x0
0119 MX1_PAD_A17__A17 0x0
0120 MX1_PAD_A18__A18 0x0
0121 MX1_PAD_A19__A19 0x0
0122 MX1_PAD_A20__A20 0x0
0123 MX1_PAD_A21__A21 0x0
0124 MX1_PAD_A22__A22 0x0
0125 MX1_PAD_A23__A23 0x0
0126 MX1_PAD_A24__A24 0x0
0127 MX1_PAD_BCLK__BCLK 0x0
0128 MX1_PAD_CS4__CS4 0x0
0129 MX1_PAD_DTACK__DTACK 0x0
0130 MX1_PAD_ECB__ECB 0x0
0131 MX1_PAD_LBA__LBA 0x0
0132 >;
0133 };
0134 };
0135 };
