0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2013-2014 Linaro Ltd.
0004 * Copyright (c) 2013-2014 HiSilicon Limited.
0005 */
0006
0007 #include <dt-bindings/clock/hix5hd2-clock.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 aliases {
0014 serial0 = &uart0;
0015 };
0016
0017 gic: interrupt-controller@f8a01000 {
0018 compatible = "arm,cortex-a9-gic";
0019 #interrupt-cells = <3>;
0020 #address-cells = <0>;
0021 interrupt-controller;
0022 /* gic dist base, gic cpu base */
0023 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
0024 };
0025
0026 soc {
0027 #address-cells = <1>;
0028 #size-cells = <1>;
0029 compatible = "simple-bus";
0030 interrupt-parent = <&gic>;
0031 ranges = <0 0xf8000000 0x8000000>;
0032
0033 amba-bus {
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 compatible = "simple-bus";
0037 ranges;
0038
0039 timer0: timer@2000 {
0040 compatible = "arm,sp804", "arm,primecell";
0041 reg = <0x00002000 0x1000>;
0042 /* timer00 & timer01 */
0043 interrupts = <0 24 4>;
0044 clocks = <&clock HIX5HD2_FIXED_24M>;
0045 status = "disabled";
0046 };
0047
0048 timer1: timer@a29000 {
0049 /*
0050 * Only used in NORMAL state, not available ins
0051 * SLOW or DOZE state.
0052 * The rate is fixed in 24MHz.
0053 */
0054 compatible = "arm,sp804", "arm,primecell";
0055 reg = <0x00a29000 0x1000>;
0056 /* timer10 & timer11 */
0057 interrupts = <0 25 4>;
0058 clocks = <&clock HIX5HD2_FIXED_24M>;
0059 status = "disabled";
0060 };
0061
0062 timer2: timer@a2a000 {
0063 compatible = "arm,sp804", "arm,primecell";
0064 reg = <0x00a2a000 0x1000>;
0065 /* timer20 & timer21 */
0066 interrupts = <0 26 4>;
0067 clocks = <&clock HIX5HD2_FIXED_24M>;
0068 status = "disabled";
0069 };
0070
0071 timer3: timer@a2b000 {
0072 compatible = "arm,sp804", "arm,primecell";
0073 reg = <0x00a2b000 0x1000>;
0074 /* timer30 & timer31 */
0075 interrupts = <0 27 4>;
0076 clocks = <&clock HIX5HD2_FIXED_24M>;
0077 status = "disabled";
0078 };
0079
0080 timer4: timer@a81000 {
0081 compatible = "arm,sp804", "arm,primecell";
0082 reg = <0x00a81000 0x1000>;
0083 /* timer30 & timer31 */
0084 interrupts = <0 28 4>;
0085 clocks = <&clock HIX5HD2_FIXED_24M>;
0086 status = "disabled";
0087 };
0088
0089 uart0: serial@b00000 {
0090 compatible = "arm,pl011", "arm,primecell";
0091 reg = <0x00b00000 0x1000>;
0092 interrupts = <0 49 4>;
0093 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
0094 clock-names = "uartclk", "apb_pclk";
0095 status = "disabled";
0096 };
0097
0098 uart1: serial@6000 {
0099 compatible = "arm,pl011", "arm,primecell";
0100 reg = <0x00006000 0x1000>;
0101 interrupts = <0 50 4>;
0102 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
0103 clock-names = "uartclk", "apb_pclk";
0104 status = "disabled";
0105 };
0106
0107 uart2: serial@b02000 {
0108 compatible = "arm,pl011", "arm,primecell";
0109 reg = <0x00b02000 0x1000>;
0110 interrupts = <0 51 4>;
0111 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
0112 clock-names = "uartclk", "apb_pclk";
0113 status = "disabled";
0114 };
0115
0116 uart3: serial@b03000 {
0117 compatible = "arm,pl011", "arm,primecell";
0118 reg = <0x00b03000 0x1000>;
0119 interrupts = <0 52 4>;
0120 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
0121 clock-names = "uartclk", "apb_pclk";
0122 status = "disabled";
0123 };
0124
0125 uart4: serial@b04000 {
0126 compatible = "arm,pl011", "arm,primecell";
0127 reg = <0xb04000 0x1000>;
0128 interrupts = <0 53 4>;
0129 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
0130 clock-names = "uartclk", "apb_pclk";
0131 status = "disabled";
0132 };
0133
0134 gpio0: gpio@b20000 {
0135 compatible = "arm,pl061", "arm,primecell";
0136 reg = <0xb20000 0x1000>;
0137 interrupts = <0 108 0x4>;
0138 gpio-controller;
0139 #gpio-cells = <2>;
0140 clocks = <&clock HIX5HD2_FIXED_100M>;
0141 clock-names = "apb_pclk";
0142 interrupt-controller;
0143 #interrupt-cells = <2>;
0144 status = "disabled";
0145 };
0146
0147 gpio1: gpio@b21000 {
0148 compatible = "arm,pl061", "arm,primecell";
0149 reg = <0xb21000 0x1000>;
0150 interrupts = <0 109 0x4>;
0151 gpio-controller;
0152 #gpio-cells = <2>;
0153 clocks = <&clock HIX5HD2_FIXED_100M>;
0154 clock-names = "apb_pclk";
0155 interrupt-controller;
0156 #interrupt-cells = <2>;
0157 status = "disabled";
0158 };
0159
0160 gpio2: gpio@b22000 {
0161 compatible = "arm,pl061", "arm,primecell";
0162 reg = <0xb22000 0x1000>;
0163 interrupts = <0 110 0x4>;
0164 gpio-controller;
0165 #gpio-cells = <2>;
0166 clocks = <&clock HIX5HD2_FIXED_100M>;
0167 clock-names = "apb_pclk";
0168 interrupt-controller;
0169 #interrupt-cells = <2>;
0170 status = "disabled";
0171 };
0172
0173 gpio3: gpio@b23000 {
0174 compatible = "arm,pl061", "arm,primecell";
0175 reg = <0xb23000 0x1000>;
0176 interrupts = <0 111 0x4>;
0177 gpio-controller;
0178 #gpio-cells = <2>;
0179 clocks = <&clock HIX5HD2_FIXED_100M>;
0180 clock-names = "apb_pclk";
0181 interrupt-controller;
0182 #interrupt-cells = <2>;
0183 status = "disabled";
0184 };
0185
0186 gpio4: gpio@b24000 {
0187 compatible = "arm,pl061", "arm,primecell";
0188 reg = <0xb24000 0x1000>;
0189 interrupts = <0 112 0x4>;
0190 gpio-controller;
0191 #gpio-cells = <2>;
0192 clocks = <&clock HIX5HD2_FIXED_100M>;
0193 clock-names = "apb_pclk";
0194 interrupt-controller;
0195 #interrupt-cells = <2>;
0196 status = "disabled";
0197 };
0198
0199 gpio5: gpio@4000 {
0200 compatible = "arm,pl061", "arm,primecell";
0201 reg = <0x004000 0x1000>;
0202 interrupts = <0 113 0x4>;
0203 gpio-controller;
0204 #gpio-cells = <2>;
0205 clocks = <&clock HIX5HD2_FIXED_100M>;
0206 clock-names = "apb_pclk";
0207 interrupt-controller;
0208 #interrupt-cells = <2>;
0209 status = "disabled";
0210 };
0211
0212 gpio6: gpio@b26000 {
0213 compatible = "arm,pl061", "arm,primecell";
0214 reg = <0xb26000 0x1000>;
0215 interrupts = <0 114 0x4>;
0216 gpio-controller;
0217 #gpio-cells = <2>;
0218 clocks = <&clock HIX5HD2_FIXED_100M>;
0219 clock-names = "apb_pclk";
0220 interrupt-controller;
0221 #interrupt-cells = <2>;
0222 status = "disabled";
0223 };
0224
0225 gpio7: gpio@b27000 {
0226 compatible = "arm,pl061", "arm,primecell";
0227 reg = <0xb27000 0x1000>;
0228 interrupts = <0 115 0x4>;
0229 gpio-controller;
0230 #gpio-cells = <2>;
0231 clocks = <&clock HIX5HD2_FIXED_100M>;
0232 clock-names = "apb_pclk";
0233 interrupt-controller;
0234 #interrupt-cells = <2>;
0235 status = "disabled";
0236 };
0237
0238 gpio8: gpio@b28000 {
0239 compatible = "arm,pl061", "arm,primecell";
0240 reg = <0xb28000 0x1000>;
0241 interrupts = <0 116 0x4>;
0242 gpio-controller;
0243 #gpio-cells = <2>;
0244 clocks = <&clock HIX5HD2_FIXED_100M>;
0245 clock-names = "apb_pclk";
0246 interrupt-controller;
0247 #interrupt-cells = <2>;
0248 status = "disabled";
0249 };
0250
0251 gpio9: gpio@b29000 {
0252 compatible = "arm,pl061", "arm,primecell";
0253 reg = <0xb29000 0x1000>;
0254 interrupts = <0 117 0x4>;
0255 gpio-controller;
0256 #gpio-cells = <2>;
0257 clocks = <&clock HIX5HD2_FIXED_100M>;
0258 clock-names = "apb_pclk";
0259 interrupt-controller;
0260 #interrupt-cells = <2>;
0261 status = "disabled";
0262 };
0263
0264 gpio10: gpio@b2a000 {
0265 compatible = "arm,pl061", "arm,primecell";
0266 reg = <0xb2a000 0x1000>;
0267 interrupts = <0 118 0x4>;
0268 gpio-controller;
0269 #gpio-cells = <2>;
0270 clocks = <&clock HIX5HD2_FIXED_100M>;
0271 clock-names = "apb_pclk";
0272 interrupt-controller;
0273 #interrupt-cells = <2>;
0274 status = "disabled";
0275 };
0276
0277 gpio11: gpio@b2b000 {
0278 compatible = "arm,pl061", "arm,primecell";
0279 reg = <0xb2b000 0x1000>;
0280 interrupts = <0 119 0x4>;
0281 gpio-controller;
0282 #gpio-cells = <2>;
0283 clocks = <&clock HIX5HD2_FIXED_100M>;
0284 clock-names = "apb_pclk";
0285 interrupt-controller;
0286 #interrupt-cells = <2>;
0287 status = "disabled";
0288 };
0289
0290 gpio12: gpio@b2c000 {
0291 compatible = "arm,pl061", "arm,primecell";
0292 reg = <0xb2c000 0x1000>;
0293 interrupts = <0 120 0x4>;
0294 gpio-controller;
0295 #gpio-cells = <2>;
0296 clocks = <&clock HIX5HD2_FIXED_100M>;
0297 clock-names = "apb_pclk";
0298 interrupt-controller;
0299 #interrupt-cells = <2>;
0300 status = "disabled";
0301 };
0302
0303 gpio13: gpio@b2d000 {
0304 compatible = "arm,pl061", "arm,primecell";
0305 reg = <0xb2d000 0x1000>;
0306 interrupts = <0 121 0x4>;
0307 gpio-controller;
0308 #gpio-cells = <2>;
0309 clocks = <&clock HIX5HD2_FIXED_100M>;
0310 clock-names = "apb_pclk";
0311 interrupt-controller;
0312 #interrupt-cells = <2>;
0313 status = "disabled";
0314 };
0315
0316 gpio14: gpio@b2e000 {
0317 compatible = "arm,pl061", "arm,primecell";
0318 reg = <0xb2e000 0x1000>;
0319 interrupts = <0 122 0x4>;
0320 gpio-controller;
0321 #gpio-cells = <2>;
0322 clocks = <&clock HIX5HD2_FIXED_100M>;
0323 clock-names = "apb_pclk";
0324 interrupt-controller;
0325 #interrupt-cells = <2>;
0326 status = "disabled";
0327 };
0328
0329 gpio15: gpio@b2f000 {
0330 compatible = "arm,pl061", "arm,primecell";
0331 reg = <0xb2f000 0x1000>;
0332 interrupts = <0 123 0x4>;
0333 gpio-controller;
0334 #gpio-cells = <2>;
0335 clocks = <&clock HIX5HD2_FIXED_100M>;
0336 clock-names = "apb_pclk";
0337 interrupt-controller;
0338 #interrupt-cells = <2>;
0339 status = "disabled";
0340 };
0341
0342 gpio16: gpio@b30000 {
0343 compatible = "arm,pl061", "arm,primecell";
0344 reg = <0xb30000 0x1000>;
0345 interrupts = <0 124 0x4>;
0346 gpio-controller;
0347 #gpio-cells = <2>;
0348 clocks = <&clock HIX5HD2_FIXED_100M>;
0349 clock-names = "apb_pclk";
0350 interrupt-controller;
0351 #interrupt-cells = <2>;
0352 status = "disabled";
0353 };
0354
0355 gpio17: gpio@b31000 {
0356 compatible = "arm,pl061", "arm,primecell";
0357 reg = <0xb31000 0x1000>;
0358 interrupts = <0 125 0x4>;
0359 gpio-controller;
0360 #gpio-cells = <2>;
0361 clocks = <&clock HIX5HD2_FIXED_100M>;
0362 clock-names = "apb_pclk";
0363 interrupt-controller;
0364 #interrupt-cells = <2>;
0365 status = "disabled";
0366 };
0367
0368 wdt0: watchdog@a2c000 {
0369 compatible = "arm,sp805", "arm,primecell";
0370 arm,primecell-periphid = <0x00141805>;
0371 reg = <0xa2c000 0x1000>;
0372 interrupts = <0 29 4>;
0373 clocks = <&clock HIX5HD2_WDG0_RST>,
0374 <&clock HIX5HD2_WDG0_RST>;
0375 clock-names = "wdog_clk", "apb_pclk";
0376 };
0377 };
0378
0379 local_timer@a00600 {
0380 compatible = "arm,cortex-a9-twd-timer";
0381 reg = <0x00a00600 0x20>;
0382 interrupts = <1 13 0xf01>;
0383 };
0384
0385 l2: cache-controller {
0386 compatible = "arm,pl310-cache";
0387 reg = <0x00a10000 0x100000>;
0388 interrupts = <0 15 4>;
0389 cache-unified;
0390 cache-level = <2>;
0391 };
0392
0393 sysctrl: system-controller@0 {
0394 compatible = "hisilicon,sysctrl", "syscon";
0395 reg = <0x00000000 0x1000>;
0396 };
0397
0398 reboot {
0399 compatible = "syscon-reboot";
0400 regmap = <&sysctrl>;
0401 offset = <0x4>;
0402 mask = <0xdeadbeef>;
0403 };
0404
0405 cpuctrl@a22000 {
0406 compatible = "hisilicon,cpuctrl";
0407 #address-cells = <1>;
0408 #size-cells = <1>;
0409 reg = <0x00a22000 0x2000>;
0410 ranges = <0 0x00a22000 0x2000>;
0411
0412 clock: clock@0 {
0413 compatible = "hisilicon,hix5hd2-clock";
0414 reg = <0 0x2000>;
0415 #clock-cells = <1>;
0416 };
0417 };
0418
0419 /* unremovable emmc as mmcblk0 */
0420 mmc: mmc@1830000 {
0421 compatible = "snps,dw-mshc";
0422 reg = <0x1830000 0x1000>;
0423 interrupts = <0 35 4>;
0424 clocks = <&clock HIX5HD2_MMC_CIU_RST>,
0425 <&clock HIX5HD2_MMC_BIU_CLK>;
0426 clock-names = "biu", "ciu";
0427 };
0428
0429 sd: mmc@1820000 {
0430 compatible = "snps,dw-mshc";
0431 reg = <0x1820000 0x1000>;
0432 interrupts = <0 34 4>;
0433 clocks = <&clock HIX5HD2_SD_CIU_RST>,
0434 <&clock HIX5HD2_SD_BIU_CLK>;
0435 clock-names = "biu", "ciu";
0436 };
0437
0438 gmac0: ethernet@1840000 {
0439 compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
0440 reg = <0x1840000 0x1000>,<0x184300c 0x4>;
0441 interrupts = <0 71 4>;
0442 clocks = <&clock HIX5HD2_MAC0_CLK>;
0443 clock-names = "mac_core";
0444 status = "disabled";
0445 };
0446
0447 gmac1: ethernet@1841000 {
0448 compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
0449 reg = <0x1841000 0x1000>,<0x1843010 0x4>;
0450 interrupts = <0 72 4>;
0451 clocks = <&clock HIX5HD2_MAC1_CLK>;
0452 clock-names = "mac_core";
0453 status = "disabled";
0454 };
0455
0456 usb0: usb@1890000 {
0457 compatible = "generic-ehci";
0458 reg = <0x1890000 0x1000>;
0459 interrupts = <0 66 4>;
0460 clocks = <&clock HIX5HD2_USB_CLK>;
0461 };
0462
0463 usb1: usb@1880000 {
0464 compatible = "generic-ohci";
0465 reg = <0x1880000 0x1000>;
0466 interrupts = <0 67 4>;
0467 clocks = <&clock HIX5HD2_USB_CLK>;
0468 };
0469
0470 peripheral_ctrl: syscon@a20000 {
0471 compatible = "hisilicon,peri-subctrl", "syscon";
0472 reg = <0xa20000 0x1000>;
0473 };
0474
0475 sata_phy: phy@1900000 {
0476 compatible = "hisilicon,hix5hd2-sata-phy";
0477 reg = <0x1900000 0x10000>;
0478 #phy-cells = <0>;
0479 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
0480 hisilicon,power-reg = <0x8 10>;
0481 };
0482
0483 ahci: sata@1900000 {
0484 compatible = "hisilicon,hisi-ahci";
0485 reg = <0x1900000 0x10000>;
0486 interrupts = <0 70 4>;
0487 clocks = <&clock HIX5HD2_SATA_CLK>;
0488 };
0489
0490 ir: ir@1000 {
0491 compatible = "hisilicon,hix5hd2-ir";
0492 reg = <0x001000 0x1000>;
0493 interrupts = <0 47 4>;
0494 clocks = <&clock HIX5HD2_FIXED_24M>;
0495 hisilicon,power-syscon = <&sysctrl>;
0496 };
0497
0498 i2c0: i2c@b10000 {
0499 compatible = "hisilicon,hix5hd2-i2c";
0500 reg = <0xb10000 0x1000>;
0501 interrupts = <0 38 4>;
0502 clocks = <&clock HIX5HD2_I2C0_RST>;
0503 #address-cells = <1>;
0504 #size-cells = <0>;
0505 status = "disabled";
0506 };
0507
0508 i2c1: i2c@b11000 {
0509 compatible = "hisilicon,hix5hd2-i2c";
0510 reg = <0xb11000 0x1000>;
0511 interrupts = <0 39 4>;
0512 clocks = <&clock HIX5HD2_I2C1_RST>;
0513 #address-cells = <1>;
0514 #size-cells = <0>;
0515 status = "disabled";
0516 };
0517
0518 i2c2: i2c@b12000 {
0519 compatible = "hisilicon,hix5hd2-i2c";
0520 reg = <0xb12000 0x1000>;
0521 interrupts = <0 40 4>;
0522 clocks = <&clock HIX5HD2_I2C2_RST>;
0523 #address-cells = <1>;
0524 #size-cells = <0>;
0525 status = "disabled";
0526 };
0527
0528 i2c3: i2c@b13000 {
0529 compatible = "hisilicon,hix5hd2-i2c";
0530 reg = <0xb13000 0x1000>;
0531 interrupts = <0 41 4>;
0532 clocks = <&clock HIX5HD2_I2C3_RST>;
0533 #address-cells = <1>;
0534 #size-cells = <0>;
0535 status = "disabled";
0536 };
0537
0538 i2c4: i2c@b16000 {
0539 compatible = "hisilicon,hix5hd2-i2c";
0540 reg = <0xb16000 0x1000>;
0541 interrupts = <0 43 4>;
0542 clocks = <&clock HIX5HD2_I2C4_RST>;
0543 #address-cells = <1>;
0544 #size-cells = <0>;
0545 status = "disabled";
0546 };
0547
0548 i2c5: i2c@b17000 {
0549 compatible = "hisilicon,hix5hd2-i2c";
0550 reg = <0xb17000 0x1000>;
0551 interrupts = <0 44 4>;
0552 clocks = <&clock HIX5HD2_I2C5_RST>;
0553 #address-cells = <1>;
0554 #size-cells = <0>;
0555 status = "disabled";
0556 };
0557 };
0558 };
