0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2013-2014 Linaro Ltd.
0004 * Copyright (c) 2013-2014 HiSilicon Limited.
0005 */
0006
0007 /dts-v1/;
0008 #include "hisi-x5hd2.dtsi"
0009
0010 / {
0011 model = "Hisilicon HIX5HD2 Development Board";
0012 compatible = "hisilicon,hix5hd2";
0013
0014 chosen {
0015 stdout-path = "serial0:115200n8";
0016 };
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021 enable-method = "hisilicon,hix5hd2-smp";
0022
0023 cpu@0 {
0024 compatible = "arm,cortex-a9";
0025 device_type = "cpu";
0026 reg = <0>;
0027 next-level-cache = <&l2>;
0028 };
0029
0030 cpu@1 {
0031 compatible = "arm,cortex-a9";
0032 device_type = "cpu";
0033 reg = <1>;
0034 next-level-cache = <&l2>;
0035 };
0036 };
0037
0038 memory@0 {
0039 device_type = "memory";
0040 reg = <0x00000000 0x80000000>;
0041 };
0042 };
0043
0044 &timer0 {
0045 status = "okay";
0046 };
0047
0048 &uart0 {
0049 status = "okay";
0050 };
0051
0052 &gmac0 {
0053 #address-cells = <1>;
0054 #size-cells = <0>;
0055 phy-handle = <&phy2>;
0056 phy-mode = "mii";
0057 /* Placeholder, overwritten by bootloader */
0058 mac-address = [00 00 00 00 00 00];
0059 status = "okay";
0060
0061 phy2: ethernet-phy@2 {
0062 reg = <2>;
0063 };
0064 };
0065
0066 &gmac1 {
0067 #address-cells = <1>;
0068 #size-cells = <0>;
0069 phy-handle = <&phy1>;
0070 phy-mode = "rgmii";
0071 /* Placeholder, overwritten by bootloader */
0072 mac-address = [00 00 00 00 00 00];
0073 status = "okay";
0074
0075 phy1: ethernet-phy@1 {
0076 reg = <1>;
0077 };
0078 };
0079
0080 &ahci {
0081 phys = <&sata_phy>;
0082 phy-names = "sata-phy";
0083 };
