0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * HiSilicon Ltd. HiP01 SoC
0004 *
0005 * Copyright (c) 2014 HiSilicon Ltd.
0006 * Copyright (c) 2014 Huawei Ltd.
0007 *
0008 * Author: Wang Long <long.wanglong@huawei.com>
0009 */
0010
0011 / {
0012 interrupt-parent = <&gic>;
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 gic: interrupt-controller@1e001000 {
0017 compatible = "arm,cortex-a9-gic";
0018 #interrupt-cells = <3>;
0019 #address-cells = <0>;
0020 interrupt-controller;
0021 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
0022 };
0023
0024 hisi_refclk144mhz: refclk144mkhz {
0025 compatible = "fixed-clock";
0026 #clock-cells = <0>;
0027 clock-frequency = <144000000>;
0028 clock-output-names = "hisi:refclk144khz";
0029 };
0030
0031 soc {
0032 #address-cells = <1>;
0033 #size-cells = <1>;
0034 compatible = "simple-bus";
0035 interrupt-parent = <&gic>;
0036 ranges = <0 0x10000000 0x20000000>;
0037
0038 amba-bus {
0039 #address-cells = <1>;
0040 #size-cells = <1>;
0041 compatible = "simple-bus";
0042 ranges;
0043
0044 uart0: serial@10001000 {
0045 compatible = "snps,dw-apb-uart";
0046 reg = <0x10001000 0x1000>;
0047 clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
0048 clock-names = "baudclk", "apb_pclk";
0049 reg-shift = <2>;
0050 interrupts = <0 32 4>;
0051 status = "disabled";
0052 };
0053
0054 uart1: serial@10002000 {
0055 compatible = "snps,dw-apb-uart";
0056 reg = <0x10002000 0x1000>;
0057 clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
0058 clock-names = "baudclk", "apb_pclk";
0059 reg-shift = <2>;
0060 interrupts = <0 33 4>;
0061 status = "disabled";
0062 };
0063
0064 uart2: serial@10003000 {
0065 compatible = "snps,dw-apb-uart";
0066 reg = <0x10003000 0x1000>;
0067 clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
0068 clock-names = "baudclk", "apb_pclk";
0069 reg-shift = <2>;
0070 interrupts = <0 34 4>;
0071 status = "disabled";
0072 };
0073
0074 uart3: serial@10006000 {
0075 compatible = "snps,dw-apb-uart";
0076 reg = <0x10006000 0x1000>;
0077 clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
0078 clock-names = "baudclk", "apb_pclk";
0079 reg-shift = <2>;
0080 interrupts = <0 4 4>;
0081 status = "disabled";
0082 };
0083 };
0084
0085 system-controller@10000000 {
0086 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
0087 reg = <0x10000000 0x1000>;
0088 reboot-offset = <0x4>;
0089 };
0090
0091 global_timer@a000200 {
0092 compatible = "arm,cortex-a9-global-timer";
0093 reg = <0x0a000200 0x100>;
0094 interrupts = <1 11 0xf04>;
0095 clocks = <&hisi_refclk144mhz>;
0096 };
0097
0098 local_timer@a000600 {
0099 compatible = "arm,cortex-a9-twd-timer";
0100 reg = <0x0a000600 0x100>;
0101 interrupts = <1 13 0xf04>;
0102 clocks = <&hisi_refclk144mhz>;
0103 };
0104 };
0105 };
