boot/dts/hip01-ca9x2.dts

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * HiSilicon Ltd. HiP01 SoC
0004  *
0005  * Copyright (C) 2014 HiSilicon Ltd.
0006  * Copyright (C) 2014 Huawei Ltd.
0007  *
0008  * Author: Wang Long <long.wanglong@huawei.com>
0009  */
0010
0011 /dts-v1/;
0012
0013 /* First 8KB reserved for secondary core boot */
0014 /memreserve/ 0x80000000 0x00002000;
0015
0016 #include "hip01.dtsi"
0017
0018 / {
0019         model = "Hisilicon HIP01 Development Board";
0020         compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
0021
0022         cpus {
0023                 #address-cells = <1>;
0024                 #size-cells = <0>;
0025                 enable-method = "hisilicon,hip01-smp";
0026
0027                 cpu@0 {
0028                         device_type = "cpu";
0029                         compatible = "arm,cortex-a9";
0030                         reg = <0>;
0031                 };
0032
0033                 cpu@1 {
0034                         device_type = "cpu";
0035                         compatible = "arm,cortex-a9";
0036                         reg = <1>;
0037                 };
0038         };
0039
0040         memory@80000000 {
0041                 device_type = "memory";
0042                 reg = <0x80000000 0x80000000>;
0043         };
0044 };
0045
0046 &uart0 {
0047         status = "okay";
0048 };