0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright 2011-2012 Calxeda, Inc.
0004 */
0005
0006 /dts-v1/;
0007
0008 /* First 4KB has pen for secondary cores. */
0009 /memreserve/ 0x00000000 0x0001000;
0010
0011 / {
0012 model = "Calxeda Highbank";
0013 compatible = "calxeda,highbank";
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu@900 {
0022 compatible = "arm,cortex-a9";
0023 device_type = "cpu";
0024 reg = <0x900>;
0025 next-level-cache = <&L2>;
0026 clocks = <&a9pll>;
0027 clock-names = "cpu";
0028 operating-points = <
0029 /* kHz ignored */
0030 1300000 1000000
0031 1200000 1000000
0032 1100000 1000000
0033 800000 1000000
0034 400000 1000000
0035 200000 1000000
0036 >;
0037 clock-latency = <100000>;
0038 };
0039
0040 cpu@901 {
0041 compatible = "arm,cortex-a9";
0042 device_type = "cpu";
0043 reg = <0x901>;
0044 next-level-cache = <&L2>;
0045 clocks = <&a9pll>;
0046 clock-names = "cpu";
0047 operating-points = <
0048 /* kHz ignored */
0049 1300000 1000000
0050 1200000 1000000
0051 1100000 1000000
0052 800000 1000000
0053 400000 1000000
0054 200000 1000000
0055 >;
0056 clock-latency = <100000>;
0057 };
0058
0059 cpu@902 {
0060 compatible = "arm,cortex-a9";
0061 device_type = "cpu";
0062 reg = <0x902>;
0063 next-level-cache = <&L2>;
0064 clocks = <&a9pll>;
0065 clock-names = "cpu";
0066 operating-points = <
0067 /* kHz ignored */
0068 1300000 1000000
0069 1200000 1000000
0070 1100000 1000000
0071 800000 1000000
0072 400000 1000000
0073 200000 1000000
0074 >;
0075 clock-latency = <100000>;
0076 };
0077
0078 cpu@903 {
0079 compatible = "arm,cortex-a9";
0080 device_type = "cpu";
0081 reg = <0x903>;
0082 next-level-cache = <&L2>;
0083 clocks = <&a9pll>;
0084 clock-names = "cpu";
0085 operating-points = <
0086 /* kHz ignored */
0087 1300000 1000000
0088 1200000 1000000
0089 1100000 1000000
0090 800000 1000000
0091 400000 1000000
0092 200000 1000000
0093 >;
0094 clock-latency = <100000>;
0095 };
0096 };
0097
0098 memory@0 {
0099 name = "memory";
0100 device_type = "memory";
0101 reg = <0x00000000 0xff900000>;
0102 };
0103
0104 soc {
0105 ranges = <0x00000000 0x00000000 0xffffffff>;
0106
0107 memory-controller@fff00000 {
0108 compatible = "calxeda,hb-ddr-ctrl";
0109 reg = <0xfff00000 0x1000>;
0110 interrupts = <0 91 4>;
0111 };
0112
0113 timer@fff10600 {
0114 compatible = "arm,cortex-a9-twd-timer";
0115 reg = <0xfff10600 0x20>;
0116 interrupts = <1 13 0xf01>;
0117 clocks = <&a9periphclk>;
0118 };
0119
0120 watchdog@fff10620 {
0121 compatible = "arm,cortex-a9-twd-wdt";
0122 reg = <0xfff10620 0x20>;
0123 interrupts = <1 14 0xf01>;
0124 clocks = <&a9periphclk>;
0125 };
0126
0127 intc: interrupt-controller@fff11000 {
0128 compatible = "arm,cortex-a9-gic";
0129 #interrupt-cells = <3>;
0130 interrupt-controller;
0131 reg = <0xfff11000 0x1000>,
0132 <0xfff10100 0x100>;
0133 };
0134
0135 L2: cache-controller {
0136 compatible = "arm,pl310-cache";
0137 reg = <0xfff12000 0x1000>;
0138 interrupts = <0 70 4>;
0139 cache-unified;
0140 cache-level = <2>;
0141 };
0142
0143 pmu {
0144 compatible = "arm,cortex-a9-pmu";
0145 interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
0146 };
0147
0148
0149 sregs@fff3c200 {
0150 compatible = "calxeda,hb-sregs-l2-ecc";
0151 reg = <0xfff3c200 0x100>;
0152 interrupts = <0 71 4>, <0 72 4>;
0153 };
0154
0155 };
0156 };
0157
0158 /include/ "ecx-common.dtsi"
