0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * HiSilicon Ltd. Hi3620 SoC
0004 *
0005 * Copyright (C) 2012-2013 HiSilicon Ltd.
0006 * Copyright (C) 2012-2013 Linaro Ltd.
0007 *
0008 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
0009 */
0010
0011 #include <dt-bindings/clock/hi3620-clock.h>
0012
0013 / {
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 aliases {
0018 serial0 = &uart0;
0019 serial1 = &uart1;
0020 serial2 = &uart2;
0021 serial3 = &uart3;
0022 serial4 = &uart4;
0023 };
0024
0025 pclk: clk {
0026 compatible = "fixed-clock";
0027 #clock-cells = <0>;
0028 clock-frequency = <26000000>;
0029 clock-output-names = "apb_pclk";
0030 };
0031
0032 cpus {
0033 #address-cells = <1>;
0034 #size-cells = <0>;
0035 enable-method = "hisilicon,hi3620-smp";
0036
0037 cpu@0 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a9";
0040 reg = <0x0>;
0041 next-level-cache = <&L2>;
0042 };
0043
0044 cpu@1 {
0045 compatible = "arm,cortex-a9";
0046 device_type = "cpu";
0047 reg = <1>;
0048 next-level-cache = <&L2>;
0049 };
0050
0051 cpu@2 {
0052 compatible = "arm,cortex-a9";
0053 device_type = "cpu";
0054 reg = <2>;
0055 next-level-cache = <&L2>;
0056 };
0057
0058 cpu@3 {
0059 compatible = "arm,cortex-a9";
0060 device_type = "cpu";
0061 reg = <3>;
0062 next-level-cache = <&L2>;
0063 };
0064 };
0065
0066 amba-bus {
0067
0068 #address-cells = <1>;
0069 #size-cells = <1>;
0070 compatible = "simple-bus";
0071 interrupt-parent = <&gic>;
0072 ranges = <0 0xfc000000 0x2000000>;
0073
0074 L2: cache-controller {
0075 compatible = "arm,pl310-cache";
0076 reg = <0x100000 0x100000>;
0077 interrupts = <0 15 4>;
0078 cache-unified;
0079 cache-level = <2>;
0080 };
0081
0082 gic: interrupt-controller@1000 {
0083 compatible = "arm,cortex-a9-gic";
0084 #interrupt-cells = <3>;
0085 #address-cells = <0>;
0086 interrupt-controller;
0087 /* gic dist base, gic cpu base */
0088 reg = <0x1000 0x1000>, <0x100 0x100>;
0089 };
0090
0091 sysctrl: system-controller@802000 {
0092 compatible = "hisilicon,sysctrl", "syscon";
0093 #address-cells = <1>;
0094 #size-cells = <1>;
0095 ranges = <0 0x802000 0x1000>;
0096 reg = <0x802000 0x1000>;
0097
0098 smp-offset = <0x31c>;
0099 resume-offset = <0x308>;
0100 reboot-offset = <0x4>;
0101
0102 clock: clock@0 {
0103 compatible = "hisilicon,hi3620-clock";
0104 reg = <0 0x10000>;
0105 #clock-cells = <1>;
0106 };
0107 };
0108
0109 dual_timer0: dual_timer@800000 {
0110 compatible = "arm,sp804", "arm,primecell";
0111 reg = <0x800000 0x1000>;
0112 /* timer00 & timer01 */
0113 interrupts = <0 0 4>, <0 1 4>;
0114 clocks = <&clock HI3620_TIMER0_MUX>,
0115 <&clock HI3620_TIMER1_MUX>,
0116 <&clock HI3620_TIMER0_MUX>;
0117 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0118 status = "disabled";
0119 };
0120
0121 dual_timer1: dual_timer@801000 {
0122 compatible = "arm,sp804", "arm,primecell";
0123 reg = <0x801000 0x1000>;
0124 /* timer10 & timer11 */
0125 interrupts = <0 2 4>, <0 3 4>;
0126 clocks = <&clock HI3620_TIMER2_MUX>,
0127 <&clock HI3620_TIMER3_MUX>,
0128 <&clock HI3620_TIMER2_MUX>;
0129 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0130 status = "disabled";
0131 };
0132
0133 dual_timer2: dual_timer@a01000 {
0134 compatible = "arm,sp804", "arm,primecell";
0135 reg = <0xa01000 0x1000>;
0136 /* timer20 & timer21 */
0137 interrupts = <0 4 4>, <0 5 4>;
0138 clocks = <&clock HI3620_TIMER4_MUX>,
0139 <&clock HI3620_TIMER5_MUX>,
0140 <&clock HI3620_TIMER4_MUX>;
0141 clock-names = "timer0lck", "timer1clk", "apb_pclk";
0142 status = "disabled";
0143 };
0144
0145 dual_timer3: dual_timer@a02000 {
0146 compatible = "arm,sp804", "arm,primecell";
0147 reg = <0xa02000 0x1000>;
0148 /* timer30 & timer31 */
0149 interrupts = <0 6 4>, <0 7 4>;
0150 clocks = <&clock HI3620_TIMER6_MUX>,
0151 <&clock HI3620_TIMER7_MUX>,
0152 <&clock HI3620_TIMER6_MUX>;
0153 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0154 status = "disabled";
0155 };
0156
0157 dual_timer4: dual_timer@a03000 {
0158 compatible = "arm,sp804", "arm,primecell";
0159 reg = <0xa03000 0x1000>;
0160 /* timer40 & timer41 */
0161 interrupts = <0 96 4>, <0 97 4>;
0162 clocks = <&clock HI3620_TIMER8_MUX>,
0163 <&clock HI3620_TIMER9_MUX>,
0164 <&clock HI3620_TIMER8_MUX>;
0165 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0166 status = "disabled";
0167 };
0168
0169 timer5: timer@600 {
0170 compatible = "arm,cortex-a9-twd-timer";
0171 reg = <0x600 0x20>;
0172 interrupts = <1 13 0xf01>;
0173 };
0174
0175 uart0: serial@b00000 {
0176 compatible = "arm,pl011", "arm,primecell";
0177 reg = <0xb00000 0x1000>;
0178 interrupts = <0 20 4>;
0179 clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>;
0180 clock-names = "uartclk", "apb_pclk";
0181 status = "disabled";
0182 };
0183
0184 uart1: serial@b01000 {
0185 compatible = "arm,pl011", "arm,primecell";
0186 reg = <0xb01000 0x1000>;
0187 interrupts = <0 21 4>;
0188 clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>;
0189 clock-names = "uartclk", "apb_pclk";
0190 status = "disabled";
0191 };
0192
0193 uart2: serial@b02000 {
0194 compatible = "arm,pl011", "arm,primecell";
0195 reg = <0xb02000 0x1000>;
0196 interrupts = <0 22 4>;
0197 clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>;
0198 clock-names = "uartclk", "apb_pclk";
0199 status = "disabled";
0200 };
0201
0202 uart3: serial@b03000 {
0203 compatible = "arm,pl011", "arm,primecell";
0204 reg = <0xb03000 0x1000>;
0205 interrupts = <0 23 4>;
0206 clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>;
0207 clock-names = "uartclk", "apb_pclk";
0208 status = "disabled";
0209 };
0210
0211 uart4: serial@b04000 {
0212 compatible = "arm,pl011", "arm,primecell";
0213 reg = <0xb04000 0x1000>;
0214 interrupts = <0 24 4>;
0215 clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>;
0216 clock-names = "uartclk", "apb_pclk";
0217 status = "disabled";
0218 };
0219
0220 gpio0: gpio@806000 {
0221 compatible = "arm,pl061", "arm,primecell";
0222 reg = <0x806000 0x1000>;
0223 interrupts = <0 64 0x4>;
0224 gpio-controller;
0225 #gpio-cells = <2>;
0226 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
0227 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
0228 interrupt-controller;
0229 #interrupt-cells = <2>;
0230 clocks = <&clock HI3620_GPIOCLK0>;
0231 clock-names = "apb_pclk";
0232 };
0233
0234 gpio1: gpio@807000 {
0235 compatible = "arm,pl061", "arm,primecell";
0236 reg = <0x807000 0x1000>;
0237 interrupts = <0 65 0x4>;
0238 gpio-controller;
0239 #gpio-cells = <2>;
0240 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
0241 &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
0242 &pmx0 6 5 1 &pmx0 7 6 1>;
0243 interrupt-controller;
0244 #interrupt-cells = <2>;
0245 clocks = <&clock HI3620_GPIOCLK1>;
0246 clock-names = "apb_pclk";
0247 };
0248
0249 gpio2: gpio@808000 {
0250 compatible = "arm,pl061", "arm,primecell";
0251 reg = <0x808000 0x1000>;
0252 interrupts = <0 66 0x4>;
0253 gpio-controller;
0254 #gpio-cells = <2>;
0255 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
0256 &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
0257 &pmx0 6 3 1 &pmx0 7 3 1>;
0258 interrupt-controller;
0259 #interrupt-cells = <2>;
0260 clocks = <&clock HI3620_GPIOCLK2>;
0261 clock-names = "apb_pclk";
0262 };
0263
0264 gpio3: gpio@809000 {
0265 compatible = "arm,pl061", "arm,primecell";
0266 reg = <0x809000 0x1000>;
0267 interrupts = <0 67 0x4>;
0268 gpio-controller;
0269 #gpio-cells = <2>;
0270 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
0271 &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
0272 &pmx0 6 11 1 &pmx0 7 11 1>;
0273 interrupt-controller;
0274 #interrupt-cells = <2>;
0275 clocks = <&clock HI3620_GPIOCLK3>;
0276 clock-names = "apb_pclk";
0277 };
0278
0279 gpio4: gpio@80a000 {
0280 compatible = "arm,pl061", "arm,primecell";
0281 reg = <0x80a000 0x1000>;
0282 interrupts = <0 68 0x4>;
0283 gpio-controller;
0284 #gpio-cells = <2>;
0285 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
0286 &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
0287 &pmx0 6 13 1 &pmx0 7 13 1>;
0288 interrupt-controller;
0289 #interrupt-cells = <2>;
0290 clocks = <&clock HI3620_GPIOCLK4>;
0291 clock-names = "apb_pclk";
0292 };
0293
0294 gpio5: gpio@80b000 {
0295 compatible = "arm,pl061", "arm,primecell";
0296 reg = <0x80b000 0x1000>;
0297 interrupts = <0 69 0x4>;
0298 gpio-controller;
0299 #gpio-cells = <2>;
0300 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
0301 &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
0302 &pmx0 6 16 1 &pmx0 7 16 1>;
0303 interrupt-controller;
0304 #interrupt-cells = <2>;
0305 clocks = <&clock HI3620_GPIOCLK5>;
0306 clock-names = "apb_pclk";
0307 };
0308
0309 gpio6: gpio@80c000 {
0310 compatible = "arm,pl061", "arm,primecell";
0311 reg = <0x80c000 0x1000>;
0312 interrupts = <0 70 0x4>;
0313 gpio-controller;
0314 #gpio-cells = <2>;
0315 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
0316 &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
0317 &pmx0 6 18 1 &pmx0 7 19 1>;
0318 interrupt-controller;
0319 #interrupt-cells = <2>;
0320 clocks = <&clock HI3620_GPIOCLK6>;
0321 clock-names = "apb_pclk";
0322 };
0323
0324 gpio7: gpio@80d000 {
0325 compatible = "arm,pl061", "arm,primecell";
0326 reg = <0x80d000 0x1000>;
0327 interrupts = <0 71 0x4>;
0328 gpio-controller;
0329 #gpio-cells = <2>;
0330 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
0331 &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
0332 &pmx0 6 25 1 &pmx0 7 26 1>;
0333 interrupt-controller;
0334 #interrupt-cells = <2>;
0335 clocks = <&clock HI3620_GPIOCLK7>;
0336 clock-names = "apb_pclk";
0337 };
0338
0339 gpio8: gpio@80e000 {
0340 compatible = "arm,pl061", "arm,primecell";
0341 reg = <0x80e000 0x1000>;
0342 interrupts = <0 72 0x4>;
0343 gpio-controller;
0344 #gpio-cells = <2>;
0345 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
0346 &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
0347 &pmx0 6 33 1 &pmx0 7 34 1>;
0348 interrupt-controller;
0349 #interrupt-cells = <2>;
0350 clocks = <&clock HI3620_GPIOCLK8>;
0351 clock-names = "apb_pclk";
0352 };
0353
0354 gpio9: gpio@80f000 {
0355 compatible = "arm,pl061", "arm,primecell";
0356 reg = <0x80f000 0x1000>;
0357 interrupts = <0 73 0x4>;
0358 gpio-controller;
0359 #gpio-cells = <2>;
0360 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
0361 &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
0362 &pmx0 6 41 1>;
0363 interrupt-controller;
0364 #interrupt-cells = <2>;
0365 clocks = <&clock HI3620_GPIOCLK9>;
0366 clock-names = "apb_pclk";
0367 };
0368
0369 gpio10: gpio@810000 {
0370 compatible = "arm,pl061", "arm,primecell";
0371 reg = <0x810000 0x1000>;
0372 interrupts = <0 74 0x4>;
0373 gpio-controller;
0374 #gpio-cells = <2>;
0375 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
0376 &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
0377 interrupt-controller;
0378 #interrupt-cells = <2>;
0379 clocks = <&clock HI3620_GPIOCLK10>;
0380 clock-names = "apb_pclk";
0381 };
0382
0383 gpio11: gpio@811000 {
0384 compatible = "arm,pl061", "arm,primecell";
0385 reg = <0x811000 0x1000>;
0386 interrupts = <0 75 0x4>;
0387 gpio-controller;
0388 #gpio-cells = <2>;
0389 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
0390 &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
0391 &pmx0 6 49 1 &pmx0 7 49 1>;
0392 interrupt-controller;
0393 #interrupt-cells = <2>;
0394 clocks = <&clock HI3620_GPIOCLK11>;
0395 clock-names = "apb_pclk";
0396 };
0397
0398 gpio12: gpio@812000 {
0399 compatible = "arm,pl061", "arm,primecell";
0400 reg = <0x812000 0x1000>;
0401 interrupts = <0 76 0x4>;
0402 gpio-controller;
0403 #gpio-cells = <2>;
0404 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
0405 &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
0406 &pmx0 6 51 1 &pmx0 7 52 1>;
0407 interrupt-controller;
0408 #interrupt-cells = <2>;
0409 clocks = <&clock HI3620_GPIOCLK12>;
0410 clock-names = "apb_pclk";
0411 };
0412
0413 gpio13: gpio@813000 {
0414 compatible = "arm,pl061", "arm,primecell";
0415 reg = <0x813000 0x1000>;
0416 interrupts = <0 77 0x4>;
0417 gpio-controller;
0418 #gpio-cells = <2>;
0419 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
0420 &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
0421 &pmx0 6 55 1 &pmx0 7 56 1>;
0422 interrupt-controller;
0423 #interrupt-cells = <2>;
0424 clocks = <&clock HI3620_GPIOCLK13>;
0425 clock-names = "apb_pclk";
0426 };
0427
0428 gpio14: gpio@814000 {
0429 compatible = "arm,pl061", "arm,primecell";
0430 reg = <0x814000 0x1000>;
0431 interrupts = <0 78 0x4>;
0432 gpio-controller;
0433 #gpio-cells = <2>;
0434 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
0435 &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
0436 &pmx0 6 60 1 &pmx0 7 61 1>;
0437 interrupt-controller;
0438 #interrupt-cells = <2>;
0439 clocks = <&clock HI3620_GPIOCLK14>;
0440 clock-names = "apb_pclk";
0441 };
0442
0443 gpio15: gpio@815000 {
0444 compatible = "arm,pl061", "arm,primecell";
0445 reg = <0x815000 0x1000>;
0446 interrupts = <0 79 0x4>;
0447 gpio-controller;
0448 #gpio-cells = <2>;
0449 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
0450 &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
0451 &pmx0 6 64 1 &pmx0 7 65 1>;
0452 interrupt-controller;
0453 #interrupt-cells = <2>;
0454 clocks = <&clock HI3620_GPIOCLK15>;
0455 clock-names = "apb_pclk";
0456 };
0457
0458 gpio16: gpio@816000 {
0459 compatible = "arm,pl061", "arm,primecell";
0460 reg = <0x816000 0x1000>;
0461 interrupts = <0 80 0x4>;
0462 gpio-controller;
0463 #gpio-cells = <2>;
0464 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
0465 &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
0466 &pmx0 6 72 1 &pmx0 7 73 1>;
0467 interrupt-controller;
0468 #interrupt-cells = <2>;
0469 clocks = <&clock HI3620_GPIOCLK16>;
0470 clock-names = "apb_pclk";
0471 };
0472
0473 gpio17: gpio@817000 {
0474 compatible = "arm,pl061", "arm,primecell";
0475 reg = <0x817000 0x1000>;
0476 interrupts = <0 81 0x4>;
0477 gpio-controller;
0478 #gpio-cells = <2>;
0479 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
0480 &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
0481 &pmx0 6 80 1 &pmx0 7 81 1>;
0482 interrupt-controller;
0483 #interrupt-cells = <2>;
0484 clocks = <&clock HI3620_GPIOCLK17>;
0485 clock-names = "apb_pclk";
0486 };
0487
0488 gpio18: gpio@818000 {
0489 compatible = "arm,pl061", "arm,primecell";
0490 reg = <0x818000 0x1000>;
0491 interrupts = <0 82 0x4>;
0492 gpio-controller;
0493 #gpio-cells = <2>;
0494 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
0495 &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
0496 &pmx0 6 86 1 &pmx0 7 87 1>;
0497 interrupt-controller;
0498 #interrupt-cells = <2>;
0499 clocks = <&clock HI3620_GPIOCLK18>;
0500 clock-names = "apb_pclk";
0501 };
0502
0503 gpio19: gpio@819000 {
0504 compatible = "arm,pl061", "arm,primecell";
0505 reg = <0x819000 0x1000>;
0506 interrupts = <0 83 0x4>;
0507 gpio-controller;
0508 #gpio-cells = <2>;
0509 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
0510 &pmx0 3 88 1>;
0511 interrupt-controller;
0512 #interrupt-cells = <2>;
0513 clocks = <&clock HI3620_GPIOCLK19>;
0514 clock-names = "apb_pclk";
0515 };
0516
0517 gpio20: gpio@81a000 {
0518 compatible = "arm,pl061", "arm,primecell";
0519 reg = <0x81a000 0x1000>;
0520 interrupts = <0 84 0x4>;
0521 gpio-controller;
0522 #gpio-cells = <2>;
0523 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
0524 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
0525 interrupt-controller;
0526 #interrupt-cells = <2>;
0527 clocks = <&clock HI3620_GPIOCLK20>;
0528 clock-names = "apb_pclk";
0529 };
0530
0531 gpio21: gpio@81b000 {
0532 compatible = "arm,pl061", "arm,primecell";
0533 reg = <0x81b000 0x1000>;
0534 interrupts = <0 85 0x4>;
0535 gpio-controller;
0536 #gpio-cells = <2>;
0537 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
0538 interrupt-controller;
0539 #interrupt-cells = <2>;
0540 clocks = <&clock HI3620_GPIOCLK21>;
0541 clock-names = "apb_pclk";
0542 };
0543
0544 pmx0: pinmux@803000 {
0545 compatible = "pinctrl-single";
0546 reg = <0x803000 0x188>;
0547 #address-cells = <1>;
0548 #size-cells = <1>;
0549 #pinctrl-cells = <1>;
0550 #gpio-range-cells = <3>;
0551 ranges;
0552
0553 pinctrl-single,register-width = <32>;
0554 pinctrl-single,function-mask = <7>;
0555 /* pin base, nr pins & gpio function */
0556 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
0557 &range 12 1 0 &range 13 29 1
0558 &range 43 1 0 &range 44 49 1
0559 &range 94 1 1 &range 96 2 1>;
0560
0561 range: gpio-range {
0562 #pinctrl-single,gpio-range-cells = <3>;
0563 };
0564 };
0565
0566 pmx1: pinmux@803800 {
0567 compatible = "pinconf-single";
0568 reg = <0x803800 0x2dc>;
0569 #address-cells = <1>;
0570 #size-cells = <1>;
0571 #pinctrl-cells = <1>;
0572 ranges;
0573
0574 pinctrl-single,register-width = <32>;
0575 };
0576 };
0577 };
