0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
0004 */
0005
0006 #include <dt-bindings/clock/hi3519-clock.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 chosen { };
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu@0 {
0018 device_type = "cpu";
0019 compatible = "arm,cortex-a7";
0020 reg = <0>;
0021 };
0022 };
0023
0024 gic: interrupt-controller@10300000 {
0025 compatible = "arm,cortex-a7-gic";
0026 #interrupt-cells = <3>;
0027 interrupt-controller;
0028 reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
0029 };
0030
0031 clk_3m: clk_3m {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <3000000>;
0035 };
0036
0037 crg: clock-reset-controller@12010000 {
0038 compatible = "hisilicon,hi3519-crg";
0039 #clock-cells = <1>;
0040 #reset-cells = <2>;
0041 reg = <0x12010000 0x10000>;
0042 };
0043
0044 soc {
0045 #address-cells = <1>;
0046 #size-cells = <1>;
0047 compatible = "simple-bus";
0048 interrupt-parent = <&gic>;
0049 ranges;
0050
0051 uart0: serial@12100000 {
0052 compatible = "arm,pl011", "arm,primecell";
0053 reg = <0x12100000 0x1000>;
0054 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0055 clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
0056 clock-names = "uartclk", "apb_pclk";
0057 status = "disable";
0058 };
0059
0060 uart1: serial@12101000 {
0061 compatible = "arm,pl011", "arm,primecell";
0062 reg = <0x12101000 0x1000>;
0063 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0064 clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
0065 clock-names = "uartclk", "apb_pclk";
0066 status = "disable";
0067 };
0068
0069 uart2: serial@12102000 {
0070 compatible = "arm,pl011", "arm,primecell";
0071 reg = <0x12102000 0x1000>;
0072 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0073 clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
0074 clock-names = "uartclk", "apb_pclk";
0075 status = "disable";
0076 };
0077
0078 uart3: serial@12103000 {
0079 compatible = "arm,pl011", "arm,primecell";
0080 reg = <0x12103000 0x1000>;
0081 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0082 clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
0083 clock-names = "uartclk", "apb_pclk";
0084 status = "disable";
0085 };
0086
0087 uart4: serial@12104000 {
0088 compatible = "arm,pl011", "arm,primecell";
0089 reg = <0x12104000 0x1000>;
0090 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0091 clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
0092 clock-names = "uartclk", "apb_pclk";
0093 status = "disable";
0094 };
0095
0096 dual_timer0: timer@12000000 {
0097 compatible = "arm,sp804", "arm,primecell";
0098 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
0099 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0100 reg = <0x12000000 0x1000>;
0101 clocks = <&clk_3m>;
0102 clock-names = "apb_pclk";
0103 status = "disable";
0104 };
0105
0106 dual_timer1: timer@12001000 {
0107 compatible = "arm,sp804", "arm,primecell";
0108 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0109 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0110 reg = <0x12001000 0x1000>;
0111 clocks = <&clk_3m>;
0112 clock-names = "apb_pclk";
0113 status = "disable";
0114 };
0115
0116 dual_timer2: timer@12002000 {
0117 compatible = "arm,sp804", "arm,primecell";
0118 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0119 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0120 reg = <0x12002000 0x1000>;
0121 clocks = <&clk_3m>;
0122 clock-names = "apb_pclk";
0123 status = "disable";
0124 };
0125
0126 spi_bus0: spi@12120000 {
0127 compatible = "arm,pl022", "arm,primecell";
0128 reg = <0x12120000 0x1000>;
0129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0130 clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
0131 clock-names = "sspclk", "apb_pclk";
0132 num-cs = <1>;
0133 #address-cells = <1>;
0134 #size-cells = <0>;
0135 status = "disable";
0136 };
0137
0138 spi_bus1: spi@12121000 {
0139 compatible = "arm,pl022", "arm,primecell";
0140 reg = <0x12121000 0x1000>;
0141 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0142 clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
0143 clock-names = "sspclk", "apb_pclk";
0144 num-cs = <1>;
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 status = "disable";
0148 };
0149
0150 spi_bus2: spi@12122000 {
0151 compatible = "arm,pl022", "arm,primecell";
0152 reg = <0x12122000 0x1000>;
0153 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0154 clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
0155 clock-names = "sspclk", "apb_pclk";
0156 num-cs = <1>;
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159 status = "disable";
0160 };
0161
0162 sysctrl: system-controller@12020000 {
0163 compatible = "hisilicon,hi3519-sysctrl", "syscon";
0164 reg = <0x12020000 0x1000>;
0165 };
0166
0167 reboot {
0168 compatible = "syscon-reboot";
0169 regmap = <&sysctrl>;
0170 offset = <0x4>;
0171 mask = <0xdeadbeef>;
0172 };
0173 };
0174 };
