0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree file for Cortina systems Gemini SoC
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/clock/cortina,gemini-clock.h>
0008 #include <dt-bindings/reset/cortina,gemini-reset.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010
0011 / {
0012 soc {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 ranges;
0016 compatible = "simple-bus";
0017 interrupt-parent = <&intcon>;
0018
0019 flash: flash@30000000 {
0020 compatible = "cortina,gemini-flash", "cfi-flash";
0021 syscon = <&syscon>;
0022 pinctrl-names = "default";
0023 pinctrl-0 = <&pflash_default_pins>;
0024 bank-width = <2>;
0025 #address-cells = <1>;
0026 #size-cells = <1>;
0027 status = "disabled";
0028 };
0029
0030 syscon: syscon@40000000 {
0031 compatible = "cortina,gemini-syscon",
0032 "syscon", "simple-mfd";
0033 reg = <0x40000000 0x1000>;
0034 #clock-cells = <1>;
0035 #reset-cells = <1>;
0036
0037 syscon-reboot {
0038 compatible = "syscon-reboot";
0039 regmap = <&syscon>;
0040 /* GLOBAL_RESET register */
0041 offset = <0x0c>;
0042 /* RESET_GLOBAL | RESET_CPU1 */
0043 mask = <0xC0000000>;
0044 };
0045
0046 pinctrl {
0047 compatible = "cortina,gemini-pinctrl";
0048 regmap = <&syscon>;
0049 /* Hog the DRAM pins */
0050 pinctrl-names = "default";
0051 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
0052 <&vcontrol_default_pins>;
0053
0054 dram_default_pins: pinctrl-dram {
0055 mux {
0056 function = "dram";
0057 groups = "dramgrp";
0058 };
0059 };
0060 rtc_default_pins: pinctrl-rtc {
0061 mux {
0062 function = "rtc";
0063 groups = "rtcgrp";
0064 };
0065 };
0066 power_default_pins: pinctrl-power {
0067 mux {
0068 function = "power";
0069 groups = "powergrp";
0070 };
0071 };
0072 cir_default_pins: pinctrl-cir {
0073 mux {
0074 function = "cir";
0075 groups = "cirgrp";
0076 };
0077 };
0078 system_default_pins: pinctrl-system {
0079 mux {
0080 function = "system";
0081 groups = "systemgrp";
0082 };
0083 };
0084 vcontrol_default_pins: pinctrl-vcontrol {
0085 mux {
0086 function = "vcontrol";
0087 groups = "vcontrolgrp";
0088 };
0089 };
0090 ice_default_pins: pinctrl-ice {
0091 mux {
0092 function = "ice";
0093 groups = "icegrp";
0094 };
0095 };
0096 uart_default_pins: pinctrl-uart {
0097 mux {
0098 function = "uart";
0099 groups = "uartrxtxgrp";
0100 };
0101 };
0102 pflash_default_pins: pinctrl-pflash {
0103 mux {
0104 function = "pflash";
0105 groups = "pflashgrp";
0106 };
0107 };
0108 usb_default_pins: pinctrl-usb {
0109 mux {
0110 function = "usb";
0111 groups = "usbgrp";
0112 };
0113 };
0114 gmii_default_pins: pinctrl-gmii {
0115 /*
0116 * Only activate GMAC0 by default since
0117 * GMAC1 will overlap with 8 GPIO lines
0118 * gpio2a, gpio2b. Overlay groups with
0119 * "gmii_gmac0_grp", "gmii_gmac1_grp" for
0120 * both ethernet interfaces.
0121 */
0122 mux {
0123 function = "gmii";
0124 groups = "gmii_gmac0_grp";
0125 };
0126 };
0127 pci_default_pins: pinctrl-pci {
0128 mux {
0129 function = "pci";
0130 groups = "pcigrp";
0131 };
0132 };
0133 sata_default_pins: pinctrl-sata {
0134 mux {
0135 function = "sata";
0136 groups = "satagrp";
0137 };
0138 };
0139 /* Activate both groups of pins for this state */
0140 sata_and_ide_pins: pinctrl-sata-ide {
0141 mux0 {
0142 function = "sata";
0143 groups = "satagrp";
0144 };
0145 mux1 {
0146 function = "ide";
0147 groups = "idegrp";
0148 };
0149 };
0150 tvc_default_pins: pinctrl-tvc {
0151 mux {
0152 function = "tvc";
0153 groups = "tvcgrp";
0154 };
0155 };
0156 };
0157 };
0158
0159 watchdog@41000000 {
0160 compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
0161 reg = <0x41000000 0x1000>;
0162 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
0163 resets = <&syscon GEMINI_RESET_WDOG>;
0164 clocks = <&syscon GEMINI_CLK_APB>;
0165 clock-names = "PCLK";
0166 };
0167
0168 uart0: serial@42000000 {
0169 compatible = "ns16550a";
0170 reg = <0x42000000 0x100>;
0171 resets = <&syscon GEMINI_RESET_UART>;
0172 clocks = <&syscon GEMINI_CLK_UART>;
0173 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
0174 pinctrl-names = "default";
0175 pinctrl-0 = <&uart_default_pins>;
0176 reg-shift = <2>;
0177 };
0178
0179 timer@43000000 {
0180 compatible = "faraday,fttmr010";
0181 reg = <0x43000000 0x1000>;
0182 interrupt-parent = <&intcon>;
0183 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
0184 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
0185 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
0186 resets = <&syscon GEMINI_RESET_TIMER>;
0187 /* APB clock or RTC clock */
0188 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
0189 clock-names = "PCLK", "EXTCLK";
0190 syscon = <&syscon>;
0191 };
0192
0193 rtc@45000000 {
0194 compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
0195 reg = <0x45000000 0x100>;
0196 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
0197 resets = <&syscon GEMINI_RESET_RTC>;
0198 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
0199 clock-names = "PCLK", "EXTCLK";
0200 pinctrl-names = "default";
0201 pinctrl-0 = <&rtc_default_pins>;
0202 };
0203
0204 sata: sata@46000000 {
0205 compatible = "cortina,gemini-sata-bridge";
0206 reg = <0x46000000 0x100>;
0207 resets = <&syscon GEMINI_RESET_SATA0>,
0208 <&syscon GEMINI_RESET_SATA1>;
0209 reset-names = "sata0", "sata1";
0210 clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
0211 <&syscon GEMINI_CLK_GATE_SATA1>;
0212 clock-names = "SATA0_PCLK", "SATA1_PCLK";
0213 /*
0214 * This defines the special "ide" state that needs
0215 * to be explicitly enabled to enable the IDE pins,
0216 * as these pins are normally used for other things.
0217 */
0218 pinctrl-names = "default", "ide";
0219 pinctrl-0 = <&sata_default_pins>;
0220 pinctrl-1 = <&sata_and_ide_pins>;
0221 syscon = <&syscon>;
0222 status = "disabled";
0223 };
0224
0225 intcon: interrupt-controller@48000000 {
0226 compatible = "faraday,ftintc010";
0227 reg = <0x48000000 0x1000>;
0228 resets = <&syscon GEMINI_RESET_INTCON0>;
0229 interrupt-controller;
0230 #interrupt-cells = <2>;
0231 };
0232
0233 power-controller@4b000000 {
0234 compatible = "cortina,gemini-power-controller";
0235 reg = <0x4b000000 0x100>;
0236 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
0237 pinctrl-names = "default";
0238 pinctrl-0 = <&power_default_pins>;
0239 };
0240
0241 gpio0: gpio@4d000000 {
0242 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
0243 reg = <0x4d000000 0x100>;
0244 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
0245 resets = <&syscon GEMINI_RESET_GPIO0>;
0246 clocks = <&syscon GEMINI_CLK_APB>;
0247 gpio-controller;
0248 #gpio-cells = <2>;
0249 interrupt-controller;
0250 #interrupt-cells = <2>;
0251 };
0252
0253 gpio1: gpio@4e000000 {
0254 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
0255 reg = <0x4e000000 0x100>;
0256 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
0257 resets = <&syscon GEMINI_RESET_GPIO1>;
0258 clocks = <&syscon GEMINI_CLK_APB>;
0259 gpio-controller;
0260 #gpio-cells = <2>;
0261 interrupt-controller;
0262 #interrupt-cells = <2>;
0263 };
0264
0265 gpio2: gpio@4f000000 {
0266 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
0267 reg = <0x4f000000 0x100>;
0268 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
0269 resets = <&syscon GEMINI_RESET_GPIO2>;
0270 clocks = <&syscon GEMINI_CLK_APB>;
0271 gpio-controller;
0272 #gpio-cells = <2>;
0273 interrupt-controller;
0274 #interrupt-cells = <2>;
0275 };
0276
0277 pci@50000000 {
0278 compatible = "cortina,gemini-pci", "faraday,ftpci100";
0279 /*
0280 * The first 256 bytes in the IO range is actually used
0281 * to configure the host bridge.
0282 */
0283 reg = <0x50000000 0x100>;
0284 resets = <&syscon GEMINI_RESET_PCI>;
0285 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
0286 clock-names = "PCLK", "PCICLK";
0287 pinctrl-names = "default";
0288 pinctrl-0 = <&pci_default_pins>;
0289 device_type = "pci";
0290 #address-cells = <3>;
0291 #size-cells = <2>;
0292 status = "disabled";
0293
0294 #interrupt-cells = <1>;
0295 interrupt-map-mask = <0xf800 0 0 7>;
0296 interrupt-map =
0297 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
0298 <0x4800 0 0 2 &pci_intc 1>,
0299 <0x4800 0 0 3 &pci_intc 2>,
0300 <0x4800 0 0 4 &pci_intc 3>,
0301 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
0302 <0x5000 0 0 2 &pci_intc 2>,
0303 <0x5000 0 0 3 &pci_intc 3>,
0304 <0x5000 0 0 4 &pci_intc 0>,
0305 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
0306 <0x5800 0 0 2 &pci_intc 3>,
0307 <0x5800 0 0 3 &pci_intc 0>,
0308 <0x5800 0 0 4 &pci_intc 1>,
0309 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
0310 <0x6000 0 0 2 &pci_intc 0>,
0311 <0x6000 0 0 3 &pci_intc 1>,
0312 <0x6000 0 0 4 &pci_intc 2>;
0313
0314 bus-range = <0x00 0xff>;
0315 /* PCI ranges mappings */
0316 ranges =
0317 /* 1MiB I/O space 0x50000000-0x500fffff */
0318 <0x01000000 0 0 0x50000000 0 0x00100000>,
0319 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
0320 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
0321
0322 /* DMA ranges */
0323 dma-ranges =
0324 /* 128MiB at 0x00000000-0x07ffffff */
0325 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
0326 /* 64MiB at 0x00000000-0x03ffffff */
0327 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
0328 /* 64MiB at 0x00000000-0x03ffffff */
0329 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
0330
0331 /*
0332 * This PCI host bridge variant has a cascaded interrupt
0333 * controller embedded in the host bridge.
0334 */
0335 pci_intc: interrupt-controller {
0336 interrupt-parent = <&intcon>;
0337 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
0338 interrupt-controller;
0339 #address-cells = <0>;
0340 #interrupt-cells = <1>;
0341 };
0342 };
0343
0344 ethernet: ethernet@60000000 {
0345 compatible = "cortina,gemini-ethernet";
0346 reg = <0x60000000 0x4000>, /* Global registers, queue */
0347 <0x60004000 0x2000>, /* V-bit */
0348 <0x60006000 0x2000>; /* A-bit */
0349 pinctrl-names = "default";
0350 pinctrl-0 = <&gmii_default_pins>;
0351 status = "disabled";
0352 #address-cells = <1>;
0353 #size-cells = <1>;
0354 ranges;
0355
0356 gmac0: ethernet-port@0 {
0357 compatible = "cortina,gemini-ethernet-port";
0358 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
0359 <0x6000a000 0x2000>; /* Port 0 GMAC */
0360 interrupt-parent = <&intcon>;
0361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
0362 resets = <&syscon GEMINI_RESET_GMAC0>;
0363 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
0364 clock-names = "PCLK";
0365 };
0366
0367 gmac1: ethernet-port@1 {
0368 compatible = "cortina,gemini-ethernet-port";
0369 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
0370 <0x6000e000 0x2000>; /* Port 1 GMAC */
0371 interrupt-parent = <&intcon>;
0372 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0373 resets = <&syscon GEMINI_RESET_GMAC1>;
0374 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
0375 clock-names = "PCLK";
0376 };
0377 };
0378
0379 crypto: crypto@62000000 {
0380 compatible = "cortina,sl3516-crypto";
0381 reg = <0x62000000 0x10000>;
0382 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
0383 resets = <&syscon GEMINI_RESET_SECURITY>;
0384 clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
0385 };
0386
0387 ide0: ide@63000000 {
0388 compatible = "cortina,gemini-pata", "faraday,ftide010";
0389 reg = <0x63000000 0x1000>;
0390 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
0391 resets = <&syscon GEMINI_RESET_IDE>;
0392 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
0393 clock-names = "PCLK";
0394 sata = <&sata>;
0395 status = "disabled";
0396 #address-cells = <1>;
0397 #size-cells = <0>;
0398 };
0399
0400 ide1: ide@63400000 {
0401 compatible = "cortina,gemini-pata", "faraday,ftide010";
0402 reg = <0x63400000 0x1000>;
0403 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
0404 resets = <&syscon GEMINI_RESET_IDE>;
0405 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
0406 clock-names = "PCLK";
0407 sata = <&sata>;
0408 status = "disabled";
0409 #address-cells = <1>;
0410 #size-cells = <0>;
0411 };
0412
0413 dma-controller@67000000 {
0414 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
0415 /* Faraday Technology FTDMAC020 variant */
0416 arm,primecell-periphid = <0x0003b080>;
0417 reg = <0x67000000 0x1000>;
0418 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
0419 resets = <&syscon GEMINI_RESET_DMAC>;
0420 clocks = <&syscon GEMINI_CLK_AHB>;
0421 clock-names = "apb_pclk";
0422 /* Bus interface AHB1 (AHB0) is totally tilted */
0423 lli-bus-interface-ahb2;
0424 mem-bus-interface-ahb2;
0425 memcpy-burst-size = <256>;
0426 memcpy-bus-width = <32>;
0427 #dma-cells = <2>;
0428 };
0429
0430 display-controller@6a000000 {
0431 compatible = "cortina,gemini-tvc", "faraday,tve200";
0432 reg = <0x6a000000 0x1000>;
0433 interrupts = <13 IRQ_TYPE_EDGE_RISING>;
0434 resets = <&syscon GEMINI_RESET_TVC>;
0435 clocks = <&syscon GEMINI_CLK_GATE_TVC>,
0436 <&syscon GEMINI_CLK_TVC>;
0437 clock-names = "PCLK", "TVE";
0438 pinctrl-names = "default";
0439 pinctrl-0 = <&tvc_default_pins>;
0440 status = "disabled";
0441 };
0442
0443 usb0: usb@68000000 {
0444 compatible = "cortina,gemini-usb", "faraday,fotg210";
0445 reg = <0x68000000 0x1000>;
0446 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
0447 resets = <&syscon GEMINI_RESET_USB0>;
0448 clocks = <&syscon GEMINI_CLK_GATE_USB0>;
0449 clock-names = "PCLK";
0450 /*
0451 * This will claim pins for USB0 and USB1 at the same
0452 * time as they are using some common pins. If you for
0453 * some reason have a system using USB1 at 96000000 but
0454 * NOT using USB0 at 68000000 you wll have to add the
0455 * usb_default_pins to the USB controller at 96000000
0456 * in your .dts for the board.
0457 */
0458 pinctrl-names = "default";
0459 pinctrl-0 = <&usb_default_pins>;
0460 syscon = <&syscon>;
0461 status = "disabled";
0462 };
0463
0464 usb1: usb@69000000 {
0465 compatible = "cortina,gemini-usb", "faraday,fotg210";
0466 reg = <0x69000000 0x1000>;
0467 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
0468 resets = <&syscon GEMINI_RESET_USB1>;
0469 clocks = <&syscon GEMINI_CLK_GATE_USB1>;
0470 clock-names = "PCLK";
0471 syscon = <&syscon>;
0472 status = "disabled";
0473 };
0474 };
0475 };
