0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's Exynos54xx SoC series common device tree source
0004 *
0005 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 * Copyright (c) 2016 Krzysztof Kozlowski
0008 *
0009 * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
0010 * Exynos 54xx SoCs should include this file and customize it further
0011 * (e.g. with clocks).
0012 */
0013
0014 #include "exynos5.dtsi"
0015
0016 / {
0017 compatible = "samsung,exynos5";
0018
0019 aliases {
0020 i2c4 = &hsi2c_4;
0021 i2c5 = &hsi2c_5;
0022 i2c6 = &hsi2c_6;
0023 i2c7 = &hsi2c_7;
0024 usbdrdphy0 = &usbdrd_phy0;
0025 usbdrdphy1 = &usbdrd_phy1;
0026 };
0027
0028 arm_a7_pmu: arm-a7-pmu {
0029 compatible = "arm,cortex-a7-pmu";
0030 interrupt-parent = <&gic>;
0031 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0032 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0033 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0034 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
0035 status = "disabled";
0036 };
0037
0038 arm_a15_pmu: arm-a15-pmu {
0039 compatible = "arm,cortex-a15-pmu";
0040 interrupt-parent = <&combiner>;
0041 interrupts = <1 2>,
0042 <7 0>,
0043 <16 6>,
0044 <19 2>;
0045 status = "disabled";
0046 };
0047
0048 timer: timer {
0049 compatible = "arm,armv7-timer";
0050 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0051 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0052 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0053 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0054 clock-frequency = <24000000>;
0055 };
0056
0057 soc: soc {
0058 sram@2020000 {
0059 compatible = "mmio-sram";
0060 reg = <0x02020000 0x54000>;
0061 #address-cells = <1>;
0062 #size-cells = <1>;
0063 ranges = <0 0x02020000 0x54000>;
0064
0065 smp-sram@0 {
0066 compatible = "samsung,exynos4210-sysram";
0067 reg = <0x0 0x1000>;
0068 };
0069
0070 smp-sram@53000 {
0071 compatible = "samsung,exynos4210-sysram-ns";
0072 reg = <0x53000 0x1000>;
0073 };
0074 };
0075
0076 mct: timer@101c0000 {
0077 compatible = "samsung,exynos5420-mct",
0078 "samsung,exynos4210-mct";
0079 reg = <0x101c0000 0xb00>;
0080 interrupts-extended = <&combiner 23 3>,
0081 <&combiner 23 4>,
0082 <&combiner 25 2>,
0083 <&combiner 25 3>,
0084 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0085 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0086 <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0087 <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0088 <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0089 <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0090 <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0091 <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0092 };
0093
0094 watchdog: watchdog@101d0000 {
0095 compatible = "samsung,exynos5420-wdt";
0096 reg = <0x101d0000 0x100>;
0097 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0098 };
0099
0100 adc: adc@12d10000 {
0101 compatible = "samsung,exynos-adc-v2";
0102 reg = <0x12d10000 0x100>;
0103 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0104 #io-channel-cells = <1>;
0105 status = "disabled";
0106 };
0107
0108 /* i2c_0-3 are defined in exynos5.dtsi */
0109 hsi2c_4: i2c@12ca0000 {
0110 compatible = "samsung,exynos5250-hsi2c";
0111 reg = <0x12ca0000 0x1000>;
0112 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0113 #address-cells = <1>;
0114 #size-cells = <0>;
0115 status = "disabled";
0116 };
0117
0118 hsi2c_5: i2c@12cb0000 {
0119 compatible = "samsung,exynos5250-hsi2c";
0120 reg = <0x12cb0000 0x1000>;
0121 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0122 #address-cells = <1>;
0123 #size-cells = <0>;
0124 status = "disabled";
0125 };
0126
0127 hsi2c_6: i2c@12cc0000 {
0128 compatible = "samsung,exynos5250-hsi2c";
0129 reg = <0x12cc0000 0x1000>;
0130 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133 status = "disabled";
0134 };
0135
0136 hsi2c_7: i2c@12cd0000 {
0137 compatible = "samsung,exynos5250-hsi2c";
0138 reg = <0x12cd0000 0x1000>;
0139 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0140 #address-cells = <1>;
0141 #size-cells = <0>;
0142 status = "disabled";
0143 };
0144
0145 usbdrd3_0: usb3-0 {
0146 compatible = "samsung,exynos5250-dwusb3";
0147 #address-cells = <1>;
0148 #size-cells = <1>;
0149 ranges;
0150
0151 usbdrd_dwc3_0: usb@12000000 {
0152 compatible = "snps,dwc3";
0153 reg = <0x12000000 0x10000>;
0154 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0155 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
0156 phy-names = "usb2-phy", "usb3-phy";
0157 snps,dis_u3_susphy_quirk;
0158 };
0159 };
0160
0161 usbdrd_phy0: phy@12100000 {
0162 compatible = "samsung,exynos5420-usbdrd-phy";
0163 reg = <0x12100000 0x100>;
0164 #phy-cells = <1>;
0165 };
0166
0167 usbdrd3_1: usb3-1 {
0168 compatible = "samsung,exynos5250-dwusb3";
0169 #address-cells = <1>;
0170 #size-cells = <1>;
0171 ranges;
0172
0173 usbdrd_dwc3_1: usb@12400000 {
0174 compatible = "snps,dwc3";
0175 reg = <0x12400000 0x10000>;
0176 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
0177 phy-names = "usb2-phy", "usb3-phy";
0178 snps,dis_u3_susphy_quirk;
0179 };
0180 };
0181
0182 usbdrd_phy1: phy@12500000 {
0183 compatible = "samsung,exynos5420-usbdrd-phy";
0184 reg = <0x12500000 0x100>;
0185 #phy-cells = <1>;
0186 };
0187
0188 usbhost2: usb@12110000 {
0189 compatible = "samsung,exynos4210-ehci";
0190 reg = <0x12110000 0x100>;
0191 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0192 phys = <&usb2_phy 0>;
0193 phy-names = "host";
0194 };
0195
0196 usbhost1: usb@12120000 {
0197 compatible = "samsung,exynos4210-ohci";
0198 reg = <0x12120000 0x100>;
0199 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0200 phys = <&usb2_phy 0>;
0201 phy-names = "host";
0202 };
0203
0204 usb2_phy: phy@12130000 {
0205 compatible = "samsung,exynos5420-usb2-phy";
0206 reg = <0x12130000 0x100>;
0207 #phy-cells = <1>;
0208 };
0209 };
0210 };
