boot/dts/exynos5422-odroidxu3-audio.dtsi

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Hardkernel Odroid XU3 audio subsystem device tree source
0004  *
0005  * Copyright (c) 2015 Krzysztof Kozlowski
0006  * Copyright (c) 2014 Collabora Ltd.
0007  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0008  *              http://www.samsung.com
0009  */
0010
0011 #include <dt-bindings/sound/samsung-i2s.h>
0012
0013 / {
0014         sound: sound {
0015                 compatible = "samsung,odroid-xu3-audio";
0016                 model = "Odroid-XU3";
0017
0018                 samsung,audio-widgets =
0019                         "Headphone", "Headphone Jack",
0020                         "Speakers", "Speakers";
0021                 samsung,audio-routing =
0022                         "Headphone Jack", "HPL",
0023                         "Headphone Jack", "HPR",
0024                         "Headphone Jack", "MICBIAS",
0025                         "IN12", "Headphone Jack",
0026                         "Speakers", "SPKL",
0027                         "Speakers", "SPKR",
0028                         "I2S Playback", "Mixer DAI TX",
0029                         "HiFi Playback", "Mixer DAI TX",
0030                         "Mixer DAI RX", "HiFi Capture";
0031
0032                 cpu {
0033                         sound-dai = <&i2s0 0>, <&i2s0 1>;
0034                 };
0035                 codec {
0036                         sound-dai = <&hdmi>, <&max98090>;
0037                 };
0038         };
0039 };
0040
0041 &hsi2c_5 {
0042         status = "okay";
0043         max98090: audio-codec@10 {
0044                 compatible = "maxim,max98090";
0045                 reg = <0x10>;
0046                 interrupt-parent = <&gpx3>;
0047                 interrupts = <2 IRQ_TYPE_NONE>;
0048                 clocks = <&i2s0 CLK_I2S_CDCLK>;
0049                 clock-names = "mclk";
0050                 #sound-dai-cells = <0>;
0051         };
0052 };
0053
0054 &i2s0 {
0055         status = "okay";
0056         assigned-clocks = <&clock CLK_MOUT_EPLL>,
0057                         <&clock CLK_MOUT_MAU_EPLL>,
0058                         <&clock CLK_MOUT_USER_MAU_EPLL>,
0059                         <&clock_audss EXYNOS_MOUT_AUDSS>,
0060                         <&clock_audss EXYNOS_MOUT_I2S>,
0061                         <&i2s0 CLK_I2S_RCLK_SRC>,
0062                         <&clock_audss EXYNOS_DOUT_SRP>,
0063                         <&clock_audss EXYNOS_DOUT_AUD_BUS>,
0064                         <&clock_audss EXYNOS_DOUT_I2S>;
0065
0066         assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
0067                         <&clock CLK_MOUT_EPLL>,
0068                         <&clock CLK_MOUT_MAU_EPLL>,
0069                         <&clock CLK_MAU_EPLL>,
0070                         <&clock_audss EXYNOS_MOUT_AUDSS>,
0071                         <&clock_audss EXYNOS_SCLK_I2S>;
0072
0073         assigned-clock-rates = <0>,
0074                         <0>,
0075                         <0>,
0076                         <0>,
0077                         <0>,
0078                         <0>,
0079                         <196608001>,
0080                         <(196608002 / 2)>,
0081                         <196608000>;
0082
0083 };