0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
0004 *
0005 * Copyright (c) 2017 Marek Szyprowski
0006 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
0007 * http://www.samsung.com
0008 */
0009
0010 #include <dt-bindings/clock/samsung,s2mps11.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/gpio/gpio.h>
0013 #include "exynos5800.dtsi"
0014 #include "exynos5422-cpus.dtsi"
0015
0016 / {
0017 memory@40000000 {
0018 device_type = "memory";
0019 reg = <0x40000000 0x7EA00000>;
0020 };
0021
0022 chosen {
0023 stdout-path = "serial2:115200n8";
0024 };
0025
0026 firmware@2073000 {
0027 compatible = "samsung,secure-firmware";
0028 reg = <0x02073000 0x1000>;
0029 };
0030
0031 fixed-rate-clocks {
0032 oscclk {
0033 compatible = "samsung,exynos5420-oscclk";
0034 clock-frequency = <24000000>;
0035 };
0036 };
0037
0038 bus_wcore_opp_table: opp-table2 {
0039 compatible = "operating-points-v2";
0040
0041 /* derived from 532MHz MPLL */
0042 opp00 {
0043 opp-hz = /bits/ 64 <88700000>;
0044 opp-microvolt = <925000 925000 1400000>;
0045 };
0046 opp01 {
0047 opp-hz = /bits/ 64 <133000000>;
0048 opp-microvolt = <950000 950000 1400000>;
0049 };
0050 opp02 {
0051 opp-hz = /bits/ 64 <177400000>;
0052 opp-microvolt = <950000 950000 1400000>;
0053 };
0054 opp03 {
0055 opp-hz = /bits/ 64 <266000000>;
0056 opp-microvolt = <950000 950000 1400000>;
0057 };
0058 opp04 {
0059 opp-hz = /bits/ 64 <532000000>;
0060 opp-microvolt = <1000000 1000000 1400000>;
0061 };
0062 };
0063
0064 bus_noc_opp_table: opp-table3 {
0065 compatible = "operating-points-v2";
0066
0067 /* derived from 666MHz CPLL */
0068 opp00 {
0069 opp-hz = /bits/ 64 <66600000>;
0070 };
0071 opp01 {
0072 opp-hz = /bits/ 64 <74000000>;
0073 };
0074 opp02 {
0075 opp-hz = /bits/ 64 <83250000>;
0076 };
0077 opp03 {
0078 opp-hz = /bits/ 64 <111000000>;
0079 };
0080 };
0081
0082 bus_fsys_apb_opp_table: opp-table4 {
0083 compatible = "operating-points-v2";
0084
0085 /* derived from 666MHz CPLL */
0086 opp00 {
0087 opp-hz = /bits/ 64 <111000000>;
0088 };
0089 opp01 {
0090 opp-hz = /bits/ 64 <222000000>;
0091 };
0092 };
0093
0094 bus_fsys2_opp_table: opp-table5 {
0095 compatible = "operating-points-v2";
0096
0097 /* derived from 600MHz DPLL */
0098 opp00 {
0099 opp-hz = /bits/ 64 <75000000>;
0100 };
0101 opp01 {
0102 opp-hz = /bits/ 64 <120000000>;
0103 };
0104 opp02 {
0105 opp-hz = /bits/ 64 <200000000>;
0106 };
0107 };
0108
0109 bus_mfc_opp_table: opp-table6 {
0110 compatible = "operating-points-v2";
0111
0112 /* derived from 666MHz CPLL */
0113 opp00 {
0114 opp-hz = /bits/ 64 <83250000>;
0115 };
0116 opp01 {
0117 opp-hz = /bits/ 64 <111000000>;
0118 };
0119 opp02 {
0120 opp-hz = /bits/ 64 <166500000>;
0121 };
0122 opp03 {
0123 opp-hz = /bits/ 64 <222000000>;
0124 };
0125 opp04 {
0126 opp-hz = /bits/ 64 <333000000>;
0127 };
0128 };
0129
0130 bus_gen_opp_table: opp-table7 {
0131 compatible = "operating-points-v2";
0132
0133 /* derived from 532MHz MPLL */
0134 opp00 {
0135 opp-hz = /bits/ 64 <88700000>;
0136 };
0137 opp01 {
0138 opp-hz = /bits/ 64 <133000000>;
0139 };
0140 opp02 {
0141 opp-hz = /bits/ 64 <178000000>;
0142 };
0143 opp03 {
0144 opp-hz = /bits/ 64 <266000000>;
0145 };
0146 };
0147
0148 bus_peri_opp_table: opp-table8 {
0149 compatible = "operating-points-v2";
0150
0151 /* derived from 666MHz CPLL */
0152 opp00 {
0153 opp-hz = /bits/ 64 <66600000>;
0154 };
0155 };
0156
0157 bus_g2d_opp_table: opp-table9 {
0158 compatible = "operating-points-v2";
0159
0160 /* derived from 666MHz CPLL */
0161 opp00 {
0162 opp-hz = /bits/ 64 <83250000>;
0163 };
0164 opp01 {
0165 opp-hz = /bits/ 64 <111000000>;
0166 };
0167 opp02 {
0168 opp-hz = /bits/ 64 <166500000>;
0169 };
0170 opp03 {
0171 opp-hz = /bits/ 64 <222000000>;
0172 };
0173 opp04 {
0174 opp-hz = /bits/ 64 <333000000>;
0175 };
0176 };
0177
0178 bus_g2d_acp_opp_table: opp-table10 {
0179 compatible = "operating-points-v2";
0180
0181 /* derived from 532MHz MPLL */
0182 opp00 {
0183 opp-hz = /bits/ 64 <66500000>;
0184 };
0185 opp01 {
0186 opp-hz = /bits/ 64 <133000000>;
0187 };
0188 opp02 {
0189 opp-hz = /bits/ 64 <178000000>;
0190 };
0191 opp03 {
0192 opp-hz = /bits/ 64 <266000000>;
0193 };
0194 };
0195
0196 bus_jpeg_opp_table: opp-table11 {
0197 compatible = "operating-points-v2";
0198
0199 /* derived from 600MHz DPLL */
0200 opp00 {
0201 opp-hz = /bits/ 64 <75000000>;
0202 };
0203 opp01 {
0204 opp-hz = /bits/ 64 <150000000>;
0205 };
0206 opp02 {
0207 opp-hz = /bits/ 64 <200000000>;
0208 };
0209 opp03 {
0210 opp-hz = /bits/ 64 <300000000>;
0211 };
0212 };
0213
0214 bus_jpeg_apb_opp_table: opp-table12 {
0215 compatible = "operating-points-v2";
0216
0217 /* derived from 666MHz CPLL */
0218 opp00 {
0219 opp-hz = /bits/ 64 <83250000>;
0220 };
0221 opp01 {
0222 opp-hz = /bits/ 64 <111000000>;
0223 };
0224 opp02 {
0225 opp-hz = /bits/ 64 <133000000>;
0226 };
0227 opp03 {
0228 opp-hz = /bits/ 64 <166500000>;
0229 };
0230 };
0231
0232 bus_disp1_fimd_opp_table: opp-table13 {
0233 compatible = "operating-points-v2";
0234
0235 /* derived from 600MHz DPLL */
0236 opp00 {
0237 opp-hz = /bits/ 64 <120000000>;
0238 };
0239 opp01 {
0240 opp-hz = /bits/ 64 <200000000>;
0241 };
0242 };
0243
0244 bus_disp1_opp_table: opp-table14 {
0245 compatible = "operating-points-v2";
0246
0247 /* derived from 600MHz DPLL */
0248 opp00 {
0249 opp-hz = /bits/ 64 <120000000>;
0250 };
0251 opp01 {
0252 opp-hz = /bits/ 64 <200000000>;
0253 };
0254 opp02 {
0255 opp-hz = /bits/ 64 <300000000>;
0256 };
0257 };
0258
0259 bus_gscl_opp_table: opp-table15 {
0260 compatible = "operating-points-v2";
0261
0262 /* derived from 600MHz DPLL */
0263 opp00 {
0264 opp-hz = /bits/ 64 <150000000>;
0265 };
0266 opp01 {
0267 opp-hz = /bits/ 64 <200000000>;
0268 };
0269 opp02 {
0270 opp-hz = /bits/ 64 <300000000>;
0271 };
0272 };
0273
0274 bus_mscl_opp_table: opp-table16 {
0275 compatible = "operating-points-v2";
0276
0277 /* derived from 666MHz CPLL */
0278 opp00 {
0279 opp-hz = /bits/ 64 <84000000>;
0280 };
0281 opp01 {
0282 opp-hz = /bits/ 64 <167000000>;
0283 };
0284 opp02 {
0285 opp-hz = /bits/ 64 <222000000>;
0286 };
0287 opp03 {
0288 opp-hz = /bits/ 64 <333000000>;
0289 };
0290 opp04 {
0291 opp-hz = /bits/ 64 <666000000>;
0292 };
0293 };
0294
0295 dmc_opp_table: opp-table17 {
0296 compatible = "operating-points-v2";
0297
0298 opp00 {
0299 opp-hz = /bits/ 64 <165000000>;
0300 opp-microvolt = <875000>;
0301 };
0302 opp01 {
0303 opp-hz = /bits/ 64 <206000000>;
0304 opp-microvolt = <875000>;
0305 };
0306 opp02 {
0307 opp-hz = /bits/ 64 <275000000>;
0308 opp-microvolt = <875000>;
0309 };
0310 opp03 {
0311 opp-hz = /bits/ 64 <413000000>;
0312 opp-microvolt = <887500>;
0313 };
0314 opp04 {
0315 opp-hz = /bits/ 64 <543000000>;
0316 opp-microvolt = <937500>;
0317 };
0318 opp05 {
0319 opp-hz = /bits/ 64 <633000000>;
0320 opp-microvolt = <1012500>;
0321 };
0322 opp06 {
0323 opp-hz = /bits/ 64 <728000000>;
0324 opp-microvolt = <1037500>;
0325 };
0326 opp07 {
0327 opp-hz = /bits/ 64 <825000000>;
0328 opp-microvolt = <1050000>;
0329 };
0330 };
0331
0332 samsung_K3QF2F20DB: lpddr3 {
0333 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
0334 density = <16384>;
0335 io-width = <32>;
0336
0337 tRFC-min-tck = <17>;
0338 tRRD-min-tck = <2>;
0339 tRPab-min-tck = <2>;
0340 tRPpb-min-tck = <2>;
0341 tRCD-min-tck = <3>;
0342 tRC-min-tck = <6>;
0343 tRAS-min-tck = <5>;
0344 tWTR-min-tck = <2>;
0345 tWR-min-tck = <7>;
0346 tRTP-min-tck = <2>;
0347 tW2W-C2C-min-tck = <0>;
0348 tR2R-C2C-min-tck = <0>;
0349 tWL-min-tck = <8>;
0350 tDQSCK-min-tck = <5>;
0351 tRL-min-tck = <14>;
0352 tFAW-min-tck = <5>;
0353 tXSR-min-tck = <12>;
0354 tXP-min-tck = <2>;
0355 tCKE-min-tck = <2>;
0356 tCKESR-min-tck = <2>;
0357 tMRD-min-tck = <5>;
0358
0359 timings_samsung_K3QF2F20DB_800mhz: timings {
0360 compatible = "jedec,lpddr3-timings";
0361 max-freq = <800000000>;
0362 min-freq = <100000000>;
0363 tRFC = <65000>;
0364 tRRD = <6000>;
0365 tRPab = <12000>;
0366 tRPpb = <12000>;
0367 tRCD = <10000>;
0368 tRC = <33750>;
0369 tRAS = <23000>;
0370 tWTR = <3750>;
0371 tWR = <7500>;
0372 tRTP = <3750>;
0373 tW2W-C2C = <0>;
0374 tR2R-C2C = <0>;
0375 tFAW = <25000>;
0376 tXSR = <70000>;
0377 tXP = <3750>;
0378 tCKE = <3750>;
0379 tCKESR = <3750>;
0380 tMRD = <7000>;
0381 };
0382 };
0383 };
0384
0385 &adc {
0386 vdd-supply = <&ldo4_reg>;
0387 status = "okay";
0388 };
0389
0390 &bus_wcore {
0391 operating-points-v2 = <&bus_wcore_opp_table>;
0392 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
0393 <&nocp_mem1_0>, <&nocp_mem1_1>;
0394 vdd-supply = <&buck3_reg>;
0395 exynos,saturation-ratio = <100>;
0396 status = "okay";
0397 };
0398
0399 &bus_noc {
0400 operating-points-v2 = <&bus_noc_opp_table>;
0401 devfreq = <&bus_wcore>;
0402 status = "okay";
0403 };
0404
0405 &bus_fsys_apb {
0406 operating-points-v2 = <&bus_fsys_apb_opp_table>;
0407 devfreq = <&bus_wcore>;
0408 status = "okay";
0409 };
0410
0411 &bus_fsys2 {
0412 operating-points-v2 = <&bus_fsys2_opp_table>;
0413 devfreq = <&bus_wcore>;
0414 status = "okay";
0415 };
0416
0417 &bus_mfc {
0418 operating-points-v2 = <&bus_mfc_opp_table>;
0419 devfreq = <&bus_wcore>;
0420 status = "okay";
0421 };
0422
0423 &bus_gen {
0424 operating-points-v2 = <&bus_gen_opp_table>;
0425 devfreq = <&bus_wcore>;
0426 status = "okay";
0427 };
0428
0429 &bus_peri {
0430 operating-points-v2 = <&bus_peri_opp_table>;
0431 devfreq = <&bus_wcore>;
0432 status = "okay";
0433 };
0434
0435 &bus_g2d {
0436 operating-points-v2 = <&bus_g2d_opp_table>;
0437 devfreq = <&bus_wcore>;
0438 status = "okay";
0439 };
0440
0441 &bus_g2d_acp {
0442 operating-points-v2 = <&bus_g2d_acp_opp_table>;
0443 devfreq = <&bus_wcore>;
0444 status = "okay";
0445 };
0446
0447 &bus_jpeg {
0448 operating-points-v2 = <&bus_jpeg_opp_table>;
0449 devfreq = <&bus_wcore>;
0450 status = "okay";
0451 };
0452
0453 &bus_jpeg_apb {
0454 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
0455 devfreq = <&bus_wcore>;
0456 status = "okay";
0457 };
0458
0459 &bus_disp1_fimd {
0460 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
0461 devfreq = <&bus_wcore>;
0462 status = "okay";
0463 };
0464
0465 &bus_disp1 {
0466 operating-points-v2 = <&bus_disp1_opp_table>;
0467 devfreq = <&bus_wcore>;
0468 status = "okay";
0469 };
0470
0471 &bus_gscl_scaler {
0472 operating-points-v2 = <&bus_gscl_opp_table>;
0473 devfreq = <&bus_wcore>;
0474 status = "okay";
0475 };
0476
0477 &bus_mscl {
0478 operating-points-v2 = <&bus_mscl_opp_table>;
0479 devfreq = <&bus_wcore>;
0480 status = "okay";
0481 };
0482
0483 &cpu0 {
0484 cpu-supply = <&buck6_reg>;
0485 };
0486
0487 &cpu4 {
0488 cpu-supply = <&buck2_reg>;
0489 };
0490
0491 &dmc {
0492 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
0493 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
0494 device-handle = <&samsung_K3QF2F20DB>;
0495 operating-points-v2 = <&dmc_opp_table>;
0496 vdd-supply = <&buck1_reg>;
0497 status = "okay";
0498 };
0499
0500 &hsi2c_4 {
0501 status = "okay";
0502
0503 pmic@66 {
0504 compatible = "samsung,s2mps11-pmic";
0505 reg = <0x66>;
0506 samsung,s2mps11-acokb-ground;
0507
0508 interrupt-parent = <&gpx0>;
0509 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0510 pinctrl-names = "default";
0511 pinctrl-0 = <&s2mps11_irq>;
0512 wakeup-source;
0513
0514 s2mps11_osc: clocks {
0515 compatible = "samsung,s2mps11-clk";
0516 #clock-cells = <1>;
0517 clock-output-names = "s2mps11_ap",
0518 "s2mps11_cp", "s2mps11_bt";
0519 };
0520
0521 regulators {
0522 ldo1_reg: LDO1 {
0523 regulator-name = "vdd_ldo1";
0524 regulator-min-microvolt = <1000000>;
0525 regulator-max-microvolt = <1000000>;
0526 regulator-always-on;
0527 };
0528
0529 ldo2_reg: LDO2 {
0530 regulator-name = "vdd_ldo2";
0531 regulator-min-microvolt = <1800000>;
0532 regulator-max-microvolt = <1800000>;
0533 regulator-always-on;
0534 };
0535
0536 ldo3_reg: LDO3 {
0537 regulator-name = "vddq_mmc0";
0538 regulator-min-microvolt = <1800000>;
0539 regulator-max-microvolt = <1800000>;
0540 };
0541
0542 ldo4_reg: LDO4 {
0543 regulator-name = "vdd_adc";
0544 regulator-min-microvolt = <1800000>;
0545 regulator-max-microvolt = <1800000>;
0546
0547 regulator-state-mem {
0548 regulator-off-in-suspend;
0549 };
0550 };
0551
0552 ldo5_reg: LDO5 {
0553 regulator-name = "vdd_ldo5";
0554 regulator-min-microvolt = <1800000>;
0555 regulator-max-microvolt = <1800000>;
0556 regulator-always-on;
0557
0558 regulator-state-mem {
0559 regulator-off-in-suspend;
0560 };
0561 };
0562
0563 ldo6_reg: LDO6 {
0564 regulator-name = "vdd_ldo6";
0565 regulator-min-microvolt = <1000000>;
0566 regulator-max-microvolt = <1000000>;
0567 regulator-always-on;
0568
0569 regulator-state-mem {
0570 regulator-off-in-suspend;
0571 };
0572 };
0573
0574 ldo7_reg: LDO7 {
0575 regulator-name = "vdd_ldo7";
0576 regulator-min-microvolt = <1800000>;
0577 regulator-max-microvolt = <1800000>;
0578 regulator-always-on;
0579
0580 regulator-state-mem {
0581 regulator-off-in-suspend;
0582 };
0583 };
0584
0585 ldo8_reg: LDO8 {
0586 regulator-name = "vdd_ldo8";
0587 regulator-min-microvolt = <1800000>;
0588 regulator-max-microvolt = <1800000>;
0589 regulator-always-on;
0590
0591 regulator-state-mem {
0592 regulator-off-in-suspend;
0593 };
0594 };
0595
0596 ldo9_reg: LDO9 {
0597 regulator-name = "vdd_ldo9";
0598 regulator-min-microvolt = <3000000>;
0599 regulator-max-microvolt = <3000000>;
0600 regulator-always-on;
0601
0602 regulator-state-mem {
0603 regulator-off-in-suspend;
0604 };
0605 };
0606
0607 ldo10_reg: LDO10 {
0608 regulator-name = "vdd_ldo10";
0609 regulator-min-microvolt = <1800000>;
0610 regulator-max-microvolt = <1800000>;
0611 regulator-always-on;
0612
0613 regulator-state-mem {
0614 regulator-off-in-suspend;
0615 };
0616 };
0617
0618 ldo11_reg: LDO11 {
0619 regulator-name = "vdd_ldo11";
0620 regulator-min-microvolt = <1000000>;
0621 regulator-max-microvolt = <1000000>;
0622 regulator-always-on;
0623
0624 regulator-state-mem {
0625 regulator-off-in-suspend;
0626 };
0627 };
0628
0629 ldo12_reg: LDO12 {
0630 /* Unused */
0631 regulator-name = "vdd_ldo12";
0632 regulator-min-microvolt = <800000>;
0633 regulator-max-microvolt = <2375000>;
0634 };
0635
0636 ldo13_reg: LDO13 {
0637 regulator-name = "vddq_mmc2";
0638 regulator-min-microvolt = <1800000>;
0639 regulator-max-microvolt = <2800000>;
0640
0641 regulator-state-mem {
0642 regulator-off-in-suspend;
0643 };
0644 };
0645
0646 ldo14_reg: LDO14 {
0647 /* Unused */
0648 regulator-name = "vdd_ldo14";
0649 regulator-min-microvolt = <800000>;
0650 regulator-max-microvolt = <3950000>;
0651 };
0652
0653 ldo15_reg: LDO15 {
0654 regulator-name = "vdd_ldo15";
0655 regulator-min-microvolt = <3300000>;
0656 regulator-max-microvolt = <3300000>;
0657 regulator-always-on;
0658
0659 regulator-state-mem {
0660 regulator-off-in-suspend;
0661 };
0662 };
0663
0664 ldo16_reg: LDO16 {
0665 /* Unused */
0666 regulator-name = "vdd_ldo16";
0667 regulator-min-microvolt = <800000>;
0668 regulator-max-microvolt = <3950000>;
0669 };
0670
0671 ldo17_reg: LDO17 {
0672 regulator-name = "vdd_ldo17";
0673 regulator-min-microvolt = <3300000>;
0674 regulator-max-microvolt = <3300000>;
0675 regulator-always-on;
0676
0677 regulator-state-mem {
0678 regulator-off-in-suspend;
0679 };
0680 };
0681
0682 ldo18_reg: LDO18 {
0683 regulator-name = "vdd_emmc_1V8";
0684 regulator-min-microvolt = <1800000>;
0685 regulator-max-microvolt = <1800000>;
0686
0687 regulator-state-mem {
0688 regulator-off-in-suspend;
0689 };
0690 };
0691
0692 ldo19_reg: LDO19 {
0693 regulator-name = "vdd_sd";
0694 regulator-min-microvolt = <2800000>;
0695 regulator-max-microvolt = <2800000>;
0696
0697 regulator-state-mem {
0698 regulator-off-in-suspend;
0699 };
0700 };
0701
0702 ldo20_reg: LDO20 {
0703 /* Unused */
0704 regulator-name = "vdd_ldo20";
0705 regulator-min-microvolt = <800000>;
0706 regulator-max-microvolt = <3950000>;
0707 };
0708
0709 ldo21_reg: LDO21 {
0710 /* Unused */
0711 regulator-name = "vdd_ldo21";
0712 regulator-min-microvolt = <800000>;
0713 regulator-max-microvolt = <3950000>;
0714 };
0715
0716 ldo22_reg: LDO22 {
0717 /* Unused */
0718 regulator-name = "vdd_ldo22";
0719 regulator-min-microvolt = <800000>;
0720 regulator-max-microvolt = <2375000>;
0721 };
0722
0723 ldo23_reg: LDO23 {
0724 regulator-name = "vdd_mifs";
0725 regulator-min-microvolt = <1100000>;
0726 regulator-max-microvolt = <1100000>;
0727 regulator-always-on;
0728
0729 regulator-state-mem {
0730 regulator-off-in-suspend;
0731 };
0732 };
0733
0734 ldo24_reg: LDO24 {
0735 /* Unused */
0736 regulator-name = "vdd_ldo24";
0737 regulator-min-microvolt = <800000>;
0738 regulator-max-microvolt = <3950000>;
0739 };
0740
0741 ldo25_reg: LDO25 {
0742 /* Unused */
0743 regulator-name = "vdd_ldo25";
0744 regulator-min-microvolt = <800000>;
0745 regulator-max-microvolt = <3950000>;
0746 };
0747
0748 ldo26_reg: LDO26 {
0749 /* Used on XU3, XU3-Lite and XU4 */
0750 regulator-name = "vdd_ldo26";
0751 regulator-min-microvolt = <800000>;
0752 regulator-max-microvolt = <3950000>;
0753
0754 regulator-state-mem {
0755 regulator-off-in-suspend;
0756 };
0757 };
0758
0759 ldo27_reg: LDO27 {
0760 regulator-name = "vdd_g3ds";
0761 regulator-min-microvolt = <1000000>;
0762 regulator-max-microvolt = <1000000>;
0763 regulator-always-on;
0764
0765 regulator-state-mem {
0766 regulator-off-in-suspend;
0767 };
0768 };
0769
0770 ldo28_reg: LDO28 {
0771 /* Used on XU3 */
0772 regulator-name = "vdd_ldo28";
0773 regulator-min-microvolt = <800000>;
0774 regulator-max-microvolt = <3950000>;
0775
0776 regulator-state-mem {
0777 regulator-off-in-suspend;
0778 };
0779 };
0780
0781 ldo29_reg: LDO29 {
0782 /* Unused */
0783 regulator-name = "vdd_ldo29";
0784 regulator-min-microvolt = <800000>;
0785 regulator-max-microvolt = <3950000>;
0786 };
0787
0788 ldo30_reg: LDO30 {
0789 /* Unused */
0790 regulator-name = "vdd_ldo30";
0791 regulator-min-microvolt = <800000>;
0792 regulator-max-microvolt = <3950000>;
0793 };
0794
0795 ldo31_reg: LDO31 {
0796 /* Unused */
0797 regulator-name = "vdd_ldo31";
0798 regulator-min-microvolt = <800000>;
0799 regulator-max-microvolt = <3950000>;
0800 };
0801
0802 ldo32_reg: LDO32 {
0803 /* Unused */
0804 regulator-name = "vdd_ldo32";
0805 regulator-min-microvolt = <800000>;
0806 regulator-max-microvolt = <3950000>;
0807 };
0808
0809 ldo33_reg: LDO33 {
0810 /* Unused */
0811 regulator-name = "vdd_ldo33";
0812 regulator-min-microvolt = <800000>;
0813 regulator-max-microvolt = <3950000>;
0814 };
0815
0816 ldo34_reg: LDO34 {
0817 /* Unused */
0818 regulator-name = "vdd_ldo34";
0819 regulator-min-microvolt = <800000>;
0820 regulator-max-microvolt = <3950000>;
0821 };
0822
0823 ldo35_reg: LDO35 {
0824 /* Unused */
0825 regulator-name = "vdd_ldo35";
0826 regulator-min-microvolt = <800000>;
0827 regulator-max-microvolt = <2375000>;
0828 };
0829
0830 ldo36_reg: LDO36 {
0831 /* Unused */
0832 regulator-name = "vdd_ldo36";
0833 regulator-min-microvolt = <800000>;
0834 regulator-max-microvolt = <3950000>;
0835 };
0836
0837 ldo37_reg: LDO37 {
0838 /* Unused */
0839 regulator-name = "vdd_ldo37";
0840 regulator-min-microvolt = <800000>;
0841 regulator-max-microvolt = <3950000>;
0842 };
0843
0844 ldo38_reg: LDO38 {
0845 /* Unused */
0846 regulator-name = "vdd_ldo38";
0847 regulator-min-microvolt = <800000>;
0848 regulator-max-microvolt = <3950000>;
0849 };
0850
0851 buck1_reg: BUCK1 {
0852 regulator-name = "vdd_mif";
0853 regulator-min-microvolt = <800000>;
0854 regulator-max-microvolt = <1300000>;
0855 regulator-always-on;
0856 regulator-boot-on;
0857
0858 regulator-state-mem {
0859 regulator-off-in-suspend;
0860 };
0861 };
0862
0863 buck2_reg: BUCK2 {
0864 regulator-name = "vdd_arm";
0865 regulator-min-microvolt = <800000>;
0866 regulator-max-microvolt = <1500000>;
0867 regulator-always-on;
0868 regulator-boot-on;
0869 regulator-coupled-with = <&buck3_reg>;
0870 regulator-coupled-max-spread = <300000>;
0871
0872 regulator-state-mem {
0873 regulator-off-in-suspend;
0874 };
0875 };
0876
0877 buck3_reg: BUCK3 {
0878 regulator-name = "vdd_int";
0879 regulator-min-microvolt = <800000>;
0880 regulator-max-microvolt = <1400000>;
0881 regulator-always-on;
0882 regulator-boot-on;
0883 regulator-coupled-with = <&buck2_reg>;
0884 regulator-coupled-max-spread = <300000>;
0885
0886 regulator-state-mem {
0887 regulator-off-in-suspend;
0888 };
0889 };
0890
0891 buck4_reg: BUCK4 {
0892 regulator-name = "vdd_g3d";
0893 regulator-min-microvolt = <800000>;
0894 regulator-max-microvolt = <1400000>;
0895 regulator-boot-on;
0896 regulator-always-on;
0897
0898 regulator-state-mem {
0899 regulator-off-in-suspend;
0900 };
0901 };
0902
0903 buck5_reg: BUCK5 {
0904 regulator-name = "vdd_mem";
0905 regulator-min-microvolt = <800000>;
0906 regulator-max-microvolt = <1400000>;
0907 regulator-always-on;
0908 regulator-boot-on;
0909 };
0910
0911 buck6_reg: BUCK6 {
0912 regulator-name = "vdd_kfc";
0913 regulator-min-microvolt = <800000>;
0914 regulator-max-microvolt = <1500000>;
0915 regulator-always-on;
0916 regulator-boot-on;
0917
0918 regulator-state-mem {
0919 regulator-off-in-suspend;
0920 };
0921 };
0922
0923 buck7_reg: BUCK7 {
0924 regulator-name = "vdd_1.35v_ldo";
0925 regulator-min-microvolt = <1200000>;
0926 regulator-max-microvolt = <1500000>;
0927 regulator-always-on;
0928 regulator-boot-on;
0929 };
0930
0931 buck8_reg: BUCK8 {
0932 regulator-name = "vdd_2.0v_ldo";
0933 regulator-min-microvolt = <1800000>;
0934 regulator-max-microvolt = <2100000>;
0935 regulator-always-on;
0936 regulator-boot-on;
0937 };
0938
0939 buck9_reg: BUCK9 {
0940 regulator-name = "vdd_2.8v_ldo";
0941 regulator-min-microvolt = <3000000>;
0942 regulator-max-microvolt = <3750000>;
0943 regulator-always-on;
0944 regulator-boot-on;
0945
0946 regulator-state-mem {
0947 regulator-off-in-suspend;
0948 };
0949 };
0950
0951 buck10_reg: BUCK10 {
0952 regulator-name = "vdd_vmem";
0953 regulator-min-microvolt = <2850000>;
0954 regulator-max-microvolt = <2850000>;
0955
0956 regulator-state-mem {
0957 regulator-off-in-suspend;
0958 };
0959 };
0960 };
0961 };
0962 };
0963
0964 &mmc_2 {
0965 status = "okay";
0966 card-detect-delay = <200>;
0967 samsung,dw-mshc-ciu-div = <3>;
0968 samsung,dw-mshc-sdr-timing = <0 4>;
0969 samsung,dw-mshc-ddr-timing = <0 2>;
0970 pinctrl-names = "default";
0971 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
0972 bus-width = <4>;
0973 cap-sd-highspeed;
0974 max-frequency = <200000000>;
0975 vmmc-supply = <&ldo19_reg>;
0976 vqmmc-supply = <&ldo13_reg>;
0977 sd-uhs-sdr50;
0978 sd-uhs-sdr104;
0979 sd-uhs-ddr50;
0980 };
0981
0982 &nocp_mem0_0 {
0983 status = "okay";
0984 };
0985
0986 &nocp_mem0_1 {
0987 status = "okay";
0988 };
0989
0990 &nocp_mem1_0 {
0991 status = "okay";
0992 };
0993
0994 &nocp_mem1_1 {
0995 status = "okay";
0996 };
0997
0998 &pinctrl_0 {
0999 s2mps11_irq: s2mps11-irq-pins {
1000 samsung,pins = "gpx0-4";
1001 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
1002 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1003 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1004 };
1005 };
1006
1007 &ppmu_dmc0_0 {
1008 status = "okay";
1009 };
1010
1011 &ppmu_dmc0_1 {
1012 status = "okay";
1013 };
1014
1015 &ppmu_dmc1_0 {
1016 status = "okay";
1017 };
1018
1019 &ppmu_dmc1_1 {
1020 status = "okay";
1021 };
1022
1023 &tmu_cpu0 {
1024 vtmu-supply = <&ldo7_reg>;
1025 };
1026
1027 &tmu_cpu1 {
1028 vtmu-supply = <&ldo7_reg>;
1029 };
1030
1031 &tmu_cpu2 {
1032 vtmu-supply = <&ldo7_reg>;
1033 };
1034
1035 &tmu_cpu3 {
1036 vtmu-supply = <&ldo7_reg>;
1037 };
1038
1039 &tmu_gpu {
1040 vtmu-supply = <&ldo7_reg>;
1041 };
1042
1043 &gpu {
1044 mali-supply = <&buck4_reg>;
1045 status = "okay";
1046 };
1047
1048 &rtc {
1049 status = "okay";
1050 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
1051 clock-names = "rtc", "rtc_src";
1052 };
1053
1054 &usbdrd_dwc3_0 {
1055 dr_mode = "host";
1056 };
1057
1058 /* usbdrd_dwc3_1 mode customized in each board */
1059
1060 &usbdrd3_0 {
1061 vdd33-supply = <&ldo9_reg>;
1062 vdd10-supply = <&ldo11_reg>;
1063 };
1064
1065 &usbdrd3_1 {
1066 vdd33-supply = <&ldo9_reg>;
1067 vdd10-supply = <&ldo11_reg>;
1068 };
