0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos5422 SoC cpu device tree source
0004 *
0005 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
0009 *
0010 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
0011 * but particular boards choose different booting order.
0012 *
0013 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
0014 * booting cluster (big or LITTLE) is chosen by IROM code by reading
0015 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
0016 * from the LITTLE: Cortex-A7.
0017 */
0018
0019 / {
0020 cpus {
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023
0024 cpu-map {
0025 cluster0 {
0026 core0 {
0027 cpu = <&cpu0>;
0028 };
0029 core1 {
0030 cpu = <&cpu1>;
0031 };
0032 core2 {
0033 cpu = <&cpu2>;
0034 };
0035 core3 {
0036 cpu = <&cpu3>;
0037 };
0038 };
0039
0040 cluster1 {
0041 core0 {
0042 cpu = <&cpu4>;
0043 };
0044 core1 {
0045 cpu = <&cpu5>;
0046 };
0047 core2 {
0048 cpu = <&cpu6>;
0049 };
0050 core3 {
0051 cpu = <&cpu7>;
0052 };
0053 };
0054 };
0055
0056 cpu0: cpu@100 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a7";
0059 reg = <0x100>;
0060 clocks = <&clock CLK_KFC_CLK>;
0061 clock-frequency = <1000000000>;
0062 cci-control-port = <&cci_control0>;
0063 operating-points-v2 = <&cluster_a7_opp_table>;
0064 #cooling-cells = <2>; /* min followed by max */
0065 capacity-dmips-mhz = <539>;
0066 dynamic-power-coefficient = <90>;
0067 };
0068
0069 cpu1: cpu@101 {
0070 device_type = "cpu";
0071 compatible = "arm,cortex-a7";
0072 reg = <0x101>;
0073 clocks = <&clock CLK_KFC_CLK>;
0074 clock-frequency = <1000000000>;
0075 cci-control-port = <&cci_control0>;
0076 operating-points-v2 = <&cluster_a7_opp_table>;
0077 #cooling-cells = <2>; /* min followed by max */
0078 capacity-dmips-mhz = <539>;
0079 dynamic-power-coefficient = <90>;
0080 };
0081
0082 cpu2: cpu@102 {
0083 device_type = "cpu";
0084 compatible = "arm,cortex-a7";
0085 reg = <0x102>;
0086 clocks = <&clock CLK_KFC_CLK>;
0087 clock-frequency = <1000000000>;
0088 cci-control-port = <&cci_control0>;
0089 operating-points-v2 = <&cluster_a7_opp_table>;
0090 #cooling-cells = <2>; /* min followed by max */
0091 capacity-dmips-mhz = <539>;
0092 dynamic-power-coefficient = <90>;
0093 };
0094
0095 cpu3: cpu@103 {
0096 device_type = "cpu";
0097 compatible = "arm,cortex-a7";
0098 reg = <0x103>;
0099 clocks = <&clock CLK_KFC_CLK>;
0100 clock-frequency = <1000000000>;
0101 cci-control-port = <&cci_control0>;
0102 operating-points-v2 = <&cluster_a7_opp_table>;
0103 #cooling-cells = <2>; /* min followed by max */
0104 capacity-dmips-mhz = <539>;
0105 dynamic-power-coefficient = <90>;
0106 };
0107
0108 cpu4: cpu@0 {
0109 device_type = "cpu";
0110 compatible = "arm,cortex-a15";
0111 reg = <0x0>;
0112 clocks = <&clock CLK_ARM_CLK>;
0113 clock-frequency = <1800000000>;
0114 cci-control-port = <&cci_control1>;
0115 operating-points-v2 = <&cluster_a15_opp_table>;
0116 #cooling-cells = <2>; /* min followed by max */
0117 capacity-dmips-mhz = <1024>;
0118 dynamic-power-coefficient = <310>;
0119 };
0120
0121 cpu5: cpu@1 {
0122 device_type = "cpu";
0123 compatible = "arm,cortex-a15";
0124 reg = <0x1>;
0125 clocks = <&clock CLK_ARM_CLK>;
0126 clock-frequency = <1800000000>;
0127 cci-control-port = <&cci_control1>;
0128 operating-points-v2 = <&cluster_a15_opp_table>;
0129 #cooling-cells = <2>; /* min followed by max */
0130 capacity-dmips-mhz = <1024>;
0131 dynamic-power-coefficient = <310>;
0132 };
0133
0134 cpu6: cpu@2 {
0135 device_type = "cpu";
0136 compatible = "arm,cortex-a15";
0137 reg = <0x2>;
0138 clocks = <&clock CLK_ARM_CLK>;
0139 clock-frequency = <1800000000>;
0140 cci-control-port = <&cci_control1>;
0141 operating-points-v2 = <&cluster_a15_opp_table>;
0142 #cooling-cells = <2>; /* min followed by max */
0143 capacity-dmips-mhz = <1024>;
0144 dynamic-power-coefficient = <310>;
0145 };
0146
0147 cpu7: cpu@3 {
0148 device_type = "cpu";
0149 compatible = "arm,cortex-a15";
0150 reg = <0x3>;
0151 clocks = <&clock CLK_ARM_CLK>;
0152 clock-frequency = <1800000000>;
0153 cci-control-port = <&cci_control1>;
0154 operating-points-v2 = <&cluster_a15_opp_table>;
0155 #cooling-cells = <2>; /* min followed by max */
0156 capacity-dmips-mhz = <1024>;
0157 dynamic-power-coefficient = <310>;
0158 };
0159 };
0160 };
0161
0162 &arm_a7_pmu {
0163 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0164 status = "okay";
0165 };
0166
0167 &arm_a15_pmu {
0168 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
0169 status = "okay";
0170 };
