0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos5420 SoC device tree source
0004 *
0005 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * Samsung Exynos5420 SoC device nodes are listed in this file.
0009 * Exynos5420 based board files can include this file and provide
0010 * values for board specfic bindings.
0011 */
0012
0013 #include "exynos54xx.dtsi"
0014 #include <dt-bindings/clock/exynos5420.h>
0015 #include <dt-bindings/clock/exynos-audss-clk.h>
0016 #include <dt-bindings/interrupt-controller/arm-gic.h>
0017
0018 / {
0019 compatible = "samsung,exynos5420", "samsung,exynos5";
0020
0021 aliases {
0022 mshc0 = &mmc_0;
0023 mshc1 = &mmc_1;
0024 mshc2 = &mmc_2;
0025 pinctrl0 = &pinctrl_0;
0026 pinctrl1 = &pinctrl_1;
0027 pinctrl2 = &pinctrl_2;
0028 pinctrl3 = &pinctrl_3;
0029 pinctrl4 = &pinctrl_4;
0030 i2c8 = &hsi2c_8;
0031 i2c9 = &hsi2c_9;
0032 i2c10 = &hsi2c_10;
0033 gsc0 = &gsc_0;
0034 gsc1 = &gsc_1;
0035 spi0 = &spi_0;
0036 spi1 = &spi_1;
0037 spi2 = &spi_2;
0038 };
0039
0040 /*
0041 * The 'cpus' node is not present here but instead it is provided
0042 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
0043 */
0044
0045 cluster_a15_opp_table: opp-table0 {
0046 compatible = "operating-points-v2";
0047 opp-shared;
0048
0049 opp-1800000000 {
0050 opp-hz = /bits/ 64 <1800000000>;
0051 opp-microvolt = <1250000 1250000 1500000>;
0052 clock-latency-ns = <140000>;
0053 };
0054 opp-1700000000 {
0055 opp-hz = /bits/ 64 <1700000000>;
0056 opp-microvolt = <1212500 1212500 1500000>;
0057 clock-latency-ns = <140000>;
0058 };
0059 opp-1600000000 {
0060 opp-hz = /bits/ 64 <1600000000>;
0061 opp-microvolt = <1175000 1175000 1500000>;
0062 clock-latency-ns = <140000>;
0063 };
0064 opp-1500000000 {
0065 opp-hz = /bits/ 64 <1500000000>;
0066 opp-microvolt = <1137500 1137500 1500000>;
0067 clock-latency-ns = <140000>;
0068 };
0069 opp-1400000000 {
0070 opp-hz = /bits/ 64 <1400000000>;
0071 opp-microvolt = <1112500 1112500 1500000>;
0072 clock-latency-ns = <140000>;
0073 };
0074 opp-1300000000 {
0075 opp-hz = /bits/ 64 <1300000000>;
0076 opp-microvolt = <1062500 1062500 1500000>;
0077 clock-latency-ns = <140000>;
0078 };
0079 opp-1200000000 {
0080 opp-hz = /bits/ 64 <1200000000>;
0081 opp-microvolt = <1037500 1037500 1500000>;
0082 clock-latency-ns = <140000>;
0083 };
0084 opp-1100000000 {
0085 opp-hz = /bits/ 64 <1100000000>;
0086 opp-microvolt = <1012500 1012500 1500000>;
0087 clock-latency-ns = <140000>;
0088 };
0089 opp-1000000000 {
0090 opp-hz = /bits/ 64 <1000000000>;
0091 opp-microvolt = < 987500 987500 1500000>;
0092 clock-latency-ns = <140000>;
0093 };
0094 opp-900000000 {
0095 opp-hz = /bits/ 64 <900000000>;
0096 opp-microvolt = < 962500 962500 1500000>;
0097 clock-latency-ns = <140000>;
0098 };
0099 opp-800000000 {
0100 opp-hz = /bits/ 64 <800000000>;
0101 opp-microvolt = < 937500 937500 1500000>;
0102 clock-latency-ns = <140000>;
0103 };
0104 opp-700000000 {
0105 opp-hz = /bits/ 64 <700000000>;
0106 opp-microvolt = < 912500 912500 1500000>;
0107 clock-latency-ns = <140000>;
0108 };
0109 };
0110
0111 cluster_a7_opp_table: opp-table1 {
0112 compatible = "operating-points-v2";
0113 opp-shared;
0114
0115 opp-1300000000 {
0116 opp-hz = /bits/ 64 <1300000000>;
0117 opp-microvolt = <1275000>;
0118 clock-latency-ns = <140000>;
0119 };
0120 opp-1200000000 {
0121 opp-hz = /bits/ 64 <1200000000>;
0122 opp-microvolt = <1212500>;
0123 clock-latency-ns = <140000>;
0124 };
0125 opp-1100000000 {
0126 opp-hz = /bits/ 64 <1100000000>;
0127 opp-microvolt = <1162500>;
0128 clock-latency-ns = <140000>;
0129 };
0130 opp-1000000000 {
0131 opp-hz = /bits/ 64 <1000000000>;
0132 opp-microvolt = <1112500>;
0133 clock-latency-ns = <140000>;
0134 };
0135 opp-900000000 {
0136 opp-hz = /bits/ 64 <900000000>;
0137 opp-microvolt = <1062500>;
0138 clock-latency-ns = <140000>;
0139 };
0140 opp-800000000 {
0141 opp-hz = /bits/ 64 <800000000>;
0142 opp-microvolt = <1025000>;
0143 clock-latency-ns = <140000>;
0144 };
0145 opp-700000000 {
0146 opp-hz = /bits/ 64 <700000000>;
0147 opp-microvolt = <975000>;
0148 clock-latency-ns = <140000>;
0149 };
0150 opp-600000000 {
0151 opp-hz = /bits/ 64 <600000000>;
0152 opp-microvolt = <937500>;
0153 clock-latency-ns = <140000>;
0154 };
0155 };
0156
0157 soc: soc {
0158 cci: cci@10d20000 {
0159 compatible = "arm,cci-400";
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162 reg = <0x10d20000 0x1000>;
0163 ranges = <0x0 0x10d20000 0x6000>;
0164
0165 cci_control0: slave-if@4000 {
0166 compatible = "arm,cci-400-ctrl-if";
0167 interface-type = "ace";
0168 reg = <0x4000 0x1000>;
0169 };
0170 cci_control1: slave-if@5000 {
0171 compatible = "arm,cci-400-ctrl-if";
0172 interface-type = "ace";
0173 reg = <0x5000 0x1000>;
0174 };
0175 };
0176
0177 clock: clock-controller@10010000 {
0178 compatible = "samsung,exynos5420-clock", "syscon";
0179 reg = <0x10010000 0x30000>;
0180 #clock-cells = <1>;
0181 };
0182
0183 clock_audss: audss-clock-controller@3810000 {
0184 compatible = "samsung,exynos5420-audss-clock";
0185 reg = <0x03810000 0x0C>;
0186 #clock-cells = <1>;
0187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
0188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
0189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
0190 power-domains = <&mau_pd>;
0191 };
0192
0193 mfc: codec@11000000 {
0194 compatible = "samsung,mfc-v7";
0195 reg = <0x11000000 0x10000>;
0196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0197 clocks = <&clock CLK_MFC>;
0198 clock-names = "mfc";
0199 power-domains = <&mfc_pd>;
0200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
0201 iommu-names = "left", "right";
0202 };
0203
0204 mmc_0: mmc@12200000 {
0205 compatible = "samsung,exynos5420-dw-mshc-smu";
0206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0207 #address-cells = <1>;
0208 #size-cells = <0>;
0209 reg = <0x12200000 0x2000>;
0210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
0211 clock-names = "biu", "ciu";
0212 fifo-depth = <0x40>;
0213 status = "disabled";
0214 };
0215
0216 mmc_1: mmc@12210000 {
0217 compatible = "samsung,exynos5420-dw-mshc-smu";
0218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0219 #address-cells = <1>;
0220 #size-cells = <0>;
0221 reg = <0x12210000 0x2000>;
0222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
0223 clock-names = "biu", "ciu";
0224 fifo-depth = <0x40>;
0225 status = "disabled";
0226 };
0227
0228 mmc_2: mmc@12220000 {
0229 compatible = "samsung,exynos5420-dw-mshc";
0230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0231 #address-cells = <1>;
0232 #size-cells = <0>;
0233 reg = <0x12220000 0x1000>;
0234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
0235 clock-names = "biu", "ciu";
0236 fifo-depth = <0x40>;
0237 status = "disabled";
0238 };
0239
0240 dmc: memory-controller@10c20000 {
0241 compatible = "samsung,exynos5422-dmc";
0242 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
0243 clocks = <&clock CLK_FOUT_SPLL>,
0244 <&clock CLK_MOUT_SCLK_SPLL>,
0245 <&clock CLK_FF_DOUT_SPLL2>,
0246 <&clock CLK_FOUT_BPLL>,
0247 <&clock CLK_MOUT_BPLL>,
0248 <&clock CLK_SCLK_BPLL>,
0249 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
0250 <&clock CLK_MOUT_MCLK_CDREX>;
0251 clock-names = "fout_spll",
0252 "mout_sclk_spll",
0253 "ff_dout_spll2",
0254 "fout_bpll",
0255 "mout_bpll",
0256 "sclk_bpll",
0257 "mout_mx_mspll_ccore",
0258 "mout_mclk_cdrex";
0259 samsung,syscon-clk = <&clock>;
0260 status = "disabled";
0261 };
0262
0263 nocp_mem0_0: nocp@10ca1000 {
0264 compatible = "samsung,exynos5420-nocp";
0265 reg = <0x10CA1000 0x200>;
0266 status = "disabled";
0267 };
0268
0269 nocp_mem0_1: nocp@10ca1400 {
0270 compatible = "samsung,exynos5420-nocp";
0271 reg = <0x10CA1400 0x200>;
0272 status = "disabled";
0273 };
0274
0275 nocp_mem1_0: nocp@10ca1800 {
0276 compatible = "samsung,exynos5420-nocp";
0277 reg = <0x10CA1800 0x200>;
0278 status = "disabled";
0279 };
0280
0281 nocp_mem1_1: nocp@10ca1c00 {
0282 compatible = "samsung,exynos5420-nocp";
0283 reg = <0x10CA1C00 0x200>;
0284 status = "disabled";
0285 };
0286
0287 nocp_g3d_0: nocp@11a51000 {
0288 compatible = "samsung,exynos5420-nocp";
0289 reg = <0x11A51000 0x200>;
0290 status = "disabled";
0291 };
0292
0293 nocp_g3d_1: nocp@11a51400 {
0294 compatible = "samsung,exynos5420-nocp";
0295 reg = <0x11A51400 0x200>;
0296 status = "disabled";
0297 };
0298
0299 ppmu_dmc0_0: ppmu@10d00000 {
0300 compatible = "samsung,exynos-ppmu";
0301 reg = <0x10d00000 0x2000>;
0302 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
0303 clock-names = "ppmu";
0304 events {
0305 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
0306 event-name = "ppmu-event3-dmc0-0";
0307 };
0308 };
0309 };
0310
0311 ppmu_dmc0_1: ppmu@10d10000 {
0312 compatible = "samsung,exynos-ppmu";
0313 reg = <0x10d10000 0x2000>;
0314 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
0315 clock-names = "ppmu";
0316 events {
0317 ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
0318 event-name = "ppmu-event3-dmc0-1";
0319 };
0320 };
0321 };
0322
0323 ppmu_dmc1_0: ppmu@10d60000 {
0324 compatible = "samsung,exynos-ppmu";
0325 reg = <0x10d60000 0x2000>;
0326 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
0327 clock-names = "ppmu";
0328 events {
0329 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
0330 event-name = "ppmu-event3-dmc1-0";
0331 };
0332 };
0333 };
0334
0335 ppmu_dmc1_1: ppmu@10d70000 {
0336 compatible = "samsung,exynos-ppmu";
0337 reg = <0x10d70000 0x2000>;
0338 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
0339 clock-names = "ppmu";
0340 events {
0341 ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
0342 event-name = "ppmu-event3-dmc1-1";
0343 };
0344 };
0345 };
0346
0347 gsc_pd: power-domain@10044000 {
0348 compatible = "samsung,exynos4210-pd";
0349 reg = <0x10044000 0x20>;
0350 #power-domain-cells = <0>;
0351 label = "GSC";
0352 };
0353
0354 isp_pd: power-domain@10044020 {
0355 compatible = "samsung,exynos4210-pd";
0356 reg = <0x10044020 0x20>;
0357 #power-domain-cells = <0>;
0358 label = "ISP";
0359 };
0360
0361 mfc_pd: power-domain@10044060 {
0362 compatible = "samsung,exynos4210-pd";
0363 reg = <0x10044060 0x20>;
0364 #power-domain-cells = <0>;
0365 label = "MFC";
0366 };
0367
0368 g3d_pd: power-domain@10044080 {
0369 compatible = "samsung,exynos4210-pd";
0370 reg = <0x10044080 0x20>;
0371 #power-domain-cells = <0>;
0372 label = "G3D";
0373 };
0374
0375 disp_pd: power-domain@100440c0 {
0376 compatible = "samsung,exynos4210-pd";
0377 reg = <0x100440C0 0x20>;
0378 #power-domain-cells = <0>;
0379 label = "DISP";
0380 };
0381
0382 mau_pd: power-domain@100440e0 {
0383 compatible = "samsung,exynos4210-pd";
0384 reg = <0x100440E0 0x20>;
0385 #power-domain-cells = <0>;
0386 label = "MAU";
0387 };
0388
0389 msc_pd: power-domain@10044120 {
0390 compatible = "samsung,exynos4210-pd";
0391 reg = <0x10044120 0x20>;
0392 #power-domain-cells = <0>;
0393 label = "MSC";
0394 };
0395
0396 pinctrl_0: pinctrl@13400000 {
0397 compatible = "samsung,exynos5420-pinctrl";
0398 reg = <0x13400000 0x1000>;
0399 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0400
0401 wakeup-interrupt-controller {
0402 compatible = "samsung,exynos4210-wakeup-eint";
0403 interrupt-parent = <&gic>;
0404 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0405 };
0406 };
0407
0408 pinctrl_1: pinctrl@13410000 {
0409 compatible = "samsung,exynos5420-pinctrl";
0410 reg = <0x13410000 0x1000>;
0411 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0412 };
0413
0414 pinctrl_2: pinctrl@14000000 {
0415 compatible = "samsung,exynos5420-pinctrl";
0416 reg = <0x14000000 0x1000>;
0417 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0418 };
0419
0420 pinctrl_3: pinctrl@14010000 {
0421 compatible = "samsung,exynos5420-pinctrl";
0422 reg = <0x14010000 0x1000>;
0423 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0424 };
0425
0426 pinctrl_4: pinctrl@3860000 {
0427 compatible = "samsung,exynos5420-pinctrl";
0428 reg = <0x03860000 0x1000>;
0429 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0430 power-domains = <&mau_pd>;
0431 };
0432
0433 adma: dma-controller@3880000 {
0434 compatible = "arm,pl330", "arm,primecell";
0435 reg = <0x03880000 0x1000>;
0436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0437 clocks = <&clock_audss EXYNOS_ADMA>;
0438 clock-names = "apb_pclk";
0439 #dma-cells = <1>;
0440 power-domains = <&mau_pd>;
0441 };
0442
0443 pdma0: dma-controller@121a0000 {
0444 compatible = "arm,pl330", "arm,primecell";
0445 reg = <0x121A0000 0x1000>;
0446 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0447 clocks = <&clock CLK_PDMA0>;
0448 clock-names = "apb_pclk";
0449 #dma-cells = <1>;
0450 };
0451
0452 pdma1: dma-controller@121b0000 {
0453 compatible = "arm,pl330", "arm,primecell";
0454 reg = <0x121B0000 0x1000>;
0455 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0456 clocks = <&clock CLK_PDMA1>;
0457 clock-names = "apb_pclk";
0458 #dma-cells = <1>;
0459 };
0460
0461 mdma0: dma-controller@10800000 {
0462 compatible = "arm,pl330", "arm,primecell";
0463 reg = <0x10800000 0x1000>;
0464 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0465 clocks = <&clock CLK_MDMA0>;
0466 clock-names = "apb_pclk";
0467 #dma-cells = <1>;
0468 };
0469
0470 mdma1: dma-controller@11c10000 {
0471 compatible = "arm,pl330", "arm,primecell";
0472 reg = <0x11C10000 0x1000>;
0473 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
0474 clocks = <&clock CLK_MDMA1>;
0475 clock-names = "apb_pclk";
0476 #dma-cells = <1>;
0477 /*
0478 * MDMA1 can support both secure and non-secure
0479 * AXI transactions. When this is enabled in
0480 * the kernel for boards that run in secure
0481 * mode, we are getting imprecise external
0482 * aborts causing the kernel to oops.
0483 */
0484 status = "disabled";
0485 };
0486
0487 i2s0: i2s@3830000 {
0488 compatible = "samsung,exynos5420-i2s";
0489 reg = <0x03830000 0x100>;
0490 dmas = <&adma 0>,
0491 <&adma 2>,
0492 <&adma 1>;
0493 dma-names = "tx", "rx", "tx-sec";
0494 clocks = <&clock_audss EXYNOS_I2S_BUS>,
0495 <&clock_audss EXYNOS_I2S_BUS>,
0496 <&clock_audss EXYNOS_SCLK_I2S>;
0497 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
0498 #clock-cells = <1>;
0499 clock-output-names = "i2s_cdclk0";
0500 #sound-dai-cells = <1>;
0501 samsung,idma-addr = <0x03000000>;
0502 pinctrl-names = "default";
0503 pinctrl-0 = <&i2s0_bus>;
0504 power-domains = <&mau_pd>;
0505 status = "disabled";
0506 };
0507
0508 i2s1: i2s@12d60000 {
0509 compatible = "samsung,exynos5420-i2s";
0510 reg = <0x12D60000 0x100>;
0511 dmas = <&pdma1 12>,
0512 <&pdma1 11>;
0513 dma-names = "tx", "rx";
0514 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
0515 clock-names = "iis", "i2s_opclk0";
0516 #clock-cells = <1>;
0517 clock-output-names = "i2s_cdclk1";
0518 #sound-dai-cells = <1>;
0519 pinctrl-names = "default";
0520 pinctrl-0 = <&i2s1_bus>;
0521 status = "disabled";
0522 };
0523
0524 i2s2: i2s@12d70000 {
0525 compatible = "samsung,exynos5420-i2s";
0526 reg = <0x12D70000 0x100>;
0527 dmas = <&pdma0 12>,
0528 <&pdma0 11>;
0529 dma-names = "tx", "rx";
0530 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
0531 clock-names = "iis", "i2s_opclk0";
0532 #clock-cells = <1>;
0533 clock-output-names = "i2s_cdclk2";
0534 #sound-dai-cells = <1>;
0535 pinctrl-names = "default";
0536 pinctrl-0 = <&i2s2_bus>;
0537 status = "disabled";
0538 };
0539
0540 spi_0: spi@12d20000 {
0541 compatible = "samsung,exynos4210-spi";
0542 reg = <0x12d20000 0x100>;
0543 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0544 dmas = <&pdma0 5
0545 &pdma0 4>;
0546 dma-names = "tx", "rx";
0547 #address-cells = <1>;
0548 #size-cells = <0>;
0549 pinctrl-names = "default";
0550 pinctrl-0 = <&spi0_bus>;
0551 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
0552 clock-names = "spi", "spi_busclk0";
0553 status = "disabled";
0554 };
0555
0556 spi_1: spi@12d30000 {
0557 compatible = "samsung,exynos4210-spi";
0558 reg = <0x12d30000 0x100>;
0559 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0560 dmas = <&pdma1 5
0561 &pdma1 4>;
0562 dma-names = "tx", "rx";
0563 #address-cells = <1>;
0564 #size-cells = <0>;
0565 pinctrl-names = "default";
0566 pinctrl-0 = <&spi1_bus>;
0567 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
0568 clock-names = "spi", "spi_busclk0";
0569 status = "disabled";
0570 };
0571
0572 spi_2: spi@12d40000 {
0573 compatible = "samsung,exynos4210-spi";
0574 reg = <0x12d40000 0x100>;
0575 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0576 dmas = <&pdma0 7
0577 &pdma0 6>;
0578 dma-names = "tx", "rx";
0579 #address-cells = <1>;
0580 #size-cells = <0>;
0581 pinctrl-names = "default";
0582 pinctrl-0 = <&spi2_bus>;
0583 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
0584 clock-names = "spi", "spi_busclk0";
0585 status = "disabled";
0586 };
0587
0588 dp_phy: dp-video-phy {
0589 compatible = "samsung,exynos5420-dp-video-phy";
0590 samsung,pmu-syscon = <&pmu_system_controller>;
0591 #phy-cells = <0>;
0592 };
0593
0594 mipi_phy: mipi-video-phy {
0595 compatible = "samsung,s5pv210-mipi-video-phy";
0596 syscon = <&pmu_system_controller>;
0597 #phy-cells = <1>;
0598 };
0599
0600 dsi@14500000 {
0601 compatible = "samsung,exynos5410-mipi-dsi";
0602 reg = <0x14500000 0x10000>;
0603 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0604 phys = <&mipi_phy 1>;
0605 phy-names = "dsim";
0606 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
0607 clock-names = "bus_clk", "pll_clk";
0608 #address-cells = <1>;
0609 #size-cells = <0>;
0610 status = "disabled";
0611 };
0612
0613 hsi2c_8: i2c@12e00000 {
0614 compatible = "samsung,exynos5250-hsi2c";
0615 reg = <0x12E00000 0x1000>;
0616 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0617 #address-cells = <1>;
0618 #size-cells = <0>;
0619 pinctrl-names = "default";
0620 pinctrl-0 = <&i2c8_hs_bus>;
0621 clocks = <&clock CLK_USI4>;
0622 clock-names = "hsi2c";
0623 status = "disabled";
0624 };
0625
0626 hsi2c_9: i2c@12e10000 {
0627 compatible = "samsung,exynos5250-hsi2c";
0628 reg = <0x12E10000 0x1000>;
0629 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0630 #address-cells = <1>;
0631 #size-cells = <0>;
0632 pinctrl-names = "default";
0633 pinctrl-0 = <&i2c9_hs_bus>;
0634 clocks = <&clock CLK_USI5>;
0635 clock-names = "hsi2c";
0636 status = "disabled";
0637 };
0638
0639 hsi2c_10: i2c@12e20000 {
0640 compatible = "samsung,exynos5250-hsi2c";
0641 reg = <0x12E20000 0x1000>;
0642 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0643 #address-cells = <1>;
0644 #size-cells = <0>;
0645 pinctrl-names = "default";
0646 pinctrl-0 = <&i2c10_hs_bus>;
0647 clocks = <&clock CLK_USI6>;
0648 clock-names = "hsi2c";
0649 status = "disabled";
0650 };
0651
0652 hdmi: hdmi@14530000 {
0653 compatible = "samsung,exynos5420-hdmi";
0654 reg = <0x14530000 0x70000>;
0655 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0656 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
0657 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
0658 <&clock CLK_MOUT_HDMI>;
0659 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
0660 "sclk_hdmiphy", "mout_hdmi";
0661 phy = <&hdmiphy>;
0662 samsung,syscon-phandle = <&pmu_system_controller>;
0663 status = "disabled";
0664 power-domains = <&disp_pd>;
0665 #sound-dai-cells = <0>;
0666 };
0667
0668 hdmiphy: hdmiphy@145d0000 {
0669 reg = <0x145D0000 0x20>;
0670 };
0671
0672 hdmicec: cec@101b0000 {
0673 compatible = "samsung,s5p-cec";
0674 reg = <0x101B0000 0x200>;
0675 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0676 clocks = <&clock CLK_HDMI_CEC>;
0677 clock-names = "hdmicec";
0678 samsung,syscon-phandle = <&pmu_system_controller>;
0679 hdmi-phandle = <&hdmi>;
0680 pinctrl-names = "default";
0681 pinctrl-0 = <&hdmi_cec>;
0682 status = "disabled";
0683 };
0684
0685 mixer: mixer@14450000 {
0686 compatible = "samsung,exynos5420-mixer";
0687 reg = <0x14450000 0x10000>;
0688 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0689 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
0690 <&clock CLK_SCLK_HDMI>;
0691 clock-names = "mixer", "hdmi", "sclk_hdmi";
0692 power-domains = <&disp_pd>;
0693 iommus = <&sysmmu_tv>;
0694 status = "disabled";
0695 };
0696
0697 rotator: rotator@11c00000 {
0698 compatible = "samsung,exynos5250-rotator";
0699 reg = <0x11C00000 0x64>;
0700 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0701 clocks = <&clock CLK_ROTATOR>;
0702 clock-names = "rotator";
0703 iommus = <&sysmmu_rotator>;
0704 };
0705
0706 gsc_0: video-scaler@13e00000 {
0707 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
0708 reg = <0x13e00000 0x1000>;
0709 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0710 clocks = <&clock CLK_GSCL0>;
0711 clock-names = "gscl";
0712 power-domains = <&gsc_pd>;
0713 iommus = <&sysmmu_gscl0>;
0714 };
0715
0716 gsc_1: video-scaler@13e10000 {
0717 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
0718 reg = <0x13e10000 0x1000>;
0719 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0720 clocks = <&clock CLK_GSCL1>;
0721 clock-names = "gscl";
0722 power-domains = <&gsc_pd>;
0723 iommus = <&sysmmu_gscl1>;
0724 };
0725
0726 gpu: gpu@11800000 {
0727 compatible = "samsung,exynos5420-mali", "arm,mali-t628";
0728 reg = <0x11800000 0x5000>;
0729 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
0730 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
0731 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0732 interrupt-names = "job", "mmu", "gpu";
0733
0734 clocks = <&clock CLK_G3D>;
0735 clock-names = "core";
0736 power-domains = <&g3d_pd>;
0737 operating-points-v2 = <&gpu_opp_table>;
0738
0739 status = "disabled";
0740 #cooling-cells = <2>;
0741
0742 gpu_opp_table: opp-table {
0743 compatible = "operating-points-v2";
0744
0745 opp-177000000 {
0746 opp-hz = /bits/ 64 <177000000>;
0747 opp-microvolt = <812500>;
0748 };
0749 opp-266000000 {
0750 opp-hz = /bits/ 64 <266000000>;
0751 opp-microvolt = <862500>;
0752 };
0753 opp-350000000 {
0754 opp-hz = /bits/ 64 <350000000>;
0755 opp-microvolt = <912500>;
0756 };
0757 opp-420000000 {
0758 opp-hz = /bits/ 64 <420000000>;
0759 opp-microvolt = <962500>;
0760 };
0761 opp-480000000 {
0762 opp-hz = /bits/ 64 <480000000>;
0763 opp-microvolt = <1000000>;
0764 };
0765 opp-543000000 {
0766 opp-hz = /bits/ 64 <543000000>;
0767 opp-microvolt = <1037500>;
0768 };
0769 opp-600000000 {
0770 opp-hz = /bits/ 64 <600000000>;
0771 opp-microvolt = <1150000>;
0772 };
0773 };
0774 };
0775
0776 scaler_0: scaler@12800000 {
0777 compatible = "samsung,exynos5420-scaler";
0778 reg = <0x12800000 0x1294>;
0779 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
0780 clocks = <&clock CLK_MSCL0>;
0781 clock-names = "mscl";
0782 power-domains = <&msc_pd>;
0783 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
0784 };
0785
0786 scaler_1: scaler@12810000 {
0787 compatible = "samsung,exynos5420-scaler";
0788 reg = <0x12810000 0x1294>;
0789 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
0790 clocks = <&clock CLK_MSCL1>;
0791 clock-names = "mscl";
0792 power-domains = <&msc_pd>;
0793 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
0794 };
0795
0796 scaler_2: scaler@12820000 {
0797 compatible = "samsung,exynos5420-scaler";
0798 reg = <0x12820000 0x1294>;
0799 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
0800 clocks = <&clock CLK_MSCL2>;
0801 clock-names = "mscl";
0802 power-domains = <&msc_pd>;
0803 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
0804 };
0805
0806 jpeg_0: jpeg@11f50000 {
0807 compatible = "samsung,exynos5420-jpeg";
0808 reg = <0x11F50000 0x1000>;
0809 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0810 clock-names = "jpeg";
0811 clocks = <&clock CLK_JPEG>;
0812 iommus = <&sysmmu_jpeg0>;
0813 };
0814
0815 jpeg_1: jpeg@11f60000 {
0816 compatible = "samsung,exynos5420-jpeg";
0817 reg = <0x11F60000 0x1000>;
0818 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
0819 clock-names = "jpeg";
0820 clocks = <&clock CLK_JPEG2>;
0821 iommus = <&sysmmu_jpeg1>;
0822 };
0823
0824 pmu_system_controller: system-controller@10040000 {
0825 compatible = "samsung,exynos5420-pmu", "syscon";
0826 reg = <0x10040000 0x5000>;
0827 clock-names = "clkout16";
0828 clocks = <&clock CLK_FIN_PLL>;
0829 #clock-cells = <1>;
0830 interrupt-controller;
0831 #interrupt-cells = <3>;
0832 interrupt-parent = <&gic>;
0833 };
0834
0835 tmu_cpu0: tmu@10060000 {
0836 compatible = "samsung,exynos5420-tmu";
0837 reg = <0x10060000 0x100>;
0838 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0839 clocks = <&clock CLK_TMU>;
0840 clock-names = "tmu_apbif";
0841 #thermal-sensor-cells = <0>;
0842 };
0843
0844 tmu_cpu1: tmu@10064000 {
0845 compatible = "samsung,exynos5420-tmu";
0846 reg = <0x10064000 0x100>;
0847 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
0848 clocks = <&clock CLK_TMU>;
0849 clock-names = "tmu_apbif";
0850 #thermal-sensor-cells = <0>;
0851 };
0852
0853 tmu_cpu2: tmu@10068000 {
0854 compatible = "samsung,exynos5420-tmu-ext-triminfo";
0855 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
0856 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0857 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
0858 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
0859 #thermal-sensor-cells = <0>;
0860 };
0861
0862 tmu_cpu3: tmu@1006c000 {
0863 compatible = "samsung,exynos5420-tmu-ext-triminfo";
0864 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
0865 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
0866 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
0867 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
0868 #thermal-sensor-cells = <0>;
0869 };
0870
0871 tmu_gpu: tmu@100a0000 {
0872 compatible = "samsung,exynos5420-tmu-ext-triminfo";
0873 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
0874 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
0875 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
0876 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
0877 #thermal-sensor-cells = <0>;
0878 };
0879
0880 sysmmu_g2dr: sysmmu@10a60000 {
0881 compatible = "samsung,exynos-sysmmu";
0882 reg = <0x10A60000 0x1000>;
0883 interrupt-parent = <&combiner>;
0884 interrupts = <24 5>;
0885 clock-names = "sysmmu", "master";
0886 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
0887 #iommu-cells = <0>;
0888 };
0889
0890 sysmmu_g2dw: sysmmu@10a70000 {
0891 compatible = "samsung,exynos-sysmmu";
0892 reg = <0x10A70000 0x1000>;
0893 interrupt-parent = <&combiner>;
0894 interrupts = <22 2>;
0895 clock-names = "sysmmu", "master";
0896 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
0897 #iommu-cells = <0>;
0898 };
0899
0900 sysmmu_tv: sysmmu@14650000 {
0901 compatible = "samsung,exynos-sysmmu";
0902 reg = <0x14650000 0x1000>;
0903 interrupt-parent = <&combiner>;
0904 interrupts = <7 4>;
0905 clock-names = "sysmmu", "master";
0906 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
0907 power-domains = <&disp_pd>;
0908 #iommu-cells = <0>;
0909 };
0910
0911 sysmmu_gscl0: sysmmu@13e80000 {
0912 compatible = "samsung,exynos-sysmmu";
0913 reg = <0x13E80000 0x1000>;
0914 interrupt-parent = <&combiner>;
0915 interrupts = <2 0>;
0916 clock-names = "sysmmu", "master";
0917 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
0918 power-domains = <&gsc_pd>;
0919 #iommu-cells = <0>;
0920 };
0921
0922 sysmmu_gscl1: sysmmu@13e90000 {
0923 compatible = "samsung,exynos-sysmmu";
0924 reg = <0x13E90000 0x1000>;
0925 interrupt-parent = <&combiner>;
0926 interrupts = <2 2>;
0927 clock-names = "sysmmu", "master";
0928 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
0929 power-domains = <&gsc_pd>;
0930 #iommu-cells = <0>;
0931 };
0932
0933 sysmmu_scaler0r: sysmmu@12880000 {
0934 compatible = "samsung,exynos-sysmmu";
0935 reg = <0x12880000 0x1000>;
0936 interrupt-parent = <&combiner>;
0937 interrupts = <22 4>;
0938 clock-names = "sysmmu", "master";
0939 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
0940 power-domains = <&msc_pd>;
0941 #iommu-cells = <0>;
0942 };
0943
0944 sysmmu_scaler1r: sysmmu@12890000 {
0945 compatible = "samsung,exynos-sysmmu";
0946 reg = <0x12890000 0x1000>;
0947 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
0948 clock-names = "sysmmu", "master";
0949 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
0950 power-domains = <&msc_pd>;
0951 #iommu-cells = <0>;
0952 };
0953
0954 sysmmu_scaler2r: sysmmu@128a0000 {
0955 compatible = "samsung,exynos-sysmmu";
0956 reg = <0x128A0000 0x1000>;
0957 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0958 clock-names = "sysmmu", "master";
0959 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
0960 power-domains = <&msc_pd>;
0961 #iommu-cells = <0>;
0962 };
0963
0964 sysmmu_scaler0w: sysmmu@128c0000 {
0965 compatible = "samsung,exynos-sysmmu";
0966 reg = <0x128C0000 0x1000>;
0967 interrupt-parent = <&combiner>;
0968 interrupts = <27 2>;
0969 clock-names = "sysmmu", "master";
0970 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
0971 power-domains = <&msc_pd>;
0972 #iommu-cells = <0>;
0973 };
0974
0975 sysmmu_scaler1w: sysmmu@128d0000 {
0976 compatible = "samsung,exynos-sysmmu";
0977 reg = <0x128D0000 0x1000>;
0978 interrupt-parent = <&combiner>;
0979 interrupts = <22 6>;
0980 clock-names = "sysmmu", "master";
0981 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
0982 power-domains = <&msc_pd>;
0983 #iommu-cells = <0>;
0984 };
0985
0986 sysmmu_scaler2w: sysmmu@128e0000 {
0987 compatible = "samsung,exynos-sysmmu";
0988 reg = <0x128E0000 0x1000>;
0989 interrupt-parent = <&combiner>;
0990 interrupts = <19 6>;
0991 clock-names = "sysmmu", "master";
0992 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
0993 power-domains = <&msc_pd>;
0994 #iommu-cells = <0>;
0995 };
0996
0997 sysmmu_rotator: sysmmu@11d40000 {
0998 compatible = "samsung,exynos-sysmmu";
0999 reg = <0x11D40000 0x1000>;
1000 interrupt-parent = <&combiner>;
1001 interrupts = <4 0>;
1002 clock-names = "sysmmu", "master";
1003 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1004 #iommu-cells = <0>;
1005 };
1006
1007 sysmmu_jpeg0: sysmmu@11f10000 {
1008 compatible = "samsung,exynos-sysmmu";
1009 reg = <0x11F10000 0x1000>;
1010 interrupt-parent = <&combiner>;
1011 interrupts = <4 2>;
1012 clock-names = "sysmmu", "master";
1013 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1014 #iommu-cells = <0>;
1015 };
1016
1017 sysmmu_jpeg1: sysmmu@11f20000 {
1018 compatible = "samsung,exynos-sysmmu";
1019 reg = <0x11F20000 0x1000>;
1020 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1021 clock-names = "sysmmu", "master";
1022 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1023 #iommu-cells = <0>;
1024 };
1025
1026 sysmmu_mfc_l: sysmmu@11200000 {
1027 compatible = "samsung,exynos-sysmmu";
1028 reg = <0x11200000 0x1000>;
1029 interrupt-parent = <&combiner>;
1030 interrupts = <6 2>;
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1033 power-domains = <&mfc_pd>;
1034 #iommu-cells = <0>;
1035 };
1036
1037 sysmmu_mfc_r: sysmmu@11210000 {
1038 compatible = "samsung,exynos-sysmmu";
1039 reg = <0x11210000 0x1000>;
1040 interrupt-parent = <&combiner>;
1041 interrupts = <8 5>;
1042 clock-names = "sysmmu", "master";
1043 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1044 power-domains = <&mfc_pd>;
1045 #iommu-cells = <0>;
1046 };
1047
1048 sysmmu_fimd1_0: sysmmu@14640000 {
1049 compatible = "samsung,exynos-sysmmu";
1050 reg = <0x14640000 0x1000>;
1051 interrupt-parent = <&combiner>;
1052 interrupts = <3 2>;
1053 clock-names = "sysmmu", "master";
1054 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1055 power-domains = <&disp_pd>;
1056 #iommu-cells = <0>;
1057 };
1058
1059 sysmmu_fimd1_1: sysmmu@14680000 {
1060 compatible = "samsung,exynos-sysmmu";
1061 reg = <0x14680000 0x1000>;
1062 interrupt-parent = <&combiner>;
1063 interrupts = <3 0>;
1064 clock-names = "sysmmu", "master";
1065 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1066 power-domains = <&disp_pd>;
1067 #iommu-cells = <0>;
1068 };
1069
1070 bus_wcore: bus-wcore {
1071 compatible = "samsung,exynos-bus";
1072 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1073 clock-names = "bus";
1074 status = "disabled";
1075 };
1076
1077 bus_noc: bus-noc {
1078 compatible = "samsung,exynos-bus";
1079 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1080 clock-names = "bus";
1081 status = "disabled";
1082 };
1083
1084 bus_fsys_apb: bus-fsys-apb {
1085 compatible = "samsung,exynos-bus";
1086 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1087 clock-names = "bus";
1088 status = "disabled";
1089 };
1090
1091 bus_fsys: bus-fsys {
1092 compatible = "samsung,exynos-bus";
1093 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1094 clock-names = "bus";
1095 status = "disabled";
1096 };
1097
1098 bus_fsys2: bus-fsys2 {
1099 compatible = "samsung,exynos-bus";
1100 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1101 clock-names = "bus";
1102 status = "disabled";
1103 };
1104
1105 bus_mfc: bus-mfc {
1106 compatible = "samsung,exynos-bus";
1107 clocks = <&clock CLK_DOUT_ACLK333>;
1108 clock-names = "bus";
1109 status = "disabled";
1110 };
1111
1112 bus_gen: bus-gen {
1113 compatible = "samsung,exynos-bus";
1114 clocks = <&clock CLK_DOUT_ACLK266>;
1115 clock-names = "bus";
1116 status = "disabled";
1117 };
1118
1119 bus_peri: bus-peri {
1120 compatible = "samsung,exynos-bus";
1121 clocks = <&clock CLK_DOUT_ACLK66>;
1122 clock-names = "bus";
1123 status = "disabled";
1124 };
1125
1126 bus_g2d: bus-g2d {
1127 compatible = "samsung,exynos-bus";
1128 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1129 clock-names = "bus";
1130 status = "disabled";
1131 };
1132
1133 bus_g2d_acp: bus-g2d-acp {
1134 compatible = "samsung,exynos-bus";
1135 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1136 clock-names = "bus";
1137 status = "disabled";
1138 };
1139
1140 bus_jpeg: bus-jpeg {
1141 compatible = "samsung,exynos-bus";
1142 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1143 clock-names = "bus";
1144 status = "disabled";
1145 };
1146
1147 bus_jpeg_apb: bus-jpeg-apb {
1148 compatible = "samsung,exynos-bus";
1149 clocks = <&clock CLK_DOUT_ACLK166>;
1150 clock-names = "bus";
1151 status = "disabled";
1152 };
1153
1154 bus_disp1_fimd: bus-disp1-fimd {
1155 compatible = "samsung,exynos-bus";
1156 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1157 clock-names = "bus";
1158 status = "disabled";
1159 };
1160
1161 bus_disp1: bus-disp1 {
1162 compatible = "samsung,exynos-bus";
1163 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1164 clock-names = "bus";
1165 status = "disabled";
1166 };
1167
1168 bus_gscl_scaler: bus-gscl-scaler {
1169 compatible = "samsung,exynos-bus";
1170 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1171 clock-names = "bus";
1172 status = "disabled";
1173 };
1174
1175 bus_mscl: bus-mscl {
1176 compatible = "samsung,exynos-bus";
1177 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1178 clock-names = "bus";
1179 status = "disabled";
1180 };
1181 };
1182
1183 thermal-zones {
1184 cpu0_thermal: cpu0-thermal {
1185 thermal-sensors = <&tmu_cpu0>;
1186 #include "exynos5420-trip-points.dtsi"
1187 };
1188 cpu1_thermal: cpu1-thermal {
1189 thermal-sensors = <&tmu_cpu1>;
1190 #include "exynos5420-trip-points.dtsi"
1191 };
1192 cpu2_thermal: cpu2-thermal {
1193 thermal-sensors = <&tmu_cpu2>;
1194 #include "exynos5420-trip-points.dtsi"
1195 };
1196 cpu3_thermal: cpu3-thermal {
1197 thermal-sensors = <&tmu_cpu3>;
1198 #include "exynos5420-trip-points.dtsi"
1199 };
1200 gpu_thermal: gpu-thermal {
1201 thermal-sensors = <&tmu_gpu>;
1202 #include "exynos5420-trip-points.dtsi"
1203 };
1204 };
1205 };
1206
1207 &adc {
1208 clocks = <&clock CLK_TSADC>;
1209 clock-names = "adc";
1210 samsung,syscon-phandle = <&pmu_system_controller>;
1211 };
1212
1213 &dp {
1214 clocks = <&clock CLK_DP1>;
1215 clock-names = "dp";
1216 phys = <&dp_phy>;
1217 phy-names = "dp";
1218 power-domains = <&disp_pd>;
1219 };
1220
1221 &fimd {
1222 compatible = "samsung,exynos5420-fimd";
1223 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1224 clock-names = "sclk_fimd", "fimd";
1225 power-domains = <&disp_pd>;
1226 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1227 iommu-names = "m0", "m1";
1228 };
1229
1230 &g2d {
1231 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1232 clocks = <&clock CLK_G2D>;
1233 clock-names = "fimg2d";
1234 status = "okay";
1235 };
1236
1237 &i2c_0 {
1238 clocks = <&clock CLK_I2C0>;
1239 clock-names = "i2c";
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&i2c0_bus>;
1242 };
1243
1244 &i2c_1 {
1245 clocks = <&clock CLK_I2C1>;
1246 clock-names = "i2c";
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&i2c1_bus>;
1249 };
1250
1251 &i2c_2 {
1252 clocks = <&clock CLK_I2C2>;
1253 clock-names = "i2c";
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&i2c2_bus>;
1256 };
1257
1258 &i2c_3 {
1259 clocks = <&clock CLK_I2C3>;
1260 clock-names = "i2c";
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&i2c3_bus>;
1263 };
1264
1265 &hsi2c_4 {
1266 clocks = <&clock CLK_USI0>;
1267 clock-names = "hsi2c";
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&i2c4_hs_bus>;
1270 };
1271
1272 &hsi2c_5 {
1273 clocks = <&clock CLK_USI1>;
1274 clock-names = "hsi2c";
1275 pinctrl-names = "default";
1276 pinctrl-0 = <&i2c5_hs_bus>;
1277 };
1278
1279 &hsi2c_6 {
1280 clocks = <&clock CLK_USI2>;
1281 clock-names = "hsi2c";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&i2c6_hs_bus>;
1284 };
1285
1286 &hsi2c_7 {
1287 clocks = <&clock CLK_USI3>;
1288 clock-names = "hsi2c";
1289 pinctrl-names = "default";
1290 pinctrl-0 = <&i2c7_hs_bus>;
1291 };
1292
1293 &mct {
1294 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1295 clock-names = "fin_pll", "mct";
1296 };
1297
1298 &prng {
1299 clocks = <&clock CLK_SSS>;
1300 clock-names = "secss";
1301 };
1302
1303 &pwm {
1304 clocks = <&clock CLK_PWM>;
1305 clock-names = "timers";
1306 };
1307
1308 &rtc {
1309 clocks = <&clock CLK_RTC>;
1310 clock-names = "rtc";
1311 interrupt-parent = <&pmu_system_controller>;
1312 status = "disabled";
1313 };
1314
1315 &serial_0 {
1316 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1317 clock-names = "uart", "clk_uart_baud0";
1318 dmas = <&pdma0 13>, <&pdma0 14>;
1319 dma-names = "rx", "tx";
1320 };
1321
1322 &serial_1 {
1323 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1324 clock-names = "uart", "clk_uart_baud0";
1325 dmas = <&pdma1 15>, <&pdma1 16>;
1326 dma-names = "rx", "tx";
1327 };
1328
1329 &serial_2 {
1330 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1331 clock-names = "uart", "clk_uart_baud0";
1332 dmas = <&pdma0 15>, <&pdma0 16>;
1333 dma-names = "rx", "tx";
1334 };
1335
1336 &serial_3 {
1337 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1338 clock-names = "uart", "clk_uart_baud0";
1339 dmas = <&pdma1 17>, <&pdma1 18>;
1340 dma-names = "rx", "tx";
1341 };
1342
1343 &sss {
1344 clocks = <&clock CLK_SSS>;
1345 clock-names = "secss";
1346 };
1347
1348 &trng {
1349 clocks = <&clock CLK_SSS>;
1350 clock-names = "secss";
1351 };
1352
1353 &usbdrd3_0 {
1354 clocks = <&clock CLK_USBD300>;
1355 clock-names = "usbdrd30";
1356 };
1357
1358 &usbdrd_phy0 {
1359 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1360 clock-names = "phy", "ref";
1361 samsung,pmu-syscon = <&pmu_system_controller>;
1362 };
1363
1364 &usbdrd3_1 {
1365 clocks = <&clock CLK_USBD301>;
1366 clock-names = "usbdrd30";
1367 };
1368
1369 &usbdrd_dwc3_1 {
1370 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1371 };
1372
1373 &usbdrd_phy1 {
1374 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1375 clock-names = "phy", "ref";
1376 samsung,pmu-syscon = <&pmu_system_controller>;
1377 };
1378
1379 &usbhost1 {
1380 clocks = <&clock CLK_USBH20>;
1381 clock-names = "usbhost";
1382 };
1383
1384 &usbhost2 {
1385 clocks = <&clock CLK_USBH20>;
1386 clock-names = "usbhost";
1387 };
1388
1389 &usb2_phy {
1390 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1391 clock-names = "phy", "ref";
1392 samsung,sysreg-phandle = <&sysreg_system_controller>;
1393 samsung,pmureg-phandle = <&pmu_system_controller>;
1394 };
1395
1396 &watchdog {
1397 clocks = <&clock CLK_WDT>;
1398 clock-names = "watchdog";
1399 samsung,syscon-phandle = <&pmu_system_controller>;
1400 };
1401
1402 #include "exynos5420-pinctrl.dtsi"
1403 #include "exynos-syscon-restart.dtsi"
