0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos5420 SoC cpu device tree source
0004 *
0005 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * This file provides desired ordering for Exynos5420 and Exynos5800
0009 * boards: CPU[0123] being the A15.
0010 *
0011 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
0012 * but particular boards choose different booting order.
0013 *
0014 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
0015 * booting cluster (big or LITTLE) is chosen by IROM code by reading
0016 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
0017 * from the LITTLE: Cortex-A7.
0018 */
0019
0020 / {
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 cpu-map {
0026 cluster0 {
0027 core0 {
0028 cpu = <&cpu0>;
0029 };
0030 core1 {
0031 cpu = <&cpu1>;
0032 };
0033 core2 {
0034 cpu = <&cpu2>;
0035 };
0036 core3 {
0037 cpu = <&cpu3>;
0038 };
0039 };
0040
0041 cluster1 {
0042 core0 {
0043 cpu = <&cpu4>;
0044 };
0045 core1 {
0046 cpu = <&cpu5>;
0047 };
0048 core2 {
0049 cpu = <&cpu6>;
0050 };
0051 core3 {
0052 cpu = <&cpu7>;
0053 };
0054 };
0055 };
0056
0057 cpu0: cpu@0 {
0058 device_type = "cpu";
0059 compatible = "arm,cortex-a15";
0060 reg = <0x0>;
0061 clocks = <&clock CLK_ARM_CLK>;
0062 clock-frequency = <1800000000>;
0063 cci-control-port = <&cci_control1>;
0064 operating-points-v2 = <&cluster_a15_opp_table>;
0065 #cooling-cells = <2>; /* min followed by max */
0066 capacity-dmips-mhz = <1024>;
0067 };
0068
0069 cpu1: cpu@1 {
0070 device_type = "cpu";
0071 compatible = "arm,cortex-a15";
0072 reg = <0x1>;
0073 clocks = <&clock CLK_ARM_CLK>;
0074 clock-frequency = <1800000000>;
0075 cci-control-port = <&cci_control1>;
0076 operating-points-v2 = <&cluster_a15_opp_table>;
0077 #cooling-cells = <2>; /* min followed by max */
0078 capacity-dmips-mhz = <1024>;
0079 };
0080
0081 cpu2: cpu@2 {
0082 device_type = "cpu";
0083 compatible = "arm,cortex-a15";
0084 reg = <0x2>;
0085 clocks = <&clock CLK_ARM_CLK>;
0086 clock-frequency = <1800000000>;
0087 cci-control-port = <&cci_control1>;
0088 operating-points-v2 = <&cluster_a15_opp_table>;
0089 #cooling-cells = <2>; /* min followed by max */
0090 capacity-dmips-mhz = <1024>;
0091 };
0092
0093 cpu3: cpu@3 {
0094 device_type = "cpu";
0095 compatible = "arm,cortex-a15";
0096 reg = <0x3>;
0097 clocks = <&clock CLK_ARM_CLK>;
0098 clock-frequency = <1800000000>;
0099 cci-control-port = <&cci_control1>;
0100 operating-points-v2 = <&cluster_a15_opp_table>;
0101 #cooling-cells = <2>; /* min followed by max */
0102 capacity-dmips-mhz = <1024>;
0103 };
0104
0105 cpu4: cpu@100 {
0106 device_type = "cpu";
0107 compatible = "arm,cortex-a7";
0108 reg = <0x100>;
0109 clocks = <&clock CLK_KFC_CLK>;
0110 clock-frequency = <1000000000>;
0111 cci-control-port = <&cci_control0>;
0112 operating-points-v2 = <&cluster_a7_opp_table>;
0113 #cooling-cells = <2>; /* min followed by max */
0114 capacity-dmips-mhz = <539>;
0115 };
0116
0117 cpu5: cpu@101 {
0118 device_type = "cpu";
0119 compatible = "arm,cortex-a7";
0120 reg = <0x101>;
0121 clocks = <&clock CLK_KFC_CLK>;
0122 clock-frequency = <1000000000>;
0123 cci-control-port = <&cci_control0>;
0124 operating-points-v2 = <&cluster_a7_opp_table>;
0125 #cooling-cells = <2>; /* min followed by max */
0126 capacity-dmips-mhz = <539>;
0127 };
0128
0129 cpu6: cpu@102 {
0130 device_type = "cpu";
0131 compatible = "arm,cortex-a7";
0132 reg = <0x102>;
0133 clocks = <&clock CLK_KFC_CLK>;
0134 clock-frequency = <1000000000>;
0135 cci-control-port = <&cci_control0>;
0136 operating-points-v2 = <&cluster_a7_opp_table>;
0137 #cooling-cells = <2>; /* min followed by max */
0138 capacity-dmips-mhz = <539>;
0139 };
0140
0141 cpu7: cpu@103 {
0142 device_type = "cpu";
0143 compatible = "arm,cortex-a7";
0144 reg = <0x103>;
0145 clocks = <&clock CLK_KFC_CLK>;
0146 clock-frequency = <1000000000>;
0147 cci-control-port = <&cci_control0>;
0148 operating-points-v2 = <&cluster_a7_opp_table>;
0149 #cooling-cells = <2>; /* min followed by max */
0150 capacity-dmips-mhz = <539>;
0151 };
0152 };
0153 };
0154
0155 &arm_a7_pmu {
0156 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
0157 status = "okay";
0158 };
0159
0160 &arm_a15_pmu {
0161 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0162 status = "okay";
0163 };
