0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos5410 SoC device tree source
0004 *
0005 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * Samsung Exynos5410 SoC device nodes are listed in this file.
0009 * Exynos5410 based board files can include this file and provide
0010 * values for board specfic bindings.
0011 */
0012
0013 #include "exynos54xx.dtsi"
0014 #include <dt-bindings/clock/exynos5410.h>
0015 #include <dt-bindings/clock/exynos-audss-clk.h>
0016 #include <dt-bindings/interrupt-controller/arm-gic.h>
0017
0018 / {
0019 compatible = "samsung,exynos5410", "samsung,exynos5";
0020 interrupt-parent = <&gic>;
0021
0022 aliases {
0023 pinctrl0 = &pinctrl_0;
0024 pinctrl1 = &pinctrl_1;
0025 pinctrl2 = &pinctrl_2;
0026 pinctrl3 = &pinctrl_3;
0027 };
0028
0029 cpus {
0030 #address-cells = <1>;
0031 #size-cells = <0>;
0032
0033 cpu0: cpu@0 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a15";
0036 reg = <0x0>;
0037 clock-frequency = <1600000000>;
0038 };
0039
0040 cpu1: cpu@1 {
0041 device_type = "cpu";
0042 compatible = "arm,cortex-a15";
0043 reg = <0x1>;
0044 clock-frequency = <1600000000>;
0045 };
0046
0047 cpu2: cpu@2 {
0048 device_type = "cpu";
0049 compatible = "arm,cortex-a15";
0050 reg = <0x2>;
0051 clock-frequency = <1600000000>;
0052 };
0053
0054 cpu3: cpu@3 {
0055 device_type = "cpu";
0056 compatible = "arm,cortex-a15";
0057 reg = <0x3>;
0058 clock-frequency = <1600000000>;
0059 };
0060 };
0061
0062 soc: soc {
0063 compatible = "simple-bus";
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066 ranges;
0067
0068 pmu_system_controller: system-controller@10040000 {
0069 compatible = "samsung,exynos5410-pmu", "syscon";
0070 reg = <0x10040000 0x5000>;
0071 clock-names = "clkout16";
0072 clocks = <&fin_pll>;
0073 #clock-cells = <1>;
0074 };
0075
0076 clock: clock-controller@10010000 {
0077 compatible = "samsung,exynos5410-clock";
0078 reg = <0x10010000 0x30000>;
0079 #clock-cells = <1>;
0080 };
0081
0082 clock_audss: audss-clock-controller@3810000 {
0083 compatible = "samsung,exynos5410-audss-clock";
0084 reg = <0x03810000 0x0C>;
0085 #clock-cells = <1>;
0086 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
0087 clock-names = "pll_ref", "pll_in";
0088 };
0089
0090 tmu_cpu0: tmu@10060000 {
0091 compatible = "samsung,exynos5420-tmu";
0092 reg = <0x10060000 0x100>;
0093 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0094 clocks = <&clock CLK_TMU>;
0095 clock-names = "tmu_apbif";
0096 #thermal-sensor-cells = <0>;
0097 };
0098
0099 tmu_cpu1: tmu@10064000 {
0100 compatible = "samsung,exynos5420-tmu";
0101 reg = <0x10064000 0x100>;
0102 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
0103 clocks = <&clock CLK_TMU>;
0104 clock-names = "tmu_apbif";
0105 #thermal-sensor-cells = <0>;
0106 };
0107
0108 tmu_cpu2: tmu@10068000 {
0109 compatible = "samsung,exynos5420-tmu";
0110 reg = <0x10068000 0x100>;
0111 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0112 clocks = <&clock CLK_TMU>;
0113 clock-names = "tmu_apbif";
0114 #thermal-sensor-cells = <0>;
0115 };
0116
0117 tmu_cpu3: tmu@1006c000 {
0118 compatible = "samsung,exynos5420-tmu";
0119 reg = <0x1006c000 0x100>;
0120 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
0121 clocks = <&clock CLK_TMU>;
0122 clock-names = "tmu_apbif";
0123 #thermal-sensor-cells = <0>;
0124 };
0125
0126 mmc_0: mmc@12200000 {
0127 compatible = "samsung,exynos5250-dw-mshc";
0128 reg = <0x12200000 0x1000>;
0129 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0130 #address-cells = <1>;
0131 #size-cells = <0>;
0132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
0133 clock-names = "biu", "ciu";
0134 fifo-depth = <0x80>;
0135 status = "disabled";
0136 };
0137
0138 mmc_1: mmc@12210000 {
0139 compatible = "samsung,exynos5250-dw-mshc";
0140 reg = <0x12210000 0x1000>;
0141 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
0145 clock-names = "biu", "ciu";
0146 fifo-depth = <0x80>;
0147 status = "disabled";
0148 };
0149
0150 mmc_2: mmc@12220000 {
0151 compatible = "samsung,exynos5250-dw-mshc";
0152 reg = <0x12220000 0x1000>;
0153 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
0157 clock-names = "biu", "ciu";
0158 fifo-depth = <0x80>;
0159 status = "disabled";
0160 };
0161
0162 pinctrl_0: pinctrl@13400000 {
0163 compatible = "samsung,exynos5410-pinctrl";
0164 reg = <0x13400000 0x1000>;
0165 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0166
0167 wakeup-interrupt-controller {
0168 compatible = "samsung,exynos4210-wakeup-eint";
0169 interrupt-parent = <&gic>;
0170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0171 };
0172 };
0173
0174 pinctrl_1: pinctrl@14000000 {
0175 compatible = "samsung,exynos5410-pinctrl";
0176 reg = <0x14000000 0x1000>;
0177 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0178 };
0179
0180 pinctrl_2: pinctrl@10d10000 {
0181 compatible = "samsung,exynos5410-pinctrl";
0182 reg = <0x10d10000 0x1000>;
0183 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0184 };
0185
0186 pinctrl_3: pinctrl@3860000 {
0187 compatible = "samsung,exynos5410-pinctrl";
0188 reg = <0x03860000 0x1000>;
0189 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0190 };
0191
0192 pdma0: dma-controller@121a0000 {
0193 compatible = "arm,pl330", "arm,primecell";
0194 reg = <0x121a0000 0x1000>;
0195 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0196 clocks = <&clock CLK_PDMA0>;
0197 clock-names = "apb_pclk";
0198 #dma-cells = <1>;
0199 };
0200
0201 pdma1: dma-controller@121b0000 {
0202 compatible = "arm,pl330", "arm,primecell";
0203 reg = <0x121b0000 0x1000>;
0204 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0205 clocks = <&clock CLK_PDMA1>;
0206 clock-names = "apb_pclk";
0207 #dma-cells = <1>;
0208 };
0209
0210 audi2s0: i2s@3830000 {
0211 compatible = "samsung,exynos5420-i2s";
0212 reg = <0x03830000 0x100>;
0213 dmas = <&pdma0 10>,
0214 <&pdma0 9>,
0215 <&pdma0 8>;
0216 dma-names = "tx", "rx", "tx-sec";
0217 clocks = <&clock_audss EXYNOS_I2S_BUS>,
0218 <&clock_audss EXYNOS_I2S_BUS>,
0219 <&clock_audss EXYNOS_SCLK_I2S>;
0220 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
0221 #clock-cells = <1>;
0222 clock-output-names = "i2s_cdclk0";
0223 #sound-dai-cells = <1>;
0224 samsung,idma-addr = <0x03000000>;
0225 pinctrl-names = "default";
0226 pinctrl-0 = <&audi2s0_bus>;
0227 status = "disabled";
0228 };
0229 };
0230
0231 thermal-zones {
0232 cpu0_thermal: cpu0-thermal {
0233 thermal-sensors = <&tmu_cpu0>;
0234 #include "exynos5420-trip-points.dtsi"
0235 };
0236 cpu1_thermal: cpu1-thermal {
0237 thermal-sensors = <&tmu_cpu1>;
0238 #include "exynos5420-trip-points.dtsi"
0239 };
0240 cpu2_thermal: cpu2-thermal {
0241 thermal-sensors = <&tmu_cpu2>;
0242 #include "exynos5420-trip-points.dtsi"
0243 };
0244 cpu3_thermal: cpu3-thermal {
0245 thermal-sensors = <&tmu_cpu3>;
0246 #include "exynos5420-trip-points.dtsi"
0247 };
0248 };
0249 };
0250
0251 &adc {
0252 clocks = <&clock CLK_TSADC>;
0253 clock-names = "adc";
0254 samsung,syscon-phandle = <&pmu_system_controller>;
0255 };
0256
0257 &arm_a15_pmu {
0258 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0259 status = "okay";
0260 };
0261
0262 &i2c_0 {
0263 clocks = <&clock CLK_I2C0>;
0264 clock-names = "i2c";
0265 pinctrl-names = "default";
0266 pinctrl-0 = <&i2c0_bus>;
0267 };
0268
0269 &i2c_1 {
0270 clocks = <&clock CLK_I2C1>;
0271 clock-names = "i2c";
0272 pinctrl-names = "default";
0273 pinctrl-0 = <&i2c1_bus>;
0274 };
0275
0276 &i2c_2 {
0277 clocks = <&clock CLK_I2C2>;
0278 clock-names = "i2c";
0279 pinctrl-names = "default";
0280 pinctrl-0 = <&i2c2_bus>;
0281 };
0282
0283 &i2c_3 {
0284 clocks = <&clock CLK_I2C3>;
0285 clock-names = "i2c";
0286 pinctrl-names = "default";
0287 pinctrl-0 = <&i2c3_bus>;
0288 };
0289
0290 &hsi2c_4 {
0291 clocks = <&clock CLK_USI0>;
0292 clock-names = "hsi2c";
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&i2c4_hs_bus>;
0295 };
0296
0297 &hsi2c_5 {
0298 clocks = <&clock CLK_USI1>;
0299 clock-names = "hsi2c";
0300 pinctrl-names = "default";
0301 pinctrl-0 = <&i2c5_hs_bus>;
0302 };
0303
0304 &hsi2c_6 {
0305 clocks = <&clock CLK_USI2>;
0306 clock-names = "hsi2c";
0307 pinctrl-names = "default";
0308 pinctrl-0 = <&i2c6_hs_bus>;
0309 };
0310
0311 &hsi2c_7 {
0312 clocks = <&clock CLK_USI3>;
0313 clock-names = "hsi2c";
0314 pinctrl-names = "default";
0315 pinctrl-0 = <&i2c7_hs_bus>;
0316 };
0317
0318 &mct {
0319 clocks = <&fin_pll>, <&clock CLK_MCT>;
0320 clock-names = "fin_pll", "mct";
0321 };
0322
0323 &prng {
0324 clocks = <&clock CLK_SSS>;
0325 clock-names = "secss";
0326 };
0327
0328 &pwm {
0329 clocks = <&clock CLK_PWM>;
0330 clock-names = "timers";
0331 };
0332
0333 &rtc {
0334 clocks = <&clock CLK_RTC>;
0335 clock-names = "rtc";
0336 status = "disabled";
0337 };
0338
0339 &serial_0 {
0340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
0341 clock-names = "uart", "clk_uart_baud0";
0342 dmas = <&pdma0 13>, <&pdma0 14>;
0343 dma-names = "rx", "tx";
0344 };
0345
0346 &serial_1 {
0347 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
0348 clock-names = "uart", "clk_uart_baud0";
0349 dmas = <&pdma1 15>, <&pdma1 16>;
0350 dma-names = "rx", "tx";
0351 };
0352
0353 &serial_2 {
0354 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
0355 clock-names = "uart", "clk_uart_baud0";
0356 dmas = <&pdma0 15>, <&pdma0 16>;
0357 dma-names = "rx", "tx";
0358 };
0359
0360 &serial_3 {
0361 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
0362 clock-names = "uart", "clk_uart_baud0";
0363 dmas = <&pdma1 17>, <&pdma1 18>;
0364 dma-names = "rx", "tx";
0365 };
0366
0367 &sss {
0368 clocks = <&clock CLK_SSS>;
0369 clock-names = "secss";
0370 };
0371
0372 &sromc {
0373 #address-cells = <2>;
0374 #size-cells = <1>;
0375 ranges = <0 0 0x04000000 0x20000
0376 1 0 0x05000000 0x20000
0377 2 0 0x06000000 0x20000
0378 3 0 0x07000000 0x20000>;
0379 };
0380
0381 &trng {
0382 clocks = <&clock CLK_SSS>;
0383 clock-names = "secss";
0384 };
0385
0386 &usbdrd3_0 {
0387 clocks = <&clock CLK_USBD300>;
0388 clock-names = "usbdrd30";
0389 pinctrl-names = "default";
0390 pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>;
0391 };
0392
0393 &usbdrd_phy0 {
0394 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
0395 clock-names = "phy", "ref";
0396 samsung,pmu-syscon = <&pmu_system_controller>;
0397 };
0398
0399 &usbdrd3_1 {
0400 clocks = <&clock CLK_USBD301>;
0401 clock-names = "usbdrd30";
0402 pinctrl-names = "default";
0403 pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>;
0404 };
0405
0406 &usbdrd_dwc3_1 {
0407 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0408 };
0409
0410 &usbdrd_phy1 {
0411 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
0412 clock-names = "phy", "ref";
0413 samsung,pmu-syscon = <&pmu_system_controller>;
0414 };
0415
0416 &usbhost1 {
0417 clocks = <&clock CLK_USBH20>;
0418 clock-names = "usbhost";
0419 };
0420
0421 &usbhost2 {
0422 clocks = <&clock CLK_USBH20>;
0423 clock-names = "usbhost";
0424 };
0425
0426 &usb2_phy {
0427 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
0428 clock-names = "phy", "ref";
0429 samsung,sysreg-phandle = <&sysreg_system_controller>;
0430 samsung,pmureg-phandle = <&pmu_system_controller>;
0431 };
0432
0433 &watchdog {
0434 clocks = <&clock CLK_WDT>;
0435 clock-names = "watchdog";
0436 samsung,syscon-phandle = <&pmu_system_controller>;
0437 };
0438
0439 #include "exynos5410-pinctrl.dtsi"
0440 #include "exynos-syscon-restart.dtsi"
