0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos5260 SoC device tree source
0004 *
0005 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 */
0008
0009 #include <dt-bindings/clock/exynos5260-clk.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012
0013 / {
0014 compatible = "samsung,exynos5260", "samsung,exynos5";
0015 interrupt-parent = <&gic>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018
0019 aliases {
0020 i2c0 = &hsi2c_0;
0021 i2c1 = &hsi2c_1;
0022 i2c2 = &hsi2c_2;
0023 i2c3 = &hsi2c_3;
0024 pinctrl0 = &pinctrl_0;
0025 pinctrl1 = &pinctrl_1;
0026 pinctrl2 = &pinctrl_2;
0027 serial0 = &uart0;
0028 serial1 = &uart1;
0029 serial2 = &uart2;
0030 serial3 = &uart3;
0031 };
0032
0033 cpus {
0034 #address-cells = <1>;
0035 #size-cells = <0>;
0036
0037 cpu-map {
0038 cluster0 {
0039 core0 {
0040 cpu = <&cpu0>;
0041 };
0042 core1 {
0043 cpu = <&cpu1>;
0044 };
0045 };
0046
0047 cluster1 {
0048 core0 {
0049 cpu = <&cpu2>;
0050 };
0051 core1 {
0052 cpu = <&cpu3>;
0053 };
0054 core2 {
0055 cpu = <&cpu4>;
0056 };
0057 core3 {
0058 cpu = <&cpu5>;
0059 };
0060 };
0061 };
0062
0063 cpu0: cpu@0 {
0064 device_type = "cpu";
0065 compatible = "arm,cortex-a15";
0066 reg = <0x0>;
0067 cci-control-port = <&cci_control1>;
0068 };
0069
0070 cpu1: cpu@1 {
0071 device_type = "cpu";
0072 compatible = "arm,cortex-a15";
0073 reg = <0x1>;
0074 cci-control-port = <&cci_control1>;
0075 };
0076
0077 cpu2: cpu@100 {
0078 device_type = "cpu";
0079 compatible = "arm,cortex-a7";
0080 reg = <0x100>;
0081 cci-control-port = <&cci_control0>;
0082 };
0083
0084 cpu3: cpu@101 {
0085 device_type = "cpu";
0086 compatible = "arm,cortex-a7";
0087 reg = <0x101>;
0088 cci-control-port = <&cci_control0>;
0089 };
0090
0091 cpu4: cpu@102 {
0092 device_type = "cpu";
0093 compatible = "arm,cortex-a7";
0094 reg = <0x102>;
0095 cci-control-port = <&cci_control0>;
0096 };
0097
0098 cpu5: cpu@103 {
0099 device_type = "cpu";
0100 compatible = "arm,cortex-a7";
0101 reg = <0x103>;
0102 cci-control-port = <&cci_control0>;
0103 };
0104 };
0105
0106 soc: soc {
0107 compatible = "simple-bus";
0108 #address-cells = <1>;
0109 #size-cells = <1>;
0110 ranges;
0111
0112 clock_top: clock-controller@10010000 {
0113 compatible = "samsung,exynos5260-clock-top";
0114 reg = <0x10010000 0x10000>;
0115 #clock-cells = <1>;
0116 clocks = <&fin_pll>,
0117 <&clock_mif MIF_DOUT_MEM_PLL>,
0118 <&clock_mif MIF_DOUT_BUS_PLL>,
0119 <&clock_mif MIF_DOUT_MEDIA_PLL>;
0120 clock-names = "fin_pll",
0121 "dout_mem_pll",
0122 "dout_bus_pll",
0123 "dout_media_pll";
0124 };
0125
0126 clock_peri: clock-controller@10200000 {
0127 compatible = "samsung,exynos5260-clock-peri";
0128 reg = <0x10200000 0x10000>;
0129 #clock-cells = <1>;
0130 clocks = <&fin_pll>,
0131 <&ioclk_pcm>,
0132 <&ioclk_i2s>,
0133 <&ioclk_spdif>,
0134 <&fin_pll>,
0135 <&clock_top TOP_DOUT_ACLK_PERI_66>,
0136 <&clock_top TOP_DOUT_SCLK_PERI_UART0>,
0137 <&clock_top TOP_DOUT_SCLK_PERI_UART1>,
0138 <&clock_top TOP_DOUT_SCLK_PERI_UART2>,
0139 <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>,
0140 <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>,
0141 <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>,
0142 <&clock_top TOP_DOUT_ACLK_PERI_AUD>;
0143 clock-names = "fin_pll",
0144 "ioclk_pcm_extclk",
0145 "ioclk_i2s_cdclk",
0146 "ioclk_spdif_extclk",
0147 "phyclk_hdmi_phy_ref_cko",
0148 "dout_aclk_peri_66",
0149 "dout_sclk_peri_uart0",
0150 "dout_sclk_peri_uart1",
0151 "dout_sclk_peri_uart2",
0152 "dout_sclk_peri_spi0_b",
0153 "dout_sclk_peri_spi1_b",
0154 "dout_sclk_peri_spi2_b",
0155 "dout_aclk_peri_aud";
0156 };
0157
0158 clock_egl: clock-controller@10600000 {
0159 compatible = "samsung,exynos5260-clock-egl";
0160 reg = <0x10600000 0x10000>;
0161 #clock-cells = <1>;
0162 clocks = <&fin_pll>,
0163 <&clock_mif MIF_DOUT_BUS_PLL>;
0164 clock-names = "fin_pll",
0165 "dout_bus_pll";
0166 };
0167
0168 clock_kfc: clock-controller@10700000 {
0169 compatible = "samsung,exynos5260-clock-kfc";
0170 reg = <0x10700000 0x10000>;
0171 #clock-cells = <1>;
0172 clocks = <&fin_pll>,
0173 <&clock_mif MIF_DOUT_MEDIA_PLL>;
0174 clock-names = "fin_pll",
0175 "dout_media_pll";
0176 };
0177
0178 clock_g2d: clock-controller@10a00000 {
0179 compatible = "samsung,exynos5260-clock-g2d";
0180 reg = <0x10A00000 0x10000>;
0181 #clock-cells = <1>;
0182 clocks = <&fin_pll>,
0183 <&clock_top TOP_DOUT_ACLK_G2D_333>;
0184 clock-names = "fin_pll",
0185 "dout_aclk_g2d_333";
0186 };
0187
0188 clock_mif: clock-controller@10ce0000 {
0189 compatible = "samsung,exynos5260-clock-mif";
0190 reg = <0x10CE0000 0x10000>;
0191 #clock-cells = <1>;
0192 clocks = <&fin_pll>;
0193 clock-names = "fin_pll";
0194 };
0195
0196 clock_mfc: clock-controller@11090000 {
0197 compatible = "samsung,exynos5260-clock-mfc";
0198 reg = <0x11090000 0x10000>;
0199 #clock-cells = <1>;
0200 clocks = <&fin_pll>,
0201 <&clock_top TOP_DOUT_ACLK_MFC_333>;
0202 clock-names = "fin_pll",
0203 "dout_aclk_mfc_333";
0204 };
0205
0206 clock_g3d: clock-controller@11830000 {
0207 compatible = "samsung,exynos5260-clock-g3d";
0208 reg = <0x11830000 0x10000>;
0209 #clock-cells = <1>;
0210 clocks = <&fin_pll>;
0211 clock-names = "fin_pll";
0212 };
0213
0214 clock_fsys: clock-controller@122e0000 {
0215 compatible = "samsung,exynos5260-clock-fsys";
0216 reg = <0x122E0000 0x10000>;
0217 #clock-cells = <1>;
0218 clocks = <&fin_pll>,
0219 <&fin_pll>,
0220 <&fin_pll>,
0221 <&fin_pll>,
0222 <&fin_pll>,
0223 <&fin_pll>,
0224 <&clock_top TOP_DOUT_ACLK_FSYS_200>;
0225 clock-names = "fin_pll",
0226 "phyclk_usbhost20_phy_phyclock",
0227 "phyclk_usbhost20_phy_freeclk",
0228 "phyclk_usbhost20_phy_clk48mohci",
0229 "phyclk_usbdrd30_udrd30_pipe_pclk",
0230 "phyclk_usbdrd30_udrd30_phyclock",
0231 "dout_aclk_fsys_200";
0232 };
0233
0234 clock_aud: clock-controller@128c0000 {
0235 compatible = "samsung,exynos5260-clock-aud";
0236 reg = <0x128C0000 0x10000>;
0237 #clock-cells = <1>;
0238 clocks = <&fin_pll>,
0239 <&clock_top TOP_FOUT_AUD_PLL>,
0240 <&ioclk_i2s>,
0241 <&ioclk_pcm>;
0242 clock-names = "fin_pll",
0243 "fout_aud_pll",
0244 "ioclk_i2s_cdclk",
0245 "ioclk_pcm_extclk";
0246 };
0247
0248 clock_isp: clock-controller@133c0000 {
0249 compatible = "samsung,exynos5260-clock-isp";
0250 reg = <0x133C0000 0x10000>;
0251 #clock-cells = <1>;
0252 clocks = <&fin_pll>,
0253 <&clock_top TOP_DOUT_ACLK_ISP1_266>,
0254 <&clock_top TOP_DOUT_ACLK_ISP1_400>,
0255 <&clock_top TOP_MOUT_ACLK_ISP1_266>;
0256 clock-names = "fin_pll",
0257 "dout_aclk_isp1_266",
0258 "dout_aclk_isp1_400",
0259 "mout_aclk_isp1_266";
0260 };
0261
0262 clock_gscl: clock-controller@13f00000 {
0263 compatible = "samsung,exynos5260-clock-gscl";
0264 reg = <0x13F00000 0x10000>;
0265 #clock-cells = <1>;
0266 clocks = <&fin_pll>,
0267 <&clock_top TOP_DOUT_ACLK_GSCL_400>,
0268 <&clock_top TOP_DOUT_ACLK_GSCL_333>;
0269 clock-names = "fin_pll",
0270 "dout_aclk_gscl_400",
0271 "dout_aclk_gscl_333";
0272 };
0273
0274 clock_disp: clock-controller@14550000 {
0275 compatible = "samsung,exynos5260-clock-disp";
0276 reg = <0x14550000 0x10000>;
0277 #clock-cells = <1>;
0278 clocks = <&fin_pll>,
0279 <&fin_pll>,
0280 <&fin_pll>,
0281 <&fin_pll>,
0282 <&fin_pll>,
0283 <&fin_pll>,
0284 <&fin_pll>,
0285 <&fin_pll>,
0286 <&fin_pll>,
0287 <&fin_pll>,
0288 <&fin_pll>,
0289 <&fin_pll>,
0290 <&fin_pll>,
0291 <&fin_pll>,
0292 <&ioclk_spdif>,
0293 <&clock_top TOP_DOUT_ACLK_PERI_AUD>,
0294 <&clock_top TOP_DOUT_ACLK_DISP_222>,
0295 <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>,
0296 <&clock_top TOP_DOUT_ACLK_DISP_333>;
0297 clock-names = "fin_pll",
0298 "phyclk_dptx_phy_ch3_txd_clk",
0299 "phyclk_dptx_phy_ch2_txd_clk",
0300 "phyclk_dptx_phy_ch1_txd_clk",
0301 "phyclk_dptx_phy_ch0_txd_clk",
0302 "phyclk_hdmi_phy_tmds_clko",
0303 "phyclk_hdmi_phy_ref_clko",
0304 "phyclk_hdmi_phy_pixel_clko",
0305 "phyclk_hdmi_link_o_tmds_clkhi",
0306 "phyclk_mipi_dphy_4l_m_txbyte_clkhs",
0307 "phyclk_dptx_phy_o_ref_clk_24m",
0308 "phyclk_dptx_phy_clk_div2",
0309 "phyclk_mipi_dphy_4l_m_rxclkesc0",
0310 "phyclk_hdmi_phy_ref_cko",
0311 "ioclk_spdif_extclk",
0312 "dout_aclk_peri_aud",
0313 "dout_aclk_disp_222",
0314 "dout_sclk_disp_pixel",
0315 "dout_aclk_disp_333";
0316 };
0317
0318 gic: interrupt-controller@10481000 {
0319 compatible = "arm,gic-400", "arm,cortex-a15-gic";
0320 #interrupt-cells = <3>;
0321 interrupt-controller;
0322 reg = <0x10481000 0x1000>,
0323 <0x10482000 0x2000>,
0324 <0x10484000 0x2000>,
0325 <0x10486000 0x2000>;
0326 interrupts = <GIC_PPI 9
0327 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0328 };
0329
0330 chipid: chipid@10000000 {
0331 compatible = "samsung,exynos4210-chipid";
0332 reg = <0x10000000 0x100>;
0333 };
0334
0335 mct: timer@100b0000 {
0336 compatible = "samsung,exynos5260-mct",
0337 "samsung,exynos4210-mct";
0338 reg = <0x100B0000 0x1000>;
0339 clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
0340 clock-names = "fin_pll", "mct";
0341 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0342 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0343 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0344 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0345 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0347 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0348 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0349 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0350 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0351 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0352 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
0353 };
0354
0355 cci: cci@10f00000 {
0356 compatible = "arm,cci-400";
0357 #address-cells = <1>;
0358 #size-cells = <1>;
0359 reg = <0x10F00000 0x1000>;
0360 ranges = <0x0 0x10F00000 0x6000>;
0361
0362 cci_control0: slave-if@4000 {
0363 compatible = "arm,cci-400-ctrl-if";
0364 interface-type = "ace";
0365 reg = <0x4000 0x1000>;
0366 };
0367
0368 cci_control1: slave-if@5000 {
0369 compatible = "arm,cci-400-ctrl-if";
0370 interface-type = "ace";
0371 reg = <0x5000 0x1000>;
0372 };
0373 };
0374
0375 pinctrl_0: pinctrl@11600000 {
0376 compatible = "samsung,exynos5260-pinctrl";
0377 reg = <0x11600000 0x1000>;
0378 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0379
0380 wakeup-interrupt-controller {
0381 compatible = "samsung,exynos4210-wakeup-eint";
0382 interrupt-parent = <&gic>;
0383 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0384 };
0385 };
0386
0387 pinctrl_1: pinctrl@12290000 {
0388 compatible = "samsung,exynos5260-pinctrl";
0389 reg = <0x12290000 0x1000>;
0390 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0391 };
0392
0393 pinctrl_2: pinctrl@128b0000 {
0394 compatible = "samsung,exynos5260-pinctrl";
0395 reg = <0x128B0000 0x1000>;
0396 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
0397 };
0398
0399 pmu_system_controller: system-controller@10d50000 {
0400 compatible = "samsung,exynos5260-pmu", "syscon";
0401 reg = <0x10D50000 0x10000>;
0402 };
0403
0404 uart0: serial@12c00000 {
0405 compatible = "samsung,exynos4210-uart";
0406 reg = <0x12C00000 0x100>;
0407 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0408 clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
0409 clock-names = "uart", "clk_uart_baud0";
0410 status = "disabled";
0411 };
0412
0413 uart1: serial@12c10000 {
0414 compatible = "samsung,exynos4210-uart";
0415 reg = <0x12C10000 0x100>;
0416 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
0417 clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
0418 clock-names = "uart", "clk_uart_baud0";
0419 status = "disabled";
0420 };
0421
0422 uart2: serial@12c20000 {
0423 compatible = "samsung,exynos4210-uart";
0424 reg = <0x12C20000 0x100>;
0425 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0426 clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
0427 clock-names = "uart", "clk_uart_baud0";
0428 status = "disabled";
0429 };
0430
0431 uart3: serial@12860000 {
0432 compatible = "samsung,exynos4210-uart";
0433 reg = <0x12860000 0x100>;
0434 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0435 clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
0436 clock-names = "uart", "clk_uart_baud0";
0437 status = "disabled";
0438 };
0439
0440 mmc_0: mmc@12140000 {
0441 compatible = "samsung,exynos5250-dw-mshc";
0442 reg = <0x12140000 0x2000>;
0443 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
0447 clock-names = "biu", "ciu";
0448 assigned-clocks =
0449 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>,
0450 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>,
0451 <&clock_top TOP_SCLK_MMC0>;
0452 assigned-clock-parents =
0453 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
0454 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>;
0455 assigned-clock-rates = <0>, <0>, <800000000>;
0456 fifo-depth = <64>;
0457 status = "disabled";
0458 };
0459
0460 mmc_1: mmc@12150000 {
0461 compatible = "samsung,exynos5250-dw-mshc";
0462 reg = <0x12150000 0x2000>;
0463 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0464 #address-cells = <1>;
0465 #size-cells = <0>;
0466 clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
0467 clock-names = "biu", "ciu";
0468 assigned-clocks =
0469 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>,
0470 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>,
0471 <&clock_top TOP_SCLK_MMC1>;
0472 assigned-clock-parents =
0473 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
0474 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>;
0475 assigned-clock-rates = <0>, <0>, <800000000>;
0476 fifo-depth = <64>;
0477 status = "disabled";
0478 };
0479
0480 mmc_2: mmc@12160000 {
0481 compatible = "samsung,exynos5250-dw-mshc";
0482 reg = <0x12160000 0x2000>;
0483 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0484 #address-cells = <1>;
0485 #size-cells = <0>;
0486 clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
0487 clock-names = "biu", "ciu";
0488 assigned-clocks =
0489 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>,
0490 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>,
0491 <&clock_top TOP_SCLK_MMC2>;
0492 assigned-clock-parents =
0493 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
0494 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>;
0495 assigned-clock-rates = <0>, <0>, <800000000>;
0496 fifo-depth = <64>;
0497 status = "disabled";
0498 };
0499
0500 hsi2c_0: i2c@12da0000 {
0501 compatible = "samsung,exynos5260-hsi2c";
0502 reg = <0x12DA0000 0x1000>;
0503 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0504 #address-cells = <1>;
0505 #size-cells = <0>;
0506 pinctrl-names = "default";
0507 pinctrl-0 = <&i2c0_hs_bus>;
0508 clocks = <&clock_peri PERI_CLK_HSIC0>;
0509 clock-names = "hsi2c";
0510 status = "disabled";
0511 };
0512
0513 hsi2c_1: i2c@12db0000 {
0514 compatible = "samsung,exynos5260-hsi2c";
0515 reg = <0x12DB0000 0x1000>;
0516 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0517 #address-cells = <1>;
0518 #size-cells = <0>;
0519 pinctrl-names = "default";
0520 pinctrl-0 = <&i2c1_hs_bus>;
0521 clocks = <&clock_peri PERI_CLK_HSIC1>;
0522 clock-names = "hsi2c";
0523 status = "disabled";
0524 };
0525
0526 hsi2c_2: i2c@12dc0000 {
0527 compatible = "samsung,exynos5260-hsi2c";
0528 reg = <0x12DC0000 0x1000>;
0529 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0530 #address-cells = <1>;
0531 #size-cells = <0>;
0532 pinctrl-names = "default";
0533 pinctrl-0 = <&i2c2_hs_bus>;
0534 clocks = <&clock_peri PERI_CLK_HSIC2>;
0535 clock-names = "hsi2c";
0536 status = "disabled";
0537 };
0538
0539 hsi2c_3: i2c@12dd0000 {
0540 compatible = "samsung,exynos5260-hsi2c";
0541 reg = <0x12DD0000 0x1000>;
0542 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0543 #address-cells = <1>;
0544 #size-cells = <0>;
0545 pinctrl-names = "default";
0546 pinctrl-0 = <&i2c3_hs_bus>;
0547 clocks = <&clock_peri PERI_CLK_HSIC3>;
0548 clock-names = "hsi2c";
0549 status = "disabled";
0550 };
0551 };
0552 };
0553
0554 #include "exynos5260-pinctrl.dtsi"
