0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos5250 SoC device tree source
0004 *
0005 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * Samsung Exynos5250 SoC device nodes are listed in this file.
0009 * Exynos5250 based board files can include this file and provide
0010 * values for board specfic bindings.
0011 *
0012 * Note: This file does not include device nodes for all the controllers in
0013 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
0014 * additional nodes can be added to this file.
0015 */
0016
0017 #include <dt-bindings/clock/exynos5250.h>
0018 #include "exynos5.dtsi"
0019 #include "exynos4-cpu-thermal.dtsi"
0020 #include <dt-bindings/clock/exynos-audss-clk.h>
0021
0022 / {
0023 compatible = "samsung,exynos5250", "samsung,exynos5";
0024
0025 aliases {
0026 spi0 = &spi_0;
0027 spi1 = &spi_1;
0028 spi2 = &spi_2;
0029 gsc0 = &gsc_0;
0030 gsc1 = &gsc_1;
0031 gsc2 = &gsc_2;
0032 gsc3 = &gsc_3;
0033 mshc0 = &mmc_0;
0034 mshc1 = &mmc_1;
0035 mshc2 = &mmc_2;
0036 mshc3 = &mmc_3;
0037 i2c4 = &i2c_4;
0038 i2c5 = &i2c_5;
0039 i2c6 = &i2c_6;
0040 i2c7 = &i2c_7;
0041 i2c8 = &i2c_8;
0042 i2c9 = &i2c_9;
0043 pinctrl0 = &pinctrl_0;
0044 pinctrl1 = &pinctrl_1;
0045 pinctrl2 = &pinctrl_2;
0046 pinctrl3 = &pinctrl_3;
0047 };
0048
0049 cpus {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 cpu-map {
0054 cluster0 {
0055 core0 {
0056 cpu = <&cpu0>;
0057 };
0058 core1 {
0059 cpu = <&cpu1>;
0060 };
0061 };
0062 };
0063
0064 cpu0: cpu@0 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a15";
0067 reg = <0>;
0068 clocks = <&clock CLK_ARM_CLK>;
0069 clock-names = "cpu";
0070 operating-points-v2 = <&cpu0_opp_table>;
0071 #cooling-cells = <2>; /* min followed by max */
0072 };
0073 cpu1: cpu@1 {
0074 device_type = "cpu";
0075 compatible = "arm,cortex-a15";
0076 reg = <1>;
0077 clocks = <&clock CLK_ARM_CLK>;
0078 clock-names = "cpu";
0079 operating-points-v2 = <&cpu0_opp_table>;
0080 #cooling-cells = <2>; /* min followed by max */
0081 };
0082 };
0083
0084 cpu0_opp_table: opp-table0 {
0085 compatible = "operating-points-v2";
0086 opp-shared;
0087
0088 opp-200000000 {
0089 opp-hz = /bits/ 64 <200000000>;
0090 opp-microvolt = <925000>;
0091 clock-latency-ns = <140000>;
0092 };
0093 opp-300000000 {
0094 opp-hz = /bits/ 64 <300000000>;
0095 opp-microvolt = <937500>;
0096 clock-latency-ns = <140000>;
0097 };
0098 opp-400000000 {
0099 opp-hz = /bits/ 64 <400000000>;
0100 opp-microvolt = <950000>;
0101 clock-latency-ns = <140000>;
0102 };
0103 opp-500000000 {
0104 opp-hz = /bits/ 64 <500000000>;
0105 opp-microvolt = <975000>;
0106 clock-latency-ns = <140000>;
0107 };
0108 opp-600000000 {
0109 opp-hz = /bits/ 64 <600000000>;
0110 opp-microvolt = <1000000>;
0111 clock-latency-ns = <140000>;
0112 };
0113 opp-700000000 {
0114 opp-hz = /bits/ 64 <700000000>;
0115 opp-microvolt = <1012500>;
0116 clock-latency-ns = <140000>;
0117 };
0118 opp-800000000 {
0119 opp-hz = /bits/ 64 <800000000>;
0120 opp-microvolt = <1025000>;
0121 clock-latency-ns = <140000>;
0122 };
0123 opp-900000000 {
0124 opp-hz = /bits/ 64 <900000000>;
0125 opp-microvolt = <1050000>;
0126 clock-latency-ns = <140000>;
0127 };
0128 opp-1000000000 {
0129 opp-hz = /bits/ 64 <1000000000>;
0130 opp-microvolt = <1075000>;
0131 clock-latency-ns = <140000>;
0132 opp-suspend;
0133 };
0134 opp-1100000000 {
0135 opp-hz = /bits/ 64 <1100000000>;
0136 opp-microvolt = <1100000>;
0137 clock-latency-ns = <140000>;
0138 };
0139 opp-1200000000 {
0140 opp-hz = /bits/ 64 <1200000000>;
0141 opp-microvolt = <1125000>;
0142 clock-latency-ns = <140000>;
0143 };
0144 opp-1300000000 {
0145 opp-hz = /bits/ 64 <1300000000>;
0146 opp-microvolt = <1150000>;
0147 clock-latency-ns = <140000>;
0148 };
0149 opp-1400000000 {
0150 opp-hz = /bits/ 64 <1400000000>;
0151 opp-microvolt = <1200000>;
0152 clock-latency-ns = <140000>;
0153 };
0154 opp-1500000000 {
0155 opp-hz = /bits/ 64 <1500000000>;
0156 opp-microvolt = <1225000>;
0157 clock-latency-ns = <140000>;
0158 };
0159 opp-1600000000 {
0160 opp-hz = /bits/ 64 <1600000000>;
0161 opp-microvolt = <1250000>;
0162 clock-latency-ns = <140000>;
0163 };
0164 opp-1700000000 {
0165 opp-hz = /bits/ 64 <1700000000>;
0166 opp-microvolt = <1300000>;
0167 clock-latency-ns = <140000>;
0168 };
0169 };
0170
0171 pmu {
0172 compatible = "arm,cortex-a15-pmu";
0173 interrupt-parent = <&combiner>;
0174 interrupts = <1 2>, <22 4>;
0175 };
0176
0177 soc: soc {
0178 sram@2020000 {
0179 compatible = "mmio-sram";
0180 reg = <0x02020000 0x30000>;
0181 #address-cells = <1>;
0182 #size-cells = <1>;
0183 ranges = <0 0x02020000 0x30000>;
0184
0185 smp-sram@0 {
0186 compatible = "samsung,exynos4210-sysram";
0187 reg = <0x0 0x1000>;
0188 };
0189
0190 smp-sram@2f000 {
0191 compatible = "samsung,exynos4210-sysram-ns";
0192 reg = <0x2f000 0x1000>;
0193 };
0194 };
0195
0196 pd_gsc: power-domain@10044000 {
0197 compatible = "samsung,exynos4210-pd";
0198 reg = <0x10044000 0x20>;
0199 #power-domain-cells = <0>;
0200 label = "GSC";
0201 };
0202
0203 pd_mfc: power-domain@10044040 {
0204 compatible = "samsung,exynos4210-pd";
0205 reg = <0x10044040 0x20>;
0206 #power-domain-cells = <0>;
0207 label = "MFC";
0208 };
0209
0210 pd_g3d: power-domain@10044060 {
0211 compatible = "samsung,exynos4210-pd";
0212 reg = <0x10044060 0x20>;
0213 #power-domain-cells = <0>;
0214 label = "G3D";
0215 };
0216
0217 pd_disp1: power-domain@100440a0 {
0218 compatible = "samsung,exynos4210-pd";
0219 reg = <0x100440A0 0x20>;
0220 #power-domain-cells = <0>;
0221 label = "DISP1";
0222 };
0223
0224 pd_mau: power-domain@100440c0 {
0225 compatible = "samsung,exynos4210-pd";
0226 reg = <0x100440C0 0x20>;
0227 #power-domain-cells = <0>;
0228 label = "MAU";
0229 };
0230
0231 clock: clock-controller@10010000 {
0232 compatible = "samsung,exynos5250-clock";
0233 reg = <0x10010000 0x30000>;
0234 #clock-cells = <1>;
0235 };
0236
0237 clock_audss: audss-clock-controller@3810000 {
0238 compatible = "samsung,exynos5250-audss-clock";
0239 reg = <0x03810000 0x0C>;
0240 #clock-cells = <1>;
0241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
0242 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
0243 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
0244 power-domains = <&pd_mau>;
0245 };
0246
0247 timer@101c0000 {
0248 compatible = "samsung,exynos5250-mct",
0249 "samsung,exynos4210-mct";
0250 reg = <0x101C0000 0x800>;
0251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
0252 clock-names = "fin_pll", "mct";
0253 interrupts-extended = <&combiner 23 3>,
0254 <&combiner 23 4>,
0255 <&combiner 25 2>,
0256 <&combiner 25 3>,
0257 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0258 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0259 };
0260
0261 pinctrl_0: pinctrl@11400000 {
0262 compatible = "samsung,exynos5250-pinctrl";
0263 reg = <0x11400000 0x1000>;
0264 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0265
0266 wakup_eint: wakeup-interrupt-controller {
0267 compatible = "samsung,exynos4210-wakeup-eint";
0268 interrupt-parent = <&gic>;
0269 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0270 };
0271 };
0272
0273 pinctrl_1: pinctrl@13400000 {
0274 compatible = "samsung,exynos5250-pinctrl";
0275 reg = <0x13400000 0x1000>;
0276 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0277 };
0278
0279 pinctrl_2: pinctrl@10d10000 {
0280 compatible = "samsung,exynos5250-pinctrl";
0281 reg = <0x10d10000 0x1000>;
0282 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0283 };
0284
0285 pinctrl_3: pinctrl@3860000 {
0286 compatible = "samsung,exynos5250-pinctrl";
0287 reg = <0x03860000 0x1000>;
0288 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0289 power-domains = <&pd_mau>;
0290 };
0291
0292 pmu_system_controller: system-controller@10040000 {
0293 compatible = "samsung,exynos5250-pmu", "syscon";
0294 reg = <0x10040000 0x5000>;
0295 clock-names = "clkout16";
0296 clocks = <&clock CLK_FIN_PLL>;
0297 #clock-cells = <1>;
0298 interrupt-controller;
0299 #interrupt-cells = <3>;
0300 interrupt-parent = <&gic>;
0301 };
0302
0303 watchdog@101d0000 {
0304 compatible = "samsung,exynos5250-wdt";
0305 reg = <0x101D0000 0x100>;
0306 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0307 clocks = <&clock CLK_WDT>;
0308 clock-names = "watchdog";
0309 samsung,syscon-phandle = <&pmu_system_controller>;
0310 };
0311
0312 mfc: codec@11000000 {
0313 compatible = "samsung,mfc-v6";
0314 reg = <0x11000000 0x10000>;
0315 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0316 power-domains = <&pd_mfc>;
0317 clocks = <&clock CLK_MFC>;
0318 clock-names = "mfc";
0319 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
0320 iommu-names = "left", "right";
0321 };
0322
0323 rotator: rotator@11c00000 {
0324 compatible = "samsung,exynos5250-rotator";
0325 reg = <0x11C00000 0x64>;
0326 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0327 clocks = <&clock CLK_ROTATOR>;
0328 clock-names = "rotator";
0329 iommus = <&sysmmu_rotator>;
0330 };
0331
0332 mali: gpu@11800000 {
0333 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
0334 reg = <0x11800000 0x5000>;
0335 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0336 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0337 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0338 interrupt-names = "job", "mmu", "gpu";
0339 clocks = <&clock CLK_G3D>;
0340 clock-names = "core";
0341 operating-points-v2 = <&gpu_opp_table>;
0342 power-domains = <&pd_g3d>;
0343 status = "disabled";
0344
0345 gpu_opp_table: opp-table {
0346 compatible = "operating-points-v2";
0347
0348 opp-100000000 {
0349 opp-hz = /bits/ 64 <100000000>;
0350 opp-microvolt = <925000>;
0351 };
0352 opp-160000000 {
0353 opp-hz = /bits/ 64 <160000000>;
0354 opp-microvolt = <925000>;
0355 };
0356 opp-266000000 {
0357 opp-hz = /bits/ 64 <266000000>;
0358 opp-microvolt = <1025000>;
0359 };
0360 opp-350000000 {
0361 opp-hz = /bits/ 64 <350000000>;
0362 opp-microvolt = <1075000>;
0363 };
0364 opp-400000000 {
0365 opp-hz = /bits/ 64 <400000000>;
0366 opp-microvolt = <1125000>;
0367 };
0368 opp-450000000 {
0369 opp-hz = /bits/ 64 <450000000>;
0370 opp-microvolt = <1150000>;
0371 };
0372 opp-533000000 {
0373 opp-hz = /bits/ 64 <533000000>;
0374 opp-microvolt = <1250000>;
0375 };
0376 };
0377 };
0378
0379 tmu: tmu@10060000 {
0380 compatible = "samsung,exynos5250-tmu";
0381 reg = <0x10060000 0x100>;
0382 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0383 clocks = <&clock CLK_TMU>;
0384 clock-names = "tmu_apbif";
0385 #thermal-sensor-cells = <0>;
0386 };
0387
0388 sata: sata@122f0000 {
0389 compatible = "snps,dwc-ahci";
0390 reg = <0x122F0000 0x1ff>;
0391 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0392 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
0393 clock-names = "sata", "sclk_sata";
0394 phys = <&sata_phy>;
0395 phy-names = "sata-phy";
0396 ports-implemented = <0x1>;
0397 status = "disabled";
0398 };
0399
0400 sata_phy: sata-phy@12170000 {
0401 compatible = "samsung,exynos5250-sata-phy";
0402 reg = <0x12170000 0x1ff>;
0403 clocks = <&clock CLK_SATA_PHYCTRL>;
0404 clock-names = "sata_phyctrl";
0405 #phy-cells = <0>;
0406 samsung,syscon-phandle = <&pmu_system_controller>;
0407 status = "disabled";
0408 };
0409
0410 /* i2c_0-3 are defined in exynos5.dtsi */
0411 i2c_4: i2c@12ca0000 {
0412 compatible = "samsung,s3c2440-i2c";
0413 reg = <0x12CA0000 0x100>;
0414 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0415 #address-cells = <1>;
0416 #size-cells = <0>;
0417 clocks = <&clock CLK_I2C4>;
0418 clock-names = "i2c";
0419 pinctrl-names = "default";
0420 pinctrl-0 = <&i2c4_bus>;
0421 status = "disabled";
0422 };
0423
0424 i2c_5: i2c@12cb0000 {
0425 compatible = "samsung,s3c2440-i2c";
0426 reg = <0x12CB0000 0x100>;
0427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0428 #address-cells = <1>;
0429 #size-cells = <0>;
0430 clocks = <&clock CLK_I2C5>;
0431 clock-names = "i2c";
0432 pinctrl-names = "default";
0433 pinctrl-0 = <&i2c5_bus>;
0434 status = "disabled";
0435 };
0436
0437 i2c_6: i2c@12cc0000 {
0438 compatible = "samsung,s3c2440-i2c";
0439 reg = <0x12CC0000 0x100>;
0440 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0441 #address-cells = <1>;
0442 #size-cells = <0>;
0443 clocks = <&clock CLK_I2C6>;
0444 clock-names = "i2c";
0445 pinctrl-names = "default";
0446 pinctrl-0 = <&i2c6_bus>;
0447 status = "disabled";
0448 };
0449
0450 i2c_7: i2c@12cd0000 {
0451 compatible = "samsung,s3c2440-i2c";
0452 reg = <0x12CD0000 0x100>;
0453 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0454 #address-cells = <1>;
0455 #size-cells = <0>;
0456 clocks = <&clock CLK_I2C7>;
0457 clock-names = "i2c";
0458 pinctrl-names = "default";
0459 pinctrl-0 = <&i2c7_bus>;
0460 status = "disabled";
0461 };
0462
0463 i2c_8: i2c@12ce0000 {
0464 compatible = "samsung,s3c2440-hdmiphy-i2c";
0465 reg = <0x12CE0000 0x1000>;
0466 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0467 #address-cells = <1>;
0468 #size-cells = <0>;
0469 clocks = <&clock CLK_I2C_HDMI>;
0470 clock-names = "i2c";
0471 status = "disabled";
0472
0473 hdmiphy: hdmiphy@38 {
0474 compatible = "samsung,exynos4212-hdmiphy";
0475 reg = <0x38>;
0476 };
0477 };
0478
0479 i2c_9: i2c@121d0000 {
0480 compatible = "samsung,exynos5-sata-phy-i2c";
0481 reg = <0x121D0000 0x100>;
0482 #address-cells = <1>;
0483 #size-cells = <0>;
0484 clocks = <&clock CLK_SATA_PHYI2C>;
0485 clock-names = "i2c";
0486 status = "disabled";
0487
0488 sata_phy_i2c: sata-phy-i2c@38 {
0489 compatible = "samsung,exynos-sataphy-i2c";
0490 reg = <0x38>;
0491 status = "disabled";
0492 };
0493 };
0494
0495 spi_0: spi@12d20000 {
0496 compatible = "samsung,exynos4210-spi";
0497 status = "disabled";
0498 reg = <0x12d20000 0x100>;
0499 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0500 dmas = <&pdma0 5>, <&pdma0 4>;
0501 dma-names = "tx", "rx";
0502 #address-cells = <1>;
0503 #size-cells = <0>;
0504 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
0505 clock-names = "spi", "spi_busclk0";
0506 pinctrl-names = "default";
0507 pinctrl-0 = <&spi0_bus>;
0508 };
0509
0510 spi_1: spi@12d30000 {
0511 compatible = "samsung,exynos4210-spi";
0512 status = "disabled";
0513 reg = <0x12d30000 0x100>;
0514 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0515 dmas = <&pdma1 5>, <&pdma1 4>;
0516 dma-names = "tx", "rx";
0517 #address-cells = <1>;
0518 #size-cells = <0>;
0519 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
0520 clock-names = "spi", "spi_busclk0";
0521 pinctrl-names = "default";
0522 pinctrl-0 = <&spi1_bus>;
0523 };
0524
0525 spi_2: spi@12d40000 {
0526 compatible = "samsung,exynos4210-spi";
0527 status = "disabled";
0528 reg = <0x12d40000 0x100>;
0529 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0530 dmas = <&pdma0 7>, <&pdma0 6>;
0531 dma-names = "tx", "rx";
0532 #address-cells = <1>;
0533 #size-cells = <0>;
0534 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
0535 clock-names = "spi", "spi_busclk0";
0536 pinctrl-names = "default";
0537 pinctrl-0 = <&spi2_bus>;
0538 };
0539
0540 mmc_0: mmc@12200000 {
0541 compatible = "samsung,exynos5250-dw-mshc";
0542 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0543 #address-cells = <1>;
0544 #size-cells = <0>;
0545 reg = <0x12200000 0x1000>;
0546 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
0547 clock-names = "biu", "ciu";
0548 fifo-depth = <0x80>;
0549 status = "disabled";
0550 };
0551
0552 mmc_1: mmc@12210000 {
0553 compatible = "samsung,exynos5250-dw-mshc";
0554 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0555 #address-cells = <1>;
0556 #size-cells = <0>;
0557 reg = <0x12210000 0x1000>;
0558 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
0559 clock-names = "biu", "ciu";
0560 fifo-depth = <0x80>;
0561 status = "disabled";
0562 };
0563
0564 mmc_2: mmc@12220000 {
0565 compatible = "samsung,exynos5250-dw-mshc";
0566 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0567 #address-cells = <1>;
0568 #size-cells = <0>;
0569 reg = <0x12220000 0x1000>;
0570 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
0571 clock-names = "biu", "ciu";
0572 fifo-depth = <0x80>;
0573 status = "disabled";
0574 };
0575
0576 mmc_3: mmc@12230000 {
0577 compatible = "samsung,exynos5250-dw-mshc";
0578 reg = <0x12230000 0x1000>;
0579 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0580 #address-cells = <1>;
0581 #size-cells = <0>;
0582 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
0583 clock-names = "biu", "ciu";
0584 fifo-depth = <0x80>;
0585 status = "disabled";
0586 };
0587
0588 i2s0: i2s@3830000 {
0589 compatible = "samsung,s5pv210-i2s";
0590 status = "disabled";
0591 reg = <0x03830000 0x100>;
0592 dmas = <&pdma0 10>,
0593 <&pdma0 9>,
0594 <&pdma0 8>;
0595 dma-names = "tx", "rx", "tx-sec";
0596 clocks = <&clock_audss EXYNOS_I2S_BUS>,
0597 <&clock_audss EXYNOS_I2S_BUS>,
0598 <&clock_audss EXYNOS_SCLK_I2S>;
0599 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
0600 samsung,idma-addr = <0x03000000>;
0601 pinctrl-names = "default";
0602 pinctrl-0 = <&i2s0_bus>;
0603 power-domains = <&pd_mau>;
0604 #clock-cells = <1>;
0605 #sound-dai-cells = <1>;
0606 };
0607
0608 i2s1: i2s@12d60000 {
0609 compatible = "samsung,s3c6410-i2s";
0610 status = "disabled";
0611 reg = <0x12D60000 0x100>;
0612 dmas = <&pdma1 12>,
0613 <&pdma1 11>;
0614 dma-names = "tx", "rx";
0615 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
0616 clock-names = "iis", "i2s_opclk0";
0617 pinctrl-names = "default";
0618 pinctrl-0 = <&i2s1_bus>;
0619 power-domains = <&pd_mau>;
0620 #sound-dai-cells = <1>;
0621 };
0622
0623 i2s2: i2s@12d70000 {
0624 compatible = "samsung,s3c6410-i2s";
0625 status = "disabled";
0626 reg = <0x12D70000 0x100>;
0627 dmas = <&pdma0 12>,
0628 <&pdma0 11>;
0629 dma-names = "tx", "rx";
0630 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
0631 clock-names = "iis", "i2s_opclk0";
0632 pinctrl-names = "default";
0633 pinctrl-0 = <&i2s2_bus>;
0634 power-domains = <&pd_mau>;
0635 #sound-dai-cells = <1>;
0636 };
0637
0638 usbdrd: usb3 {
0639 compatible = "samsung,exynos5250-dwusb3";
0640 clocks = <&clock CLK_USB3>;
0641 clock-names = "usbdrd30";
0642 #address-cells = <1>;
0643 #size-cells = <1>;
0644 ranges;
0645
0646 usbdrd_dwc3: usb@12000000 {
0647 compatible = "snps,dwc3";
0648 reg = <0x12000000 0x10000>;
0649 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0650 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
0651 phy-names = "usb2-phy", "usb3-phy";
0652 };
0653 };
0654
0655 usbdrd_phy: phy@12100000 {
0656 compatible = "samsung,exynos5250-usbdrd-phy";
0657 reg = <0x12100000 0x100>;
0658 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
0659 clock-names = "phy", "ref";
0660 samsung,pmu-syscon = <&pmu_system_controller>;
0661 #phy-cells = <1>;
0662 };
0663
0664 ehci: usb@12110000 {
0665 compatible = "samsung,exynos4210-ehci";
0666 reg = <0x12110000 0x100>;
0667 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0668
0669 clocks = <&clock CLK_USB2>;
0670 clock-names = "usbhost";
0671 phys = <&usb2_phy_gen 1>;
0672 phy-names = "host";
0673 };
0674
0675 ohci: usb@12120000 {
0676 compatible = "samsung,exynos4210-ohci";
0677 reg = <0x12120000 0x100>;
0678 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0679
0680 clocks = <&clock CLK_USB2>;
0681 clock-names = "usbhost";
0682 phys = <&usb2_phy_gen 1>;
0683 phy-names = "host";
0684 };
0685
0686 usb2_phy_gen: phy@12130000 {
0687 compatible = "samsung,exynos5250-usb2-phy";
0688 reg = <0x12130000 0x100>;
0689 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
0690 clock-names = "phy", "ref";
0691 #phy-cells = <1>;
0692 samsung,sysreg-phandle = <&sysreg_system_controller>;
0693 samsung,pmureg-phandle = <&pmu_system_controller>;
0694 };
0695
0696 pdma0: dma-controller@121a0000 {
0697 compatible = "arm,pl330", "arm,primecell";
0698 reg = <0x121A0000 0x1000>;
0699 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0700 clocks = <&clock CLK_PDMA0>;
0701 clock-names = "apb_pclk";
0702 #dma-cells = <1>;
0703 };
0704
0705 pdma1: dma-controller@121b0000 {
0706 compatible = "arm,pl330", "arm,primecell";
0707 reg = <0x121B0000 0x1000>;
0708 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0709 clocks = <&clock CLK_PDMA1>;
0710 clock-names = "apb_pclk";
0711 #dma-cells = <1>;
0712 };
0713
0714 mdma0: dma-controller@10800000 {
0715 compatible = "arm,pl330", "arm,primecell";
0716 reg = <0x10800000 0x1000>;
0717 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0718 clocks = <&clock CLK_MDMA0>;
0719 clock-names = "apb_pclk";
0720 #dma-cells = <1>;
0721 };
0722
0723 mdma1: dma-controller@11c10000 {
0724 compatible = "arm,pl330", "arm,primecell";
0725 reg = <0x11C10000 0x1000>;
0726 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
0727 clocks = <&clock CLK_MDMA1>;
0728 clock-names = "apb_pclk";
0729 #dma-cells = <1>;
0730 };
0731
0732 gsc_0: gsc@13e00000 {
0733 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
0734 reg = <0x13e00000 0x1000>;
0735 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0736 power-domains = <&pd_gsc>;
0737 clocks = <&clock CLK_GSCL0>;
0738 clock-names = "gscl";
0739 iommus = <&sysmmu_gsc0>;
0740 };
0741
0742 gsc_1: gsc@13e10000 {
0743 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
0744 reg = <0x13e10000 0x1000>;
0745 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0746 power-domains = <&pd_gsc>;
0747 clocks = <&clock CLK_GSCL1>;
0748 clock-names = "gscl";
0749 iommus = <&sysmmu_gsc1>;
0750 };
0751
0752 gsc_2: gsc@13e20000 {
0753 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
0754 reg = <0x13e20000 0x1000>;
0755 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0756 power-domains = <&pd_gsc>;
0757 clocks = <&clock CLK_GSCL2>;
0758 clock-names = "gscl";
0759 iommus = <&sysmmu_gsc2>;
0760 };
0761
0762 gsc_3: gsc@13e30000 {
0763 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
0764 reg = <0x13e30000 0x1000>;
0765 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0766 power-domains = <&pd_gsc>;
0767 clocks = <&clock CLK_GSCL3>;
0768 clock-names = "gscl";
0769 iommus = <&sysmmu_gsc3>;
0770 };
0771
0772 hdmi: hdmi@14530000 {
0773 compatible = "samsung,exynos4212-hdmi";
0774 reg = <0x14530000 0x70000>;
0775 power-domains = <&pd_disp1>;
0776 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0777 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
0778 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
0779 <&clock CLK_MOUT_HDMI>;
0780 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
0781 "sclk_hdmiphy", "mout_hdmi";
0782 samsung,syscon-phandle = <&pmu_system_controller>;
0783 phy = <&hdmiphy>;
0784 #sound-dai-cells = <0>;
0785 status = "disabled";
0786 };
0787
0788 hdmicec: cec@101b0000 {
0789 compatible = "samsung,s5p-cec";
0790 reg = <0x101B0000 0x200>;
0791 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0792 clocks = <&clock CLK_HDMI_CEC>;
0793 clock-names = "hdmicec";
0794 samsung,syscon-phandle = <&pmu_system_controller>;
0795 hdmi-phandle = <&hdmi>;
0796 pinctrl-names = "default";
0797 pinctrl-0 = <&hdmi_cec>;
0798 status = "disabled";
0799 };
0800
0801 mixer: mixer@14450000 {
0802 compatible = "samsung,exynos5250-mixer";
0803 reg = <0x14450000 0x10000>;
0804 power-domains = <&pd_disp1>;
0805 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0806 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
0807 <&clock CLK_SCLK_HDMI>;
0808 clock-names = "mixer", "hdmi", "sclk_hdmi";
0809 iommus = <&sysmmu_tv>;
0810 status = "disabled";
0811 };
0812
0813 dp_phy: video-phy-0 {
0814 compatible = "samsung,exynos5250-dp-video-phy";
0815 samsung,pmu-syscon = <&pmu_system_controller>;
0816 #phy-cells = <0>;
0817 };
0818
0819 mipi_phy: video-phy-1 {
0820 compatible = "samsung,s5pv210-mipi-video-phy";
0821 #phy-cells = <1>;
0822 syscon = <&pmu_system_controller>;
0823 };
0824
0825 dsi_0: dsi@14500000 {
0826 compatible = "samsung,exynos4210-mipi-dsi";
0827 reg = <0x14500000 0x10000>;
0828 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0829 samsung,power-domain = <&pd_disp1>;
0830 phys = <&mipi_phy 3>;
0831 phy-names = "dsim";
0832 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
0833 clock-names = "bus_clk", "sclk_mipi";
0834 status = "disabled";
0835 #address-cells = <1>;
0836 #size-cells = <0>;
0837 };
0838
0839 adc: adc@12d10000 {
0840 compatible = "samsung,exynos-adc-v1";
0841 reg = <0x12D10000 0x100>;
0842 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0843 clocks = <&clock CLK_ADC>;
0844 clock-names = "adc";
0845 #io-channel-cells = <1>;
0846 samsung,syscon-phandle = <&pmu_system_controller>;
0847 status = "disabled";
0848 };
0849
0850 sysmmu_g2d: sysmmu@10a60000 {
0851 compatible = "samsung,exynos-sysmmu";
0852 reg = <0x10A60000 0x1000>;
0853 interrupt-parent = <&combiner>;
0854 interrupts = <24 5>;
0855 clock-names = "sysmmu", "master";
0856 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
0857 #iommu-cells = <0>;
0858 };
0859
0860 sysmmu_mfc_r: sysmmu@11200000 {
0861 compatible = "samsung,exynos-sysmmu";
0862 reg = <0x11200000 0x1000>;
0863 interrupt-parent = <&combiner>;
0864 interrupts = <6 2>;
0865 power-domains = <&pd_mfc>;
0866 clock-names = "sysmmu", "master";
0867 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
0868 #iommu-cells = <0>;
0869 };
0870
0871 sysmmu_mfc_l: sysmmu@11210000 {
0872 compatible = "samsung,exynos-sysmmu";
0873 reg = <0x11210000 0x1000>;
0874 interrupt-parent = <&combiner>;
0875 interrupts = <8 5>;
0876 power-domains = <&pd_mfc>;
0877 clock-names = "sysmmu", "master";
0878 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
0879 #iommu-cells = <0>;
0880 };
0881
0882 sysmmu_rotator: sysmmu@11d40000 {
0883 compatible = "samsung,exynos-sysmmu";
0884 reg = <0x11D40000 0x1000>;
0885 interrupt-parent = <&combiner>;
0886 interrupts = <4 0>;
0887 clock-names = "sysmmu", "master";
0888 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
0889 #iommu-cells = <0>;
0890 };
0891
0892 sysmmu_jpeg: sysmmu@11f20000 {
0893 compatible = "samsung,exynos-sysmmu";
0894 reg = <0x11F20000 0x1000>;
0895 interrupt-parent = <&combiner>;
0896 interrupts = <4 2>;
0897 power-domains = <&pd_gsc>;
0898 clock-names = "sysmmu", "master";
0899 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
0900 #iommu-cells = <0>;
0901 };
0902
0903 sysmmu_fimc_isp: sysmmu@13260000 {
0904 compatible = "samsung,exynos-sysmmu";
0905 reg = <0x13260000 0x1000>;
0906 interrupt-parent = <&combiner>;
0907 interrupts = <10 6>;
0908 clock-names = "sysmmu";
0909 clocks = <&clock CLK_SMMU_FIMC_ISP>;
0910 #iommu-cells = <0>;
0911 };
0912
0913 sysmmu_fimc_drc: sysmmu@13270000 {
0914 compatible = "samsung,exynos-sysmmu";
0915 reg = <0x13270000 0x1000>;
0916 interrupt-parent = <&combiner>;
0917 interrupts = <11 6>;
0918 clock-names = "sysmmu";
0919 clocks = <&clock CLK_SMMU_FIMC_DRC>;
0920 #iommu-cells = <0>;
0921 };
0922
0923 sysmmu_fimc_fd: sysmmu@132a0000 {
0924 compatible = "samsung,exynos-sysmmu";
0925 reg = <0x132A0000 0x1000>;
0926 interrupt-parent = <&combiner>;
0927 interrupts = <5 0>;
0928 clock-names = "sysmmu";
0929 clocks = <&clock CLK_SMMU_FIMC_FD>;
0930 #iommu-cells = <0>;
0931 };
0932
0933 sysmmu_fimc_scc: sysmmu@13280000 {
0934 compatible = "samsung,exynos-sysmmu";
0935 reg = <0x13280000 0x1000>;
0936 interrupt-parent = <&combiner>;
0937 interrupts = <5 2>;
0938 clock-names = "sysmmu";
0939 clocks = <&clock CLK_SMMU_FIMC_SCC>;
0940 #iommu-cells = <0>;
0941 };
0942
0943 sysmmu_fimc_scp: sysmmu@13290000 {
0944 compatible = "samsung,exynos-sysmmu";
0945 reg = <0x13290000 0x1000>;
0946 interrupt-parent = <&combiner>;
0947 interrupts = <3 6>;
0948 clock-names = "sysmmu";
0949 clocks = <&clock CLK_SMMU_FIMC_SCP>;
0950 #iommu-cells = <0>;
0951 };
0952
0953 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
0954 compatible = "samsung,exynos-sysmmu";
0955 reg = <0x132B0000 0x1000>;
0956 interrupt-parent = <&combiner>;
0957 interrupts = <5 4>;
0958 clock-names = "sysmmu";
0959 clocks = <&clock CLK_SMMU_FIMC_MCU>;
0960 #iommu-cells = <0>;
0961 };
0962
0963 sysmmu_fimc_odc: sysmmu@132c0000 {
0964 compatible = "samsung,exynos-sysmmu";
0965 reg = <0x132C0000 0x1000>;
0966 interrupt-parent = <&combiner>;
0967 interrupts = <11 0>;
0968 clock-names = "sysmmu";
0969 clocks = <&clock CLK_SMMU_FIMC_ODC>;
0970 #iommu-cells = <0>;
0971 };
0972
0973 sysmmu_fimc_dis0: sysmmu@132d0000 {
0974 compatible = "samsung,exynos-sysmmu";
0975 reg = <0x132D0000 0x1000>;
0976 interrupt-parent = <&combiner>;
0977 interrupts = <10 4>;
0978 clock-names = "sysmmu";
0979 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
0980 #iommu-cells = <0>;
0981 };
0982
0983 sysmmu_fimc_dis1: sysmmu@132e0000 {
0984 compatible = "samsung,exynos-sysmmu";
0985 reg = <0x132E0000 0x1000>;
0986 interrupt-parent = <&combiner>;
0987 interrupts = <9 4>;
0988 clock-names = "sysmmu";
0989 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
0990 #iommu-cells = <0>;
0991 };
0992
0993 sysmmu_fimc_3dnr: sysmmu@132f0000 {
0994 compatible = "samsung,exynos-sysmmu";
0995 reg = <0x132F0000 0x1000>;
0996 interrupt-parent = <&combiner>;
0997 interrupts = <5 6>;
0998 clock-names = "sysmmu";
0999 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
1000 #iommu-cells = <0>;
1001 };
1002
1003 sysmmu_fimc_lite0: sysmmu@13c40000 {
1004 compatible = "samsung,exynos-sysmmu";
1005 reg = <0x13C40000 0x1000>;
1006 interrupt-parent = <&combiner>;
1007 interrupts = <3 4>;
1008 power-domains = <&pd_gsc>;
1009 clock-names = "sysmmu", "master";
1010 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1011 #iommu-cells = <0>;
1012 };
1013
1014 sysmmu_fimc_lite1: sysmmu@13c50000 {
1015 compatible = "samsung,exynos-sysmmu";
1016 reg = <0x13C50000 0x1000>;
1017 interrupt-parent = <&combiner>;
1018 interrupts = <24 1>;
1019 power-domains = <&pd_gsc>;
1020 clock-names = "sysmmu", "master";
1021 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1022 #iommu-cells = <0>;
1023 };
1024
1025 sysmmu_gsc0: sysmmu@13e80000 {
1026 compatible = "samsung,exynos-sysmmu";
1027 reg = <0x13E80000 0x1000>;
1028 interrupt-parent = <&combiner>;
1029 interrupts = <2 0>;
1030 power-domains = <&pd_gsc>;
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1033 #iommu-cells = <0>;
1034 };
1035
1036 sysmmu_gsc1: sysmmu@13e90000 {
1037 compatible = "samsung,exynos-sysmmu";
1038 reg = <0x13E90000 0x1000>;
1039 interrupt-parent = <&combiner>;
1040 interrupts = <2 2>;
1041 power-domains = <&pd_gsc>;
1042 clock-names = "sysmmu", "master";
1043 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1044 #iommu-cells = <0>;
1045 };
1046
1047 sysmmu_gsc2: sysmmu@13ea0000 {
1048 compatible = "samsung,exynos-sysmmu";
1049 reg = <0x13EA0000 0x1000>;
1050 interrupt-parent = <&combiner>;
1051 interrupts = <2 4>;
1052 power-domains = <&pd_gsc>;
1053 clock-names = "sysmmu", "master";
1054 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1055 #iommu-cells = <0>;
1056 };
1057
1058 sysmmu_gsc3: sysmmu@13eb0000 {
1059 compatible = "samsung,exynos-sysmmu";
1060 reg = <0x13EB0000 0x1000>;
1061 interrupt-parent = <&combiner>;
1062 interrupts = <2 6>;
1063 power-domains = <&pd_gsc>;
1064 clock-names = "sysmmu", "master";
1065 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1066 #iommu-cells = <0>;
1067 };
1068
1069 sysmmu_fimd1: sysmmu@14640000 {
1070 compatible = "samsung,exynos-sysmmu";
1071 reg = <0x14640000 0x1000>;
1072 interrupt-parent = <&combiner>;
1073 interrupts = <3 2>;
1074 power-domains = <&pd_disp1>;
1075 clock-names = "sysmmu", "master";
1076 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1077 #iommu-cells = <0>;
1078 };
1079
1080 sysmmu_tv: sysmmu@14650000 {
1081 compatible = "samsung,exynos-sysmmu";
1082 reg = <0x14650000 0x1000>;
1083 interrupt-parent = <&combiner>;
1084 interrupts = <7 4>;
1085 power-domains = <&pd_disp1>;
1086 clock-names = "sysmmu", "master";
1087 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1088 #iommu-cells = <0>;
1089 };
1090 };
1091
1092 timer {
1093 compatible = "arm,armv7-timer";
1094 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1095 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1096 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1097 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1098 /*
1099 * Unfortunately we need this since some versions
1100 * of U-Boot on Exynos don't set the CNTFRQ register,
1101 * so we need the value from DT.
1102 */
1103 clock-frequency = <24000000>;
1104 };
1105 };
1106
1107 &cpu_thermal {
1108 polling-delay-passive = <0>;
1109 polling-delay = <0>;
1110 thermal-sensors = <&tmu 0>;
1111
1112 cooling-maps {
1113 map0 {
1114 /* Corresponds to 800MHz at freq_table */
1115 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1116 };
1117 map1 {
1118 /* Corresponds to 200MHz at freq_table */
1119 cooling-device = <&cpu0 15 15>,
1120 <&cpu1 15 15>;
1121 };
1122 };
1123 };
1124
1125 &dp {
1126 power-domains = <&pd_disp1>;
1127 clocks = <&clock CLK_DP>;
1128 clock-names = "dp";
1129 phys = <&dp_phy>;
1130 phy-names = "dp";
1131 };
1132
1133 &fimd {
1134 power-domains = <&pd_disp1>;
1135 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1136 clock-names = "sclk_fimd", "fimd";
1137 iommus = <&sysmmu_fimd1>;
1138 };
1139
1140 &g2d {
1141 iommus = <&sysmmu_g2d>;
1142 clocks = <&clock CLK_G2D>;
1143 clock-names = "fimg2d";
1144 status = "okay";
1145 };
1146
1147 &i2c_0 {
1148 clocks = <&clock CLK_I2C0>;
1149 clock-names = "i2c";
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&i2c0_bus>;
1152 };
1153
1154 &i2c_1 {
1155 clocks = <&clock CLK_I2C1>;
1156 clock-names = "i2c";
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&i2c1_bus>;
1159 };
1160
1161 &i2c_2 {
1162 clocks = <&clock CLK_I2C2>;
1163 clock-names = "i2c";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&i2c2_bus>;
1166 };
1167
1168 &i2c_3 {
1169 clocks = <&clock CLK_I2C3>;
1170 clock-names = "i2c";
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&i2c3_bus>;
1173 };
1174
1175 &prng {
1176 clocks = <&clock CLK_SSS>;
1177 clock-names = "secss";
1178 };
1179
1180 &pwm {
1181 clocks = <&clock CLK_PWM>;
1182 clock-names = "timers";
1183 };
1184
1185 &rtc {
1186 clocks = <&clock CLK_RTC>;
1187 clock-names = "rtc";
1188 interrupt-parent = <&pmu_system_controller>;
1189 status = "disabled";
1190 };
1191
1192 &serial_0 {
1193 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1194 clock-names = "uart", "clk_uart_baud0";
1195 dmas = <&pdma0 13>, <&pdma0 14>;
1196 dma-names = "rx", "tx";
1197 };
1198
1199 &serial_1 {
1200 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1201 clock-names = "uart", "clk_uart_baud0";
1202 dmas = <&pdma1 15>, <&pdma1 16>;
1203 dma-names = "rx", "tx";
1204 };
1205
1206 &serial_2 {
1207 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1208 clock-names = "uart", "clk_uart_baud0";
1209 dmas = <&pdma0 15>, <&pdma0 16>;
1210 dma-names = "rx", "tx";
1211 };
1212
1213 &serial_3 {
1214 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1215 clock-names = "uart", "clk_uart_baud0";
1216 dmas = <&pdma1 17>, <&pdma1 18>;
1217 dma-names = "rx", "tx";
1218 };
1219
1220 &sss {
1221 clocks = <&clock CLK_SSS>;
1222 clock-names = "secss";
1223 };
1224
1225 &trng {
1226 clocks = <&clock CLK_SSS>;
1227 clock-names = "secss";
1228 };
1229
1230 #include "exynos5250-pinctrl.dtsi"
1231 #include "exynos-syscon-restart.dtsi"
