0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's Exynos4210 SoC device tree source
0004 *
0005 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 * Copyright (c) 2010-2011 Linaro Ltd.
0008 * www.linaro.org
0009 *
0010 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
0011 * based board files can include this file and provide values for board specific
0012 * bindings.
0013 *
0014 * Note: This file does not include device nodes for all the controllers in
0015 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
0016 * nodes can be added to this file.
0017 */
0018
0019 #include "exynos4.dtsi"
0020 #include "exynos4-cpu-thermal.dtsi"
0021
0022 / {
0023 compatible = "samsung,exynos4210", "samsung,exynos4";
0024
0025 aliases {
0026 pinctrl0 = &pinctrl_0;
0027 pinctrl1 = &pinctrl_1;
0028 pinctrl2 = &pinctrl_2;
0029 };
0030
0031 cpus {
0032 #address-cells = <1>;
0033 #size-cells = <0>;
0034
0035 cpu-map {
0036 cluster0 {
0037 core0 {
0038 cpu = <&cpu0>;
0039 };
0040 core1 {
0041 cpu = <&cpu1>;
0042 };
0043 };
0044 };
0045
0046 cpu0: cpu@900 {
0047 device_type = "cpu";
0048 compatible = "arm,cortex-a9";
0049 reg = <0x900>;
0050 clocks = <&clock CLK_ARM_CLK>;
0051 clock-names = "cpu";
0052 clock-latency = <160000>;
0053
0054 operating-points = <
0055 1200000 1250000
0056 1000000 1150000
0057 800000 1075000
0058 500000 975000
0059 400000 975000
0060 200000 950000
0061 >;
0062 #cooling-cells = <2>; /* min followed by max */
0063 };
0064
0065 cpu1: cpu@901 {
0066 device_type = "cpu";
0067 compatible = "arm,cortex-a9";
0068 reg = <0x901>;
0069 clocks = <&clock CLK_ARM_CLK>;
0070 clock-names = "cpu";
0071 clock-latency = <160000>;
0072
0073 operating-points = <
0074 1200000 1250000
0075 1000000 1150000
0076 800000 1075000
0077 500000 975000
0078 400000 975000
0079 200000 950000
0080 >;
0081 #cooling-cells = <2>; /* min followed by max */
0082 };
0083 };
0084
0085 soc: soc {
0086 sysram: sram@2020000 {
0087 compatible = "mmio-sram";
0088 reg = <0x02020000 0x20000>;
0089 #address-cells = <1>;
0090 #size-cells = <1>;
0091 ranges = <0 0x02020000 0x20000>;
0092
0093 smp-sram@0 {
0094 compatible = "samsung,exynos4210-sysram";
0095 reg = <0x0 0x1000>;
0096 };
0097
0098 smp-sram@1f000 {
0099 compatible = "samsung,exynos4210-sysram-ns";
0100 reg = <0x1f000 0x1000>;
0101 };
0102 };
0103
0104 pd_lcd1: power-domain@10023ca0 {
0105 compatible = "samsung,exynos4210-pd";
0106 reg = <0x10023CA0 0x20>;
0107 #power-domain-cells = <0>;
0108 label = "LCD1";
0109 };
0110
0111 l2c: cache-controller@10502000 {
0112 compatible = "arm,pl310-cache";
0113 reg = <0x10502000 0x1000>;
0114 cache-unified;
0115 cache-level = <2>;
0116 prefetch-data = <1>;
0117 prefetch-instr = <1>;
0118 arm,tag-latency = <2 2 1>;
0119 arm,data-latency = <2 2 1>;
0120 };
0121
0122 mct: timer@10050000 {
0123 compatible = "samsung,exynos4210-mct";
0124 reg = <0x10050000 0x800>;
0125 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
0126 clock-names = "fin_pll", "mct";
0127 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0128 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0129 <&combiner 12 6>,
0130 <&combiner 12 7>,
0131 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0132 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0133 };
0134
0135 watchdog: watchdog@10060000 {
0136 compatible = "samsung,s3c6410-wdt";
0137 reg = <0x10060000 0x100>;
0138 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0139 clocks = <&clock CLK_WDT>;
0140 clock-names = "watchdog";
0141 };
0142
0143 clock: clock-controller@10030000 {
0144 compatible = "samsung,exynos4210-clock";
0145 reg = <0x10030000 0x20000>;
0146 #clock-cells = <1>;
0147 };
0148
0149 pinctrl_0: pinctrl@11400000 {
0150 compatible = "samsung,exynos4210-pinctrl";
0151 reg = <0x11400000 0x1000>;
0152 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0153 };
0154
0155 pinctrl_1: pinctrl@11000000 {
0156 compatible = "samsung,exynos4210-pinctrl";
0157 reg = <0x11000000 0x1000>;
0158 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0159
0160 wakup_eint: wakeup-interrupt-controller {
0161 compatible = "samsung,exynos4210-wakeup-eint";
0162 interrupt-parent = <&gic>;
0163 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0164 };
0165 };
0166
0167 pinctrl_2: pinctrl@3860000 {
0168 compatible = "samsung,exynos4210-pinctrl";
0169 reg = <0x03860000 0x1000>;
0170 };
0171
0172 g2d: g2d@12800000 {
0173 compatible = "samsung,s5pv210-g2d";
0174 reg = <0x12800000 0x1000>;
0175 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0176 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
0177 clock-names = "sclk_fimg2d", "fimg2d";
0178 power-domains = <&pd_lcd0>;
0179 iommus = <&sysmmu_g2d>;
0180 };
0181
0182 ppmu_acp: ppmu@10ae0000 {
0183 compatible = "samsung,exynos-ppmu";
0184 reg = <0x10ae0000 0x2000>;
0185 status = "disabled";
0186 };
0187
0188 ppmu_lcd1: ppmu@12240000 {
0189 compatible = "samsung,exynos-ppmu";
0190 reg = <0x12240000 0x2000>;
0191 clocks = <&clock CLK_PPMULCD1>;
0192 clock-names = "ppmu";
0193 status = "disabled";
0194 };
0195
0196 sysmmu_g2d: sysmmu@12a20000 {
0197 compatible = "samsung,exynos-sysmmu";
0198 reg = <0x12A20000 0x1000>;
0199 interrupt-parent = <&combiner>;
0200 interrupts = <4 7>;
0201 clock-names = "sysmmu", "master";
0202 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
0203 power-domains = <&pd_lcd0>;
0204 #iommu-cells = <0>;
0205 };
0206
0207 sysmmu_fimd1: sysmmu@12220000 {
0208 compatible = "samsung,exynos-sysmmu";
0209 interrupt-parent = <&combiner>;
0210 reg = <0x12220000 0x1000>;
0211 interrupts = <5 3>;
0212 clock-names = "sysmmu", "master";
0213 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
0214 power-domains = <&pd_lcd1>;
0215 #iommu-cells = <0>;
0216 };
0217
0218 bus_dmc: bus-dmc {
0219 compatible = "samsung,exynos-bus";
0220 clocks = <&clock CLK_DIV_DMC>;
0221 clock-names = "bus";
0222 operating-points-v2 = <&bus_dmc_opp_table>;
0223 status = "disabled";
0224 };
0225
0226 bus_acp: bus-acp {
0227 compatible = "samsung,exynos-bus";
0228 clocks = <&clock CLK_DIV_ACP>;
0229 clock-names = "bus";
0230 operating-points-v2 = <&bus_acp_opp_table>;
0231 status = "disabled";
0232 };
0233
0234 bus_peri: bus-peri {
0235 compatible = "samsung,exynos-bus";
0236 clocks = <&clock CLK_ACLK100>;
0237 clock-names = "bus";
0238 operating-points-v2 = <&bus_peri_opp_table>;
0239 status = "disabled";
0240 };
0241
0242 bus_fsys: bus-fsys {
0243 compatible = "samsung,exynos-bus";
0244 clocks = <&clock CLK_ACLK133>;
0245 clock-names = "bus";
0246 operating-points-v2 = <&bus_fsys_opp_table>;
0247 status = "disabled";
0248 };
0249
0250 bus_display: bus-display {
0251 compatible = "samsung,exynos-bus";
0252 clocks = <&clock CLK_ACLK160>;
0253 clock-names = "bus";
0254 operating-points-v2 = <&bus_display_opp_table>;
0255 status = "disabled";
0256 };
0257
0258 bus_lcd0: bus-lcd0 {
0259 compatible = "samsung,exynos-bus";
0260 clocks = <&clock CLK_ACLK200>;
0261 clock-names = "bus";
0262 operating-points-v2 = <&bus_leftbus_opp_table>;
0263 status = "disabled";
0264 };
0265
0266 bus_leftbus: bus-leftbus {
0267 compatible = "samsung,exynos-bus";
0268 clocks = <&clock CLK_DIV_GDL>;
0269 clock-names = "bus";
0270 operating-points-v2 = <&bus_leftbus_opp_table>;
0271 status = "disabled";
0272 };
0273
0274 bus_rightbus: bus-rightbus {
0275 compatible = "samsung,exynos-bus";
0276 clocks = <&clock CLK_DIV_GDR>;
0277 clock-names = "bus";
0278 operating-points-v2 = <&bus_leftbus_opp_table>;
0279 status = "disabled";
0280 };
0281
0282 bus_mfc: bus-mfc {
0283 compatible = "samsung,exynos-bus";
0284 clocks = <&clock CLK_SCLK_MFC>;
0285 clock-names = "bus";
0286 operating-points-v2 = <&bus_leftbus_opp_table>;
0287 status = "disabled";
0288 };
0289
0290 bus_dmc_opp_table: opp-table1 {
0291 compatible = "operating-points-v2";
0292 opp-shared;
0293
0294 opp-134000000 {
0295 opp-hz = /bits/ 64 <134000000>;
0296 opp-microvolt = <1025000>;
0297 };
0298 opp-267000000 {
0299 opp-hz = /bits/ 64 <267000000>;
0300 opp-microvolt = <1050000>;
0301 };
0302 opp-400000000 {
0303 opp-hz = /bits/ 64 <400000000>;
0304 opp-microvolt = <1150000>;
0305 opp-suspend;
0306 };
0307 };
0308
0309 bus_acp_opp_table: opp-table2 {
0310 compatible = "operating-points-v2";
0311 opp-shared;
0312
0313 opp-134000000 {
0314 opp-hz = /bits/ 64 <134000000>;
0315 };
0316 opp-160000000 {
0317 opp-hz = /bits/ 64 <160000000>;
0318 };
0319 opp-200000000 {
0320 opp-hz = /bits/ 64 <200000000>;
0321 };
0322 };
0323
0324 bus_peri_opp_table: opp-table3 {
0325 compatible = "operating-points-v2";
0326 opp-shared;
0327
0328 opp-5000000 {
0329 opp-hz = /bits/ 64 <5000000>;
0330 };
0331 opp-100000000 {
0332 opp-hz = /bits/ 64 <100000000>;
0333 };
0334 };
0335
0336 bus_fsys_opp_table: opp-table4 {
0337 compatible = "operating-points-v2";
0338 opp-shared;
0339
0340 opp-10000000 {
0341 opp-hz = /bits/ 64 <10000000>;
0342 };
0343 opp-134000000 {
0344 opp-hz = /bits/ 64 <134000000>;
0345 };
0346 };
0347
0348 bus_display_opp_table: opp-table5 {
0349 compatible = "operating-points-v2";
0350 opp-shared;
0351
0352 opp-100000000 {
0353 opp-hz = /bits/ 64 <100000000>;
0354 };
0355 opp-134000000 {
0356 opp-hz = /bits/ 64 <134000000>;
0357 };
0358 opp-160000000 {
0359 opp-hz = /bits/ 64 <160000000>;
0360 };
0361 };
0362
0363 bus_leftbus_opp_table: opp-table6 {
0364 compatible = "operating-points-v2";
0365 opp-shared;
0366
0367 opp-100000000 {
0368 opp-hz = /bits/ 64 <100000000>;
0369 };
0370 opp-160000000 {
0371 opp-hz = /bits/ 64 <160000000>;
0372 };
0373 opp-200000000 {
0374 opp-hz = /bits/ 64 <200000000>;
0375 opp-suspend;
0376 };
0377 };
0378 };
0379 };
0380
0381 &cpu_alert0 {
0382 temperature = <85000>; /* millicelsius */
0383 };
0384
0385 &cpu_alert1 {
0386 temperature = <100000>; /* millicelsius */
0387 };
0388
0389 &cpu_alert2 {
0390 temperature = <110000>; /* millicelsius */
0391 };
0392
0393 &cpu_thermal {
0394 polling-delay-passive = <0>;
0395 polling-delay = <0>;
0396 thermal-sensors = <&tmu 0>;
0397 };
0398
0399 &gic {
0400 cpu-offset = <0x8000>;
0401 };
0402
0403 &camera {
0404 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
0405 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
0406 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
0407 };
0408
0409 &combiner {
0410 samsung,combiner-nr = <16>;
0411 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0412 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0413 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0414 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0415 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0416 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0417 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0418 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0419 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0420 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0421 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0422 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0423 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0424 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0425 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0426 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0427 };
0428
0429 &fimc_0 {
0430 samsung,pix-limits = <4224 8192 1920 4224>;
0431 samsung,mainscaler-ext;
0432 samsung,cam-if;
0433 };
0434
0435 &fimc_1 {
0436 samsung,pix-limits = <4224 8192 1920 4224>;
0437 samsung,mainscaler-ext;
0438 samsung,cam-if;
0439 };
0440
0441 &fimc_2 {
0442 samsung,pix-limits = <4224 8192 1920 4224>;
0443 samsung,mainscaler-ext;
0444 samsung,lcd-wb;
0445 };
0446
0447 &fimc_3 {
0448 samsung,pix-limits = <1920 8192 1366 1920>;
0449 samsung,rotators = <0>;
0450 samsung,mainscaler-ext;
0451 samsung,lcd-wb;
0452 };
0453
0454 &gpu {
0455 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0456 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0457 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0458 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0459 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0460 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0461 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0462 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0463 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0464 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0465 interrupt-names = "gp",
0466 "gpmmu",
0467 "pp0",
0468 "ppmmu0",
0469 "pp1",
0470 "ppmmu1",
0471 "pp2",
0472 "ppmmu2",
0473 "pp3",
0474 "ppmmu3";
0475 operating-points-v2 = <&gpu_opp_table>;
0476
0477 gpu_opp_table: opp-table {
0478 compatible = "operating-points-v2";
0479
0480 opp-160000000 {
0481 opp-hz = /bits/ 64 <160000000>;
0482 opp-microvolt = <950000>;
0483 };
0484 opp-267000000 {
0485 opp-hz = /bits/ 64 <267000000>;
0486 opp-microvolt = <1050000>;
0487 };
0488 };
0489 };
0490
0491 &mdma1 {
0492 power-domains = <&pd_lcd0>;
0493 };
0494
0495 &mixer {
0496 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
0497 "sclk_mixer";
0498 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
0499 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
0500 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
0501 };
0502
0503 &pmu {
0504 interrupts = <2 2>, <3 2>;
0505 interrupt-affinity = <&cpu0>, <&cpu1>;
0506 status = "okay";
0507 };
0508
0509 &pmu_system_controller {
0510 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
0511 "clkout4", "clkout8", "clkout9";
0512 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
0513 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
0514 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
0515 #clock-cells = <1>;
0516 };
0517
0518 &rotator {
0519 power-domains = <&pd_lcd0>;
0520 };
0521
0522 &sysmmu_rotator {
0523 power-domains = <&pd_lcd0>;
0524 };
0525
0526 &tmu {
0527 compatible = "samsung,exynos4210-tmu";
0528 clocks = <&clock CLK_TMU_APBIF>;
0529 clock-names = "tmu_apbif";
0530 };
0531
0532 #include "exynos4210-pinctrl.dtsi"
